Claims
- 1. An active matrix board, comprising:
- a matrix of pixel electrodes each having a thin-film transistor element connected thereto on an insulating substrate;
- source lines connected to each thin-film transistor element; and
- gate lines operatively coupled to said pixel electrodes wherein each gate line comprises:
- i. a first gate line formed of a low resistance metal and located outside of the areas covered by said pixel electrodes;
- ii. a second gate line fomred of a metal having a substantially higher resistance to etchants than does said first gate line, said second gate line completely covering said first gate line; and
- iii. said second gate line comprising a plurality of projecting parts, each projecting part being an addition capacity electrode extending entirely across the width of the pixel electrode.
- 2. An active matrix board as in claim 1 wherein said gate lines are scan lines.
- 3. An active matrix board as in claim 1 wherein said low-resistance metal is one metal selected from a group consisting of Al, Mo and W.
- 4. An active matrix board as in claims 1 wherein said metal having a substantially higher resistance to etchants is an anodizable metal.
- 5. An active matrix board according to claim 1, wherein said second scan line is covered with an anodized insulating layer.
- 6. An active matrix board, comprising:
- a matrix of pixel electrodes each having a thin-film transistor element connected thereto on an insulating substrate;
- source lines connected to each thin-film transistor element; and
- gate lines operatively coupled to said pixel electrodes wherein each gate line comprises:
- i. a first gate line formed of a low resistance metal and located outside of the areas covered by said pixel electrodes;
- ii. a second gate line formed of a metal having a substantially higher resistance at least to etchants used for patterning said pixel electrodes than does said first gate line, said second gate line completely covering said first gate line; and
- iii. said second gate line including a plurality of projecting parts each comprising addition capacity electrodes extending completely across the width of the pixel electrodes,
- wherein an insulating layer is formed between said pixel electrode and said second gate line, and
- wherein said second gate line comprises another projecting part forming a gate electrode for a thin-film transistor of another pixel electrode next to said pixel electrode.
Priority Claims (1)
Number |
Date |
Country |
Kind |
1-209401 |
Aug 1989 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 08/060,511, filed May 12, 1993, which was a continuation of application Ser. No. 07/857,724, filed Mar. 26, 1992, which was a continuation of application Ser. No. 07/564,287, filed Aug. 8, 1990, all abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4843438 |
Koden et al. |
Jun 1989 |
|
4955697 |
Tsukada et al. |
Sep 1990 |
|
Foreign Referenced Citations (1)
Number |
Date |
Country |
0288011 |
Oct 1988 |
EPX |
Non-Patent Literature Citations (1)
Entry |
Patent Abstract of Japan, vol. 10, No. 351 (P-520) [2407], 27th Nov. 1986; & JP-A-61 151 516 (Seiko) Oct. 7, 1986. |
Continuations (3)
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Number |
Date |
Country |
Parent |
60511 |
May 1993 |
|
Parent |
857724 |
Mar 1992 |
|
Parent |
564287 |
Aug 1990 |
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