The present invention relates to a switching signal generator, and more particularly to a switching signal generator applied in an active matrix display. The present invention also relates to an active matrix display comprising a switching signal generator.
The great progress has been made in designing and manufacturing computer equipment. The higher speed and better performance of various kinds of processors increase our dependence on computers. Moreover, computer-related skills are essential to students or workers. A monitor is the direct communication medium between a user and a computer. All the information that the user needs from the computer are displayed on the monitor. Hence, not only the speed and the performance of the computer, but also the quality of the monitor should be paid attention to.
In the past, increasing the screen size of the cathode ray tube (CRT) monitor indicates that large volume of the monitor is inevitable. It troubles the user for placing the monitor. Moreover, the radiation of the conventional monitor is harmful to human body. A liquid crystal display (LCD) is developed to solve these problems.
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The thin film transistor array 100, consisting of a plurality of display cells E11˜Emn arranged in columns and rows, is the display region of the liquid crystal display.
The scan shift register 110 consists of a plurality of register units A1˜Am interconnected in series. Each register unit A1˜Am is associated with one of the scan lines. The scan shift register 110 sequentially enables the scan lines to control the ON state of the thin film transistors 1002 row by row.
The data shift register 105 also consists of a plurality of register units B1˜Bn interconnected in series. Each register unit B1˜Bn is associated with one of the data switches C1˜Cn. The data shift register 105 can sequentially switch on data switches C1˜Cn. Each data switch C1˜Cn includes N thin film transistors (only one thin film transistor is shown in
The N-bit digital-to-analog converters D1˜Dn are correspondingly coupled to the data switches C1˜Cn. Each N-bit digital-to-analog converter D1˜Dn receives the digital video signals from the N-bit data line (Din) and converts them into analog video signals when the corresponding data switch C1˜Cn is switched on. Then, the analog video signals are inputted to the corresponding data line of the thin film transistor array 100.
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Next, the data switch C2 is switched on by the register unit B2 of the data shift register 105 when a second group of digital video signals are inputted from N-bit data line (Din). Hence, the second group of digital video signals can pass through the data switch C2, and then are converted into the second group of analog video signals by the N-bit digital-to-analog converter D2. That it, the second group of analog video signals will get into the data line connecting the display cells E12˜Em2. Meanwhile, it is still the scan line connecting the display cells E11˜E1n being driven. Hence, the second group analog video signals are stored in the display cell E12 corresponding to the first row scan line and the second column data line.
The data shift register 105 then sequentially switches on all the following data switches C3˜Cn, and the display cells E13˜E1n in the first row store corresponding groups of analog video signals. After all the display cells E11˜E1n in the first row have stored respective analog video signals, the register unit A2 of the scan shift register 110 is enabled to drive the scan line connecting the display cells E21˜E2n. The analog video signals are stored into the display cells E21˜E2n of the thin film transistor array 100 by means as described above. After the scan shift register 110 enables all the scan lines in turn, all the display cells E11˜Emn of the thin film transistor array 100 have stored analog video signals. Hence, the liquid crystal display shows a full image page on screen.
The analog video signals in every display cell E11˜Emn of the thin film transistor array 100 are refreshed frequently, and that is, the liquid crystal display refreshes images very quickly. What the user see on screen are dynamic images. Certainly, a static image is shown when the analog video signals are refreshed with the same data. Flickers may occur on the liquid crystal display if the refresh rate is too slow.
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An object of the present invention is to provide a switching signal generator for use in the driving circuit of an active matrix display, which simplifies the circuitry of the active matrix display.
Another object of the present invention is to provide an active matrix display having simplified circuit structure.
A first aspect of the present invention relates to a switching signal generator for use with a plurality of switches of an active matrix display. The switching signal generator comprises a plurality of delay units electrically connected to the plurality of switches, and generating a plurality of target switching signals in response to a source switching signal for controlling signals to be outputted to an active matrix portion of the active matrix display via the plurality of switches. There is a constant phase shift between every two successive target switching signals, thereby switching on the plurality of switches and outputting the signals to the active matrix portion in sequence.
In an embodiment, the active matrix portion includes a thin film transistor (TFT) array interconnected by a plurality of scan lines and data lines.
Preferably, the first one of the delay units receives the source switching signal, and each of the following delay units receives one of the target switching signals outputted from a preceding one of the delay units.
In an embodiment, the switching signal generator includes a first generator portion generating a first portion of the plurality of target switching signals in response to the source switching signal for controlling signals to be sequentially outputted to data lines of the active matrix display via a first portion of the plurality of switches, and a second generator portion generating a second portion of the plurality of target switching signals in response to the source switching signal for controlling signals to be sequentially outputted to scan lines of the active matrix display via a second portion of the plurality of switches
If the signals outputted via the first portion of the plurality of switches are digital video signals, they are preferably converted into analog video signals by a plurality of digital-to-analog converters of the active matrix display before being outputted to the data lines.
A second aspect of the present invention relates to a switching signal generator for use in an active matrix display. The switching signal generator comprises a first generator portion receiving a source switching signal and generating a set of first target switching signals, and a second generator portion receiving the source switching signal and generating a set of second target switching signals. There is a first phase shift between every two of the first target switching signals and there is a second phase difference between every two of the second target switching signals for switching on active matrix units of the active matrix display in sequence.
For example, the active matrix units of the active matrix display comprise a thin film transistor array interconnected by scan lines and data lines.
Preferably, the first generator portion comprises a plurality of delay units, the first one of the delay units receives and delays the source switching signal, and each of the following delay units receives and delays one of the target switching signals outputted from a preceding one of the delay units.
A third aspect of the present invention relates to an active matrix display, comprising an active matrix portion comprising a plurality of active matrix units arranged in columns and rows; a first switch portion comprising a plurality of first switches which are switched on in response to respective first switching signals to allow first signals to be outputted to the active matrix units; and a first switching signal generator sequentially asserting the first switching signals in response to a source switching signal, thereby switching on the first switches and allowing the first signals to be outputted to the active matrix units in sequence.
Preferably, the first switching signal generator comprises a plurality of delay units interconnected in series for asserting the first switching signals in sequence.
Preferably, the active matrix display further comprises a second switch portion comprising a plurality of second switches which are switched on in response to respective second switching signals to allow second signals to be outputted to the active matrix units; and a second switching signal generator sequentially asserting the second switching signals in response to the source switching signal, thereby switching on the second switches and allowing the second signals to be outputted to the active matrix units in sequence.
Preferably, the second switching signal generator comprises a plurality of delay units interconnected in series for asserting the second switching signals in sequence.
In an embodiment, the first signals are outputted to the active matrix units via data lines, and the second signals are outputted to the active matrix units via scan lines.
If the first signals are digital video signals, the active matrix display preferably further comprises a plurality of digital-to-analog converters electrically connected between the first switches and the active matrix units for converting the digital video signals passing through the first switches into analog video signals.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
a) is a circuit block diagram schematically showing a prior art liquid crystal display;
b) is a schematic circuit diagram showing a display cell of the liquid crystal display of
c) is a schematic circuit diagram showing a shift register in
a) and 3(b) are waveform diagrams showing the phase relations among a source switching signal and target switching signals generated by the first and second, respectively, according to the present invention.
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The first switching signal generator 24 includes at least one delay device. The delay device consists of n delay units H1˜Hn interconnected in series. The delay units H1˜Hn are connected to respective data switches C1˜Cn. Responsive to receiving a source switching signal (ST), the delay units H1˜Hn provide the data switches C1˜Cn with corresponding target switching signals S1˜Sn. There is a constant phase shift between every two successive target switching signals. Therefore, the data switches C1˜Cn are turned on in turn. That is, the digital video signals in the N-bit data line (Din) pass through corresponding data switch C1˜Cn in sequence.
The data switches C1˜Cn, connected to the delay units H1˜Hn, N-bit data line (Din), and N-bit digital-to-analog converters D1˜Dn, receive the digital video signals from the data line (Din) and transmit the digital video signals to corresponding N-bit digital-to-analog converters D1˜Dn in response to corresponding target switching signals. The N-bit digital-to-analog converters then convert the received digital video signals into analog video signals which will be provided for the corresponding data line.
In
In the same manner, the second switching signal generator 25 includes at least one delay device. The delay device consists of m delay units I1˜Im interconnected in series. The delay units I1˜Im are connected to respective scan switches G1˜Gm. Responsive to receiving a source switching signal (ST), the delay units I1˜Im provide the scan switches G1˜Gm with corresponding target switching signals T1˜Tm. There is a constant phase shift between every two successive target switching signals. Therefore, the scan switches G1˜Gm are switched on one by one at an interval. The scan lines are driven in turn to switch on the thin film transistors of display cells in the associated row.
In
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The delay unit H2 receives the first target switching signal S1 and generates a second target switching S2 having a phase shift later than the first target switching signal S1. Therefore, the second data switch C2, following the first data switch C1, is switched on. Hence, the second group of digital video signals from the N-bit data line (Din) passes through the second data switch C2, and then are converted into the second group of analog video signals by the N-bit digital-to-analog converter D2. Next, the second group of analog video signals get into the second data line connecting the display cells E12˜Em2. At the same time, it is still the first scan line connecting the display cells E11˜E1n is driven. Hence, the second group analog video signals are stored in the display cell E12 corresponding to the first scan line and the second data line.
In the same manner, the switching signals S3˜Sn from the other delay units H3˜Hn switch on the data switches C3˜Cn in sequence to have the display cells E13˜E1n store corresponding groups of analog video signals. After the display cells E11˜E1n in the first row are stored with the analog video signals, the second delay unit I2 of the second switching signal generator 25 provides the second scan switch G2 with a second target switching signal T2 to drive the second scan line connecting the display cells E21˜E2n. The analog video signals are stored into the display cells E21˜E2n in the second row of the thin film transistor array 23 by means as described above. After the second switching generator 25 completes driving all the scan lines, all the display cells E11˜Emn of the thin film transistor array 23 store analog video signals. Hence, the liquid crystal display shows a full image page on screen.
In conclusion, the switching signal generators 24 and 25 are used to substitute for the prior art data shift register and scan shift register. According to the present invention, the same start pulse signal (source switching signal) is used to control the ON/OFF states of the scan switches for driving the scan lines and the same start pulse signal is used to control the ON/OFF states of the data switches for driving the data lines. Thus, the number of pins of the circuit chips is minimized. It also simplifies the circuitry of the liquid crystal display.
While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
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