1. Field of the Invention
The present invention relates to a pixel circuit, and more particularly, to an active matrix organic light emitting diode (AMOLED) pixel circuit that can be implemented with amorphous silicon thin film transistors.
2. Description of the Prior Art
Several conventional active matrix drive schemes that have been used in liquid crystal display (LCDs) and are being investigated for use in AMOLEDs. These schemes include, for example, (1) an area ratio gray scale (ARG) method (M. Kimura, et al, Seiko Epson Corp., Japan, AMLDC2000), (2) a pulse width modulation method (S. Miyaguchi, et al, J. of SID, 7(3), 1999, p. 221–226), and (3) an amplitude modulation method, as used in direct view active matrix liquid crystal displays (AMLCDs).
A display-driving scheme for an array of pixels is dependent on pixel schematic, a computer aided design (CAD) layout and a manner in which control lines are brought out of the array. For example, a prior art AMOLED pixel structure having two NMOS transistors provides a current from a driver transistor that drives an OLED being switched, where the drain of the driver transistor is brought out of the array as a column line. In such a layout, the column line that supplies the current (i.e., the supply line) cannot be scanned in sync with rows lines, but must either be OFF until all the row lines are scanned or must be ON before the row lines are scanned. This aspect, as well as the layout of other control signals (e.g., whether they are brought out as row, column or common lines), dictate possible driving options. Active matrix and OLED technology, together with pixel design, dictate which driving scheme produces a least amount, or an acceptable level of, front-of-screen artifacts. For example, there is a common belief among those skilled in the display art that amorphous silicon (a-Si) thin film transistors (TFTs) are not a suitable technology for driving an OLED display, even though a-Si TFT technology is by choice and sales the mainstream technology used in AMLCDs today. Thus, conventional AMOLED displays are implemented with low temperature polysilicon (LTPS) TFT technology, and to date, no one has implemented an a-Si TFT OLED display. Some of the cited concerns are (1) an insufficient low level of drive current produced by an a-Si TFT (M. Stewart et al, IEEE IEDM, 1998, pp. 871–874; LG, SID 2001), which stems from an inherently low mobility (typically<1 cm2/V/sec and, (2) threshold voltage instabilities (J. Kanicki et al, SID 20th IDRC Proceedings, Sept. 25–28, Palm Beach, Fla., pp. 354–358).
Several references show implementations and provide discussions of an active matrix having two TFTs per pixel (T. Sasaoka et al, 2001 SID International Symposium Digest (Sony); M. Johnson et al, 2000 International Display Workshop, pp 235–238; S. Tam et al, 1999 International Display Workshop, AMD3-2, M. Kimura et al, Proceedings of International Display Workshop 1999, AMD3-1). In these references, the technology is poly-Si TFT, and the drain of all Q2 TFTs in each pixel are tied together, brought out of the active matrix as a column line, and tied to a DC voltage supply as shown in
The present invention provides for a pixel circuit having a minimal number of TFTs and capacitors, and a minimal number of control lines, while providing (1) a data voltage write to the pixel, and (2) a threshold voltage independent voltage-to-current conversion followed by pixel illumination.
Another feature of the present invention is to provide a driving technique for an active matrix OLED display using circuit having two TFTs per pixel.
Another feature of the present invention is to provide a pixel circuit compatible with a voltage amplitude modulated data driver and a pulse width modulated driver.
Another feature of the present invention is to provide a driving scheme that (1) minimizes an initial TFT threshold voltage shift, especially in a current drive TFT, (2) minimizes stress effects of the TFTs that results in a time dependent threshold voltage shift, especially in the current drive TFT, (3) provides reverse polarity and alternating current (AC) voltages on TFT terminals to prolong TFT lifetime, and (4) provides quick data voltage level charging of the pixel.
An additional aspect of the present invention is to provide an OLED architecture that facilitates reverse bias of a scanned OLED array. Since an OLED is a thin film device, charge can build up when driven normally in a forward bias manner. Reversing the voltage across the OLED can remove built-up charge and help to maintain low voltage operation.
Additionally, the present invention (1) maximizes pixel aperture area, (2) provides a pixel circuit and layout that can be employed for either a bottom emission AMOLED display or a top emission AMOLED display. Furthermore, the present invention maximizes manufacturing yield by providing a simple process and high yielding pixel circuitry and layout with low-cost fabrication processing.
One embodiment of the present invention is a circuit for driving a current mode light modulating device. The circuit includes (a) a capacitor for storing a data voltage, (b) a field effect transistor (FET) controlled by a signal on a scan line, for coupling the data voltage from a signal line to the capacitor, and (c) a current source, controlled by the stored data voltage, for driving the device with current provided from a power line. The power line is in a plane that is geometrically parallel to a plane within which the scan line is located.
Another embodiment of the present invention is an AMOLED display having a plurality of pixel circuits in a row. Each of the pixel circuits includes (a) a capacitor for storing a data voltage, (b) a first field effect transistor (FET) controlled by a signal on a scan line, for coupling the data voltage from a signal line to the capacitor, and (c) a second FET, controlled by the stored data voltage, for driving an AMOLED in the display with current provided from a power line. The power line is in a plane that is geometrically parallel to a plane within which the scan line is located, and the power line and the scan line are connected to each of the pixel circuits in the row.
a is a graph of a driving scheme simulation showing waveform V(1).
b is a graph of a driving scheme simulation showing waveform V(2).
c is a graph of a driving scheme simulation showing waveform V(3).
d is a graph of a driving scheme simulation showing waveform V(4).
e is a graph of a driving scheme simulation showing waveform V(5).
f is a graph of a driving scheme simulation showing waveform V(132).
g is a schematic of a pixel circuit being driven in accordance with the present invention.
a is a graph of drain current versus gate bias, and
a is a graph of drain current versus bias, and
a is a semilog plot, and
The present invention relates to an AMOLED pixel circuit having four modes of operation, namely (1) fast data sample and hold mode, (2) sufficient drive (illumination) current mode, (3) TFT threshold voltage compensation mode, and (4) OLED compensation mode. The circuit is configured with a minimal number of components thus allowing for a favorable aperture ratio.
The pixel circuit uses a-Si technology and incorporates several features: (1) the drains of driver transistor Q2 in a row, or group of rows, are tied together; (2) the power lines are brought out of the active matrix as a row line versus the Vsupply lines that are brought out as column lines, and (3) Vdata is a pulsed signal. The present invention offers a simple implementation of a pixel circuit with only a few TFTs, and may provide a defacto pixel adaptation by a-Si TFT-OLED display makers.
Data transfer transistor Q1 and driver transistor Q2 are connected to a common node. Storage capacitor Cs1 is connected between the common node and power driver line 315.
Pixel circuit EL1 drives a current mode light modulating device, e.g., an OLED 305. Other examples of current mode light modulating devices include inorganic light emitting diodes using electroluminescent phosphor and field emission devices.
Scan line 320 is a conductor for a voltage Vscan, which is typically supplied by a row driver (not shown). Vscan is also referred to herein as V(132), and further identified by a row number (e.g., 1, 2, 3 . . . N). In an embodiment of a full display, scan line 320 is connected to a plurality of pixel circuits in a row of the display. A scan line is provided for each row of the display. That is, a first scan line for the first row, a second scan line for the second row, etc.
Power driver line 315 is a conductor for a voltage Vsupply, which is also typically supplied by a row driver (not shown). In an embodiment of a full display, power driver line 315 is connected to a plurality of pixel circuits in a row of the display. A power driver line is provided for each row of the display. That is, a first power driver line for the first row, a second power driver line for the second row, etc.
Note that Vsupply is an AC waveform, In a physical embodiment of circuit 300, power driver line 315 is preferably in a plane that is geometrically parallel to, and electrically isolated from, a plane within which scan line 320 is located. Several favorable consequences result from this configuration. For example:
The row driver for Vscan and the row driver for Vsupply may reside on a single row driver chip or may reside on separate row driver chips. Power driver line 315 is contemplated as providing a higher current than scan line 320.
Signal line 325 is a conductor for a voltage Vdata that represents a gray level voltage amplitude. Vdata is supplied by a data driver (not shown).
Common cathode 310 is a conductor for a voltage Vcathode, which is an AC waveform. Each of pixel circuits EL1–EL4 drive an OLED, and Vcathode is common to one side of the OLED for each of EL1–EL4. In a full AMOLED array, Vcathode may be common to all of the AMOLEDs in the array, or to a subset of AMOLEDs in the array. For example, such a subset can encompass one row of pixel circuits or several rows of pixel circuits. An advantage of such a subset by row grouping is that simultaneous addressing of an upper portion and a lower portion of the AMOLED array provides a quicker addressing of the full array than can be accomplished by addressing single rows in sequence.
Although circuit 300 is shown with a common cathode configuration, i.e., the cathode of OLED 305 is tied to common cathode 310, it could have a common anode configuration. That is, rather than having the cathodes of the OLEDs connected together as shown in
Q1 operates as a pixel data write transfer switch from a gray level voltage Vdata on signal line 325 to a gate node of driver Q2 when voltage Vscan on scan line 320 is sufficiently positive. Driver transistor Q2 operates as a voltage follower to drive OLED 305. Current through OLED 305 is sourced from voltage supply Vsupply, connected to power driver line 315. As OLED 305 is driven, a threshold voltage of driver transistor Q2 changes. Voltage across OLED 305 is equal to Vsupply-Vcathode-Vgs(t), where Vcathode is a voltage on common cathode 310, and Vgs(t) is a time dependent gate-to-source voltage of Q2. Current through OLED 305 and driver transistor Q2 is proportional to (Vgs−Vt)2, where Vt is the threshold voltage of Q2. In addition, driver Q2 is biased in saturation (Vds>Vgs−Vti), where Vds is the TFT drain-to-source voltage, and Vti is the TFT initial threshold voltage before biasing induces additional TFT threshold voltage shifts. Such biasing results in a much reduced threshold voltage shift (2× to 20×) as compared to the same gate biasing of Q2 but with a smaller Vds such as in the linear region (Vds<Vgs−Vti).
a is a graph of drain current versus gate bias for TFT with channel width-to-length ratio (W/L) of 50/7, driven in linear regime (Vg=25 V, Vd=1 V).
b shows stress current versus stress time. Stress current in
a is a graph of drain current versus bias for TFT with W/L of 50/7 driven in saturation regime (Vg=Vd=10 V).
b shows stress current versus stress time. Stress current in
a (saturation region biasing) shows approximately 4 times less of a driver Q2 threshold voltage shift compared to
As a result of biasing driver Q2 in the saturation region, OLED 305 voltage and current will change much less than if driver Q2 where biased in the linear region, such as is the biasing for AMLCDs. Additional consideration must be taken into account for amorphous silicon operating voltages for the AMOLED displays of the present invention since the TFT bias is applied for a substantially larger percentage of time, i.e., duty cycles up to 100%, compared to AMLCD duty cycles of less than 1%. To further reverse any induced threshold voltage shift, a voltage of Vgs<Vti can be placed onto driver transistor Q2 as well as onto data transfer transistor Q1. Furthermore, an ability of driver transistor Q2 to faithfully reproduce a gray level current depends on a slope of a saturation region in the output characteristics of driver transistor Q2. In practice, the longer the Q2 channel, the smaller the source-drain resistance to channel resistance ratio, and hence the smaller the output source-drain current change for a given dVt, the change in threshold voltage. The voltages on the Vsupply, Vcathode, scan line and Cs1 are switched to different voltages in time to reduce or compensate for threshold voltage changes. Vcathode is the common supply applied to the common cathode electrode of 310, and scan line is the conductive line connecting the gates of Q1 on a row.
Thus, with reference to
For simplicity, voltage waveform Vdata 415 is not shown, but understood to be of valid data when Vscan 420 is high and turning Q1 on. Shown is a sequential row scan with V(132)-1 through V(132)-N being a double pulse waveform per display subframe. The first pulse defines the pixel data write operation to the gate node of driver Q2, and the second pulse writes the driver Q2 gate compensation level. Coinciding with the sequential row scan of voltage pulse V(132)-1 through V(132)-N is either the rising edge or falling edge of V(1)-1 through (1)-N, respectively. The rising edge establishes the beginning of OLED 310 illumination, where the voltage difference between V(1)-1 through V(1)-N and v(4) establish the bias across driver Q2 and OLED 310 needed for illumination of OLED 310. The falling edge establishes the end of illumination of OLED 310. Note that the row controlled V(1)-1 through V(1)-N makes it possible to do row-at-a-time addressing and illumination, and row independent illumination control. When the falling edge of V(1)-1 through V(1)-N coincides with the rising edge of V(132)-1 through V(132)-N, respectively, the start of driver Q2 or OLED 310 compensation is initiated. Driver Q2 compensation is through reverse biasing the gate to source and the gate to drain. Compensation benefits may result from an increase in the lifetime by threshold voltage shift decrease. Additional lifetime benefit may be derived by biasing the drain voltage lower than the source voltage, as is implemented when V(4) is high and V(1) is low. Typical voltage waveform amplitudes for a-Si TFT active matrix are shown. When V(4) is high and V(1)-1 through V(1)-N is low, the OLED 305 compensation takes place by allowing charge detrapping to take place due to the reverse biased OLED 305.
When a capacitor charges to a voltage, there can be a particle current and a displacement current. The particle current is produced by a flow of positive or negative charges onto a plate of the capacitor. Since a capacitor does not allow an instantaneous change in voltage across the capacitor, when one electrode of the capacitor sees an instantaneous change in voltage, the other electrode of the capacitor also sees the same increase or decrease in voltage. Such an instantaneous change in voltage on the plates of the capacitor, i.e., a voltage pedestal, is brought about by displacement current. Bootstrapping is a technique for introducing a sudden change in voltage on one electrode of a capacitor and inducing a displacement current to force the other electrode to follow the same voltage change.
With reference to
a through
and
In general, Vd or Vsupply maximum is larger than Vdata to ensure driver transistor Q2 is driven into saturation. Four independent modes of operation are shown: (1) data voltage writing to pixel during times 0 to 0.1 msec, (2) OLED illumination during times 0.1 msec and 0.2 msec, (3) Driver Q2 compensation resulting in longer driver Q2 lifetime during times 0.2 msec and 0.3 msec, and (4) OLED compensation resulting in longer OLED 550 lifetime during 0.3 msec and 0.4 msec. Typical voltage waveform amplitudes for a-Si TFT active matrix are shown. Note that when V(1) rising edge precedes V(132) rising edge at 0+ seconds, the V(1) rising edge capacitively couples or bootstraps to V(2), thereby pulling up V(2). Shown is a 13V pullup on V(2). Storage capacitor Cs1 employs a displacement current through bootstrapping to facilitate storage of the data voltage. This displacement current provides quick data voltage writing onto V(2) by providing a voltage pedestal, whose voltage divider is the change in V(1) multiplied by Cs1 divided by the total capacitance on gate node driver Q2.
a is a semilog plot, and
In
This pixel circuit schematic of
In contrast, a-Si threshold voltage instabilities are typically induced by one or two of the following mechanisms; (1) charge injection from the channel interface and charge trapping in the TFT gate insulator, and/or (2) bond breaking in the a-Si semiconductor (Stabler-Wronski effect). The dominant a-Si TFT degradation mechanism is highly dependent on the a-Si and gate insulator film technology. The first degradation mechanism, charge injection and charge trapping in the TFT gate insulator, is field dependent, and hence easily controlled or limited, by the gate insulator electric field and gate insulator technology. A time, temperature and gate bias field dependence exists where TFT threshold voltage shift, dVt, is well described by the stretched-exponential equation
|dVt|=|dVo|α×{1−e−(t
where dVo=(Vgs−Vti), is approximately the initial voltage drop across the insulator, τ=τ0e(E
This distribution of multiple traps in the gate insulator yields a power law time dependence βo˜1.04 and To˜229K for the expression β=(Tst/To)−βo for positive gate voltages. Typical values are β˜0.248 and 0.22, Et˜1.17 and 0.97 eV for positive and negative gate bias stress, respectively.
For the gradual channel conditions, i.e., TFT linear region, where Vds<(Vgs−Vth), α˜1. For the TFT operating in the saturation region, α can be dramatically reduced below 1.
The design aspects of the pixel layout and the driving method of the present invention incorporate several advantages. Three of these advantages are described below.
A first advantage exists for pixels biased in the saturation region, where the larger the Vds-to-Vgs ratio, the lower the threshold voltage shift, dVt. Also, note that a positive and negative Vgs bias produces a positive and negative dVt shift, respectively, with the zero Vth shift crossover being at Vgs˜Vti, where Vti is the initial threshold voltage.
A second advantage exists if negative Vgs bias can be applied to offset the positive Vgs bias induced dVt. In addition, β may be gate pulse frequency dependent because of a thermal release of trapped charge between gate pulses, and a typical difference in the β values are 0.233 for gate pulse conditions between ˜0.125% and ˜33.3% duty cycle, to 0.248 for steady state, i.e., duty cycle=100%, gate conditions. Since β is gate pulse frequency dependent,
where tst(pulse) is the TFT accumulated pulse width stress time, and DC is 100% duty cycle. In addition, some insulators may favor injection of the opposite charged carriers, holes or electrons, which produces less net effectively charged gate insulators, and less dVt.
A third advantage exists in minimizing dVt. This is achieved if pulse bias, i.e., duty cycle<100%, is used rather than 100% duty cycle.
The present invention provides for a line-sequential scanning and constant-voltage driving sequence to drive a pixel composed of two TFTs, i.e., an access and driver TFT, one storage capacitor, and four externally accessible control lines/signals (SCAN, SUPPLY, DATA, and COMMON OLED electrode). The driving sequence is segmented functionally into four segments; (1) data sample and hold, (2) pixel illumination, (3) driver TFT compensation, and (4) OLED compensation.
It should be understood that various alternatives and modifications of the present invention. Nonetheless, the present invention is intended to embrace all such alternatives, modifications and variances that fall within the scope of the appended claims.
The present application is claiming priority of U.S. Provisional Patent Application Ser. No. 60/332,389, filed on Nov. 20, 2001.
Number | Name | Date | Kind |
---|---|---|---|
5302966 | Stewart | Apr 1994 | A |
5552678 | Tang et al. | Sep 1996 | A |
5952789 | Stewart et al. | Sep 1999 | A |
6229506 | Dawson et al. | May 2001 | B1 |
6229508 | Kane | May 2001 | B1 |
6366025 | Yamada | Apr 2002 | B1 |
6580657 | Sanford et al. | Jun 2003 | B1 |
6583581 | Kaneko et al. | Jun 2003 | B1 |
6611108 | Kimura | Aug 2003 | B1 |
6730966 | Koyama | May 2004 | B1 |
6747639 | So | Jun 2004 | B1 |
6828950 | Koyama | Dec 2004 | B1 |
6859193 | Yumoto | Feb 2005 | B1 |
6888318 | Childs | May 2005 | B1 |
20020047568 | Koyama | Apr 2002 | A1 |
20020047581 | Koyama | Apr 2002 | A1 |
20020053884 | Kimura | May 2002 | A1 |
20020101172 | Bu | Aug 2002 | A1 |
Number | Date | Country | |
---|---|---|---|
20030107565 A1 | Jun 2003 | US |
Number | Date | Country | |
---|---|---|---|
60332389 | Nov 2001 | US |