1. Field of the Invention
The present invention relates to an active matrix type display apparatus using a display element, specifically, an electroluminescent element (hereinafter, referred to as an EL element) to emit light by injecting a current for displaying an image an image display and the driving method thereof. Hereinafter, in the present specification, the active matrix type display apparatus using the EL element is referred to as an EL panel.
2. Description of the Related Art
<Active Matrix Type Display Apparatus>
The display region 2 is disposed with a plurality of pixel circuits 1 in a matrix shape along row and column directions. Each pixel circuit 1 is connected with a signal line 4 and a scanning line 7 of the corresponding column. The pixel circuit 1 of the column is loaded with a display signal supplied simultaneously to the corresponding signal line 4 (row selection period) by a control signal (scanning signal) of the scanning line 7. When the scanning signal moves to the next row, the display element contained in each pixel circuit 1 is lighted up in luminance corresponding to the loaded display signal (lighting period). The pixel circuit 1, to perform a color display, includes three sets having a display element of RGB primary colors.
The scanning signal of each scanning line 7 is generated by a row clock KR and a row register 6 having register blocks as many as rows input with a column scanning start signal SPR. The display signal of each column supplied to each signal line 4 is generated by the column control circuits 3 as many as columns. Corresponding to the display element of RGB primary colors disposed for every three columns, the column control circuit 3 includes three sets of the display element. In the column control circuit 3 of each column, a desired display signal is supplied to the signal line 4 of each column by a video signal VIDEO and a sampling signal SP as well as a horizontal control signal 8. A control circuit 9 is input with a horizontal synchronization signal SC corresponding to the video signal VIDEO 9, and generates a horizontal control signal 8. The sampling signal SP is generated by the column resister 5 made of ⅓ number of registers of the column control circuit 3. The column resistor 5 is input with a column clock KC and a column scanning start signal SPC, and the horizontal control signal 8 for mainly performing a reset operation of the column register 5.
<Pixel Circuit>
For the pixel circuit 1, a current writing type endurable to the characteristic variations of a TFT (a thin film transistor) element being used is commonly employed. In this case, a display signal supplied to the signal line 4 is a current signal. The pixel circuit 1 of the display panel is usually formed of the TFT. Since the TFT is great in the characteristic variations, the current writing type endurable to the characteristic variations is often used.
The pixel circuit 1 is connected with a emission power line PVdd, a signal line “data” for supplying a current “Idata”, and scanning lines P1 and P2 (a first scanning line and a second scanning line) for supplying scanning signals, and a current writing operation and a lighting operation are performed through the driving circuit of the EL element. The EL element has an anode terminal (a current injection terminal) connected to the emission power line PVdd (a first power source) through the transistor M4 and the drive transistor M3, and has the cathode terminal connected to a grounding line (a second power source) CGND.
First, at the current writing operation time (row selection time T1), each scanning signal becomes P1=H level and P2=L level, and the transistors M1 and M2 are turned on, and the transistor M4 is turned off. Then, the drive transistor M3 has a drain terminal isolated from a current injection terminal (anode terminal in the examples of
Next, at the lighting operation time (lighting period T2), each scanning signal becomes P1=L level and P2=H level, and the transistors M1 and M2 are turned off, and the transistor M4 is turned on. Then, the drive transistor M3 has a drain terminal connected to a current injection terminal (an anode terminal in the examples of
When the pixel circuit shown in
The parasitic capacitance accompanying the signal line “data” of each column becomes a total sum of the parasitic capacitance accompanying the pixel circuit of each column. The parasitic capacitance value accompanying this signal line depends on a panel size and the number of displays. For example, in the display panel of 3 inches by 480 rows, the parasitic capacitance value becomes approximately 5 pF. In the pixel circuit of
However, the current writing operations of the pixel circuits shown in
[PRG ability]=[writing current]×[writing time]÷[signal line parasitic capacitance] (1).
Unless this [PRG ability] value is secured, a normal current writing operation cannot be realized due to the characteristic variation of the TFT element in which the pixel circuit is generally formed. For that reason, a display image quality is remarkably deteriorated. Particularly, the display image quality of a low brightness small in writing current is deteriorated, and at the same time, a contrast ratio which is an important factor of the image quality cannot be increased. To increase the [PRG ability], the [signal line parasitic capacitance] is almost decided by the number of display rows and a display size, and a substantial reduction cannot be expected, and at the same time, the [writing time] also cannot be increased because of the maintenance of a refresh rate of the display image.
Further, in the pixel circuits shown in
An object of the present invention is to solve such a problem and provide a pixel circuit capable of improving a current writing ability in a low drive current (low brightness) region of a current writing type pixel circuit.
To achieve the object, the active matrix type display apparatus according to the present invention is an active matrix type display apparatus configured by disposing a pixel circuit for supplying the current to a display element disposed at a position where a signal line and a scanning line are intersected, the pixel circuit including: a drive transistor having a first main conductive terminal connected to a constant voltage source, a second main conductive terminal for injecting the current to the display element, and a control terminal; and a capacitive element connected between the control terminal of the drive transistor and the first main conductive terminal, the pixel circuit being connected to the signal line during a selection period, and isolated from the signal line during a non-selection period, wherein the selection period includes a first period and a second period, and during the first period, the second main conductive terminal of the drive transistor and the display element are isolated, the control terminal and the second main conductive terminal of the drive transistor are connected to the signal line, and the signal line is supplied with the constant current capable of conducting the drive transistor, during the second period, the second main conductive terminal of the drive transistor is disconnected from the signal line, and the signal line is supplied with a signal current corresponding to the current injected to the display element, and during the non-selection period, the second main conductive terminal of the drive transistor and the display element are connected, and a drive current according to the voltage between both terminals of the capacitive element is supplied from the drive transistor to the display element.
In the present invention, during a predetermined period before transiting from the first period to the second period, the control terminal of the drive transistor may be disconnected from the signal line. During the predetermined period within the non-selection period, a connection with the second main conductive terminal of the drive transistor and the display element may be broken so as to perform a lighting-turning-off control.
The pixel circuit may further include a first switch, a second switch and a third switch including the transistors whose on-and-off operations are controlled by the control signal of the scanning line, and the first switch may be disposed between the control terminal of the drive transistor and the signal line, and the second switch may be disposed between the second main conductive terminal of the drive transistor and the signal line, and the third switch may be disposed between the second main conductive terminal of the drive transistor and one terminal of the display element.
The scanning line includes a first scanning line, a second scanning line and a third scanning line, the first scanning line may be connected to a control terminal of the first switch, the second scanning line may be connected to a control terminal of the second switch, and the third scanning line may be connected to a control terminal of the third switch.
The scanning line may include a first scanning line and a second scanning line, the second switch may include two second switches mutually connected in series, the third switch may include two third switches mutually connected in series, the first scanning line may be connected to each control terminal of the first switch, one of the two second switches, and one of the two third switches, and the second scanning line may be connected to each control terminal of the other of the two second switches and the other of the two third switches.
Any of the drive transistor, the first switch, the second switch and the third switch may include a TFT. The drive transistor may include a p-type TFT, and any of the first switch, the second switch and the third switch may include an n-type TFT.
Further, the present invention is a driving method of the active matrix type display apparatus disposed with a pixel circuit to which a signal line and a scanning line are connected for supplying the current to a display element two dimensionally arranged, the pixel circuit including: a drive transistor having a first main conductive terminal connected to a constant voltage source, a second main conductive terminal for injecting the current to the display element, and a control terminal; and a capacitive element connected between the control terminal of the drive transistor and the first main conductive terminal, the pixel circuit being connected to the signal line during a selection period and isolated from the signal line during a non-selection period, wherein the selection period includes a first period and a second period, and during the first period, the second main conductive terminal of the drive transistor and the display element are isolated, the control terminal and the second main conductive terminal of the drive transistor are connected to the signal line, and the signal line is supplied with a constant current capable of conducting the drive transistor, and during the second period, the second main conductive terminal of the drive transistor is disconnected from the signal line, and the signal line is supplied with a signal current corresponding to the current injected to the display element, and during the non-selection period, the second main conductive terminal of the drive transistor and the display element are connected, and a drive current according to the voltage between both terminals of the capacitive element is supplied from the drive transistor to the display element.
According to the present invention, a pixel circuit for improving the current writing ability in the low driving current (low brightness) region of the current writing type pixel circuit can be provided.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Hereinafter, embodiments of the present invention will be described with reference to the accompanied drawings.
[First Embodiment]
First, with reference to
An EL panel (active matrix type display apparatus) according to the present embodiment shown in
The drive circuit of
A circuit configuration of the present embodiment, when compared with
The EL element has an anode terminal (current injection terminal) connected to the emission power line PVdd through the transistor M4 and the drive transistor M3, and has a cathode terminal connected to the grounding line CGND.
A gate terminal (control terminal) of the drive transistor M3 is connected to the signal line “data” through the transistor M1, whereas it is connected to one terminal of the capacitive element C1. A source terminal (first main conductive terminal) of the transistor M3 is connected to the emission power line (constant voltage source) PVdd and the other terminal of the capacitive element C1. A drain terminal (second main conductive terminal) of the drive transistor M3 is connected to the signal line “data” through the transistor M2, while it is connected to the EL element through the transistor M4.
One of the source and drain terminals of the transistor M1 (first switch) is connected to the gate terminal of the drive transistor M3 and one terminal of the capacitive element C1. The other of the source and drain terminals of the transistor M1 is connected to the signal line “data” and one of the source and drain terminals of the transistor M2. A gate terminal of the transistor M1 is connected to the scanning line P1, and is controlled in on-off operations by scanning signals (L and H levels).
One of the source terminal and drain terminal of the transistor M2 (second switch) is connected to the signal line “data” and the other of the source and drain terminals of the transistor M1. The other of the source terminal and drain terminal of the transistor M2 is connected to the drain terminal of the drive transistor M3 and one of the source and drain terminals of the transistor M4. A gate terminal of the transistor M2 is connected to the scanning line P3, and is controlled in on-off operations by the scanning signals (L and H levels).
One of the source and drain terminals of the transistor M4 (third switch) is connected to the drain terminal of the transistor M3 and the other of the source and drain terminals of the transistor M2. The other of the source and drain terminals of the transistor M2 is connected to the anode terminal of the EL element. The gate terminal of the transistor M2 is connected to the scanning line P2, and is controlled in on-off operations by the scanning signals (L and H levels).
Next, the operation of the present embodiment will be described with reference to
First, when starting the current writing operation (row selection period T1) of the (N)th row, at the time t1, as shown in
By so doing, the drive transistor M3 has the drain terminal isolated from the anode terminal (current injection terminal) of the EL element through the transistor M4. In this state, the drive transistor M3 has the gate terminal connected to the signal line “data” through the transistor M1, and at the same time, has the gate and drain terminals short-circuited through the transistor M2, and is put into a diode connection state. As a result, by the current “Idata” supplied to the signal line “data”, a gate terminal voltage VG decided by the characteristic of the drive transistor M3 is generated, and the gate terminal voltage VG is charged to the capacitive element C1 connected between the gate terminal and the source terminal.
At this time, as shown in
The gage terminal voltage VG (N) is expressed by the following formula (2).
VG(N)=Vth(N)+(IREF/β(N))0.5 (2)
Next, at the time t2, the scanning signal of the scanning line P3 changes to P3=L level, and the transistor M2 is turned off, and this allows a connection with the drain terminal of the transistor M3 and the signal line “data” to be broken. At this time, as shown in
The reason why the voltage rise up to the time t2 to t3 is linear is because a gate load of the drive transistor M3 of the (N)th row is a capacitive load CL as shown in the following formula (3).
CL=Cs+Cg (3)
Further, the voltage rise ?V(N) in the gate terminal voltage VG(N) of the drive transistor M3 of the (N)th row is shown in the following formula (4).
ΔV(N)=IS(N)×(t3−t2)/CL (4)
Next, at the time t3, each scanning signal of the scanning lines P1 and P2 changes to P1=L and P2=H, and the transistor M1 is turned off, and the transistor M4 is turned on, and the current writing operation of the (N)th row is terminated. At this time, the drain terminal of the drive transistor M3 is connected to the anode terminal of the display element, and moves to a lighting period (non-selection period T2).
By so doing, the drive transistor M3 of the (N)th row has the gate terminal isolated from the signal line “data” through the transistor M1, and is put into an open state. As a result, at the current writing operation time, the voltage between both terminals charged to the capacitive element C1 between the gate and source terminals becomes the gate terminal voltage VG (N) of the transistor M3 as it is.
At this time, the drive current (drain current) Id(N) between the source and drain terminals of the drive transistor M3 of the (N)th row is shown by the following formula (5) using the formulas (2) and (4).
Id(N)=β(N)×[VG(N)−ΔV(N)−Vth(N)]=β(N)×[{IREF/β(N)}0.5−IS(N)×(t3−t2)/CL]2 (5)
As evident from the formula (5), the drive current Id (N) does not depend on the threshold value voltage Vth, and can be controlled by the current IS(N).
In the driving method illustrated in
That is, the current IS may be turned into a signal current for controlling the display image. In the example of
Further, a current range of the drive current Id can be easily set by the constant current (first current)IREF and the constant period (t3−t2) (second period T12) by taking into consideration the parasitic capacitance Cs accompanying the signal line “data”.
Further, as evident from the formula (5), though the drive current Id is not affected by the variations of the threshold value voltage Vth of the drive transistor M3, but is affected by the variations of the drive coefficient β of the drive transistor M3. However, since the current IS is small in a large drive current (high brightness) where the current absolute error becomes large, the drive current Id is hardly affected by the drive coefficient β. Further, though the drive current Id relates to the drive coefficient β in the small drive current where the current absolute error becomes small, since the absolute value error of the drive current can be small, the influence to the display image quality is small. When the current IREF is set [smaller] than the drive current Id(N+2) at the high brightness time, in a wide range of the drive current Id, the influence of the variations of the drive coefficient β can be made further small.
Although the drive current Id relates to the signal line parasitic capacitance Cs, since the signal line parasitic capacitance Cs is a total sum of the parasitic capacitance accompanying the signal line “data” in the pixel circuit 1 of each row, the deviation in proximity that influences the display image quality is extremely small. Even when there is the variation of the signal line parasitic capacitance, the spatial frequency in the column direction is low, and therefore, there is no great influence exerted on the display image quality.
As described above, in the present embodiment, since the writing operation ability of the pixel circuit 1 has nothing to do with the current value of the signal current IS, basically there is no problem of the writing operation ability in the current writing type pixel circuit shown in the formula (1).
The signal current IS has to be generated by a line sequential current, and can be generated also by an external IC. However, because of miniaturization and low-cost requirement, it is desirably formed by the TFT circuit on a glass substrate. The method of generating a stabilized line sequential signal current by the TFT circuit is disclosed in U.S. Patent Application Publication No. 2004/0183752. The generation of the constant current IREF is disclosed in Japanese Patent Application Laid-Open No. 2005-157322.
An outline of the operation of the present embodiment as described above is as follows.
1) During the first period T11 of the selection period T1, the drain terminal of the drive transistor M3 is connected to one terminal of the holding capacitance C1. In this state, both terminals of the holding capacitance C1 are connected between the emission power line PVdd and the signal line “data”, and from the signal line “data”, the constant current (first current) IREF capable of conducting the drive transistor M3 is supplied. As a result, the capacitive element C1 is charged.
2) During the second period T12 of the selection period T1, in a state in which the drain terminal of the drive transistor M3 is opened, the signal current (second current) IS corresponding to the injection current from the signal line “data” to the display element is supplied for a predetermined time. As a result, the voltage between both terminals of the capacitive element C1 is established.
3) After the termination of the period T12 of the selection period T1, during the lighting period T2, the holding capacitance C1 and the signal line “data” are isolated, and the source and drain terminals of the drive transistor M3 and two terminals of the display element are connected in series between the emission power line PVdd and the grounding line CGND. As a result, the drive current Id corresponding to the established voltage between both terminals of the capacitive element C1 is supplied to the display element.
As described above, in the EL panel of the present embodiment, in each pixel circuit 1, only for the period from the start of the writing period T1 to the first period T11, the constant current IREF is supplied to the signal line “Data” so as to perform the current writing. In the second period T12 after the elapse of the first period T11, a connection with the main conductive terminal (drain terminal) of the current drive transistor M3 and the signal line “Data” in each pixel circuit 1 is broken. Further, the signal current IS corresponding to the desired drive current is supplied to the signal line “Data”, and at the same time, after the elapse of the second period T12, and the period moves to the lighting period T2 in which any of the main conductive terminals of the drive transistor M3 is connected to the display element.
Consequently, according to the present embodiment, by a simple change for the current writing type pixel circuit, a voltage writing type pixel circuit that substantially suppresses an variations of the threshold value voltage of the drive transistor of the pixel circuit can be realized, so that the display image quality of the EL panel can be greatly improved. Further, since the pixel circuit can perform the threshold value voltage detection operation of the drive transistor at a high current level, even in the limited writing period, the threshold value voltage detection operation can be reliably performed.
[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to
While the first embodiment applies the pixel circuit of
[Third Embodiment]
Next, the third embodiment of the present invention will be described with reference to
A pixel circuit 1 of the present embodiment shown in
The pixel circuit 1 of
That is, as shown in
Further, in the configuration of
Further, as shown in
In each of the above described embodiments, while the drive transistor includes the p-type TFT, and the switching transistors M1, M2 and M4 include the n-type TFT, the present invention is not limited to this. The TFT to be used can adapt any of the n-type or the p-type. An active layer of the TFT may be composed by using amorphous silicon or may include a material consisting essentially of silicon or a material consisting essentially of a metal oxide or a material consisting essentially of an organic matter.
Further, as an application, electronic apparatus such as a television receiver and a portable apparatus using the EL panel for the display apparatus can be set up.
The present invention can be adapted to the EL panel and the pixel circuit used for the panel and the application of the driving method thereof.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2007-174121, filed Jul. 2, 2007, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | Kind |
---|---|---|---|
2007-174121 | Jul 2007 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
5302871 | Matsuzaki et al. | Apr 1994 | A |
5963184 | Tokunaga et al. | Oct 1999 | A |
6188378 | Yamamoto et al. | Feb 2001 | B1 |
6335720 | Mori et al. | Jan 2002 | B1 |
6348910 | Yamamoto et al. | Feb 2002 | B1 |
6373454 | Knapp et al. | Apr 2002 | B1 |
6552709 | Yamaguchi | Apr 2003 | B1 |
6559824 | Kubota et al. | May 2003 | B1 |
6587086 | Koyama | Jul 2003 | B1 |
6661180 | Koyama | Dec 2003 | B2 |
7126565 | Kawasaki et al. | Oct 2006 | B2 |
7242397 | Iseki et al. | Jul 2007 | B2 |
7253812 | Sasaki | Aug 2007 | B2 |
7259735 | Kasai | Aug 2007 | B2 |
7532207 | Kawasaki et al. | May 2009 | B2 |
7605899 | Shikina et al. | Oct 2009 | B2 |
7692643 | Kawasaki et al. | Apr 2010 | B2 |
7812812 | Yoshinaga et al. | Oct 2010 | B2 |
7911425 | Goden et al. | Mar 2011 | B2 |
20020047581 | Koyama | Apr 2002 | A1 |
20030058687 | Kimura | Mar 2003 | A1 |
20040155843 | Sasaki | Aug 2004 | A1 |
20040183752 | Kawasaki et al. | Sep 2004 | A1 |
20050007316 | Akimoto et al. | Jan 2005 | A1 |
20050007319 | Shin et al. | Jan 2005 | A1 |
20050041002 | Takahara et al. | Feb 2005 | A1 |
20050122150 | Iseki et al. | Jun 2005 | A1 |
20050285151 | Kawasaki | Dec 2005 | A1 |
20060061529 | Kim | Mar 2006 | A1 |
20060114194 | Kawasaki et al. | Jun 2006 | A1 |
20060114195 | Yamashita et al. | Jun 2006 | A1 |
20060132395 | Kawasaki et al. | Jun 2006 | A1 |
20060187185 | Yoshinaga et al. | Aug 2006 | A1 |
20060267509 | Yang | Nov 2006 | A1 |
20070132719 | Yamashita et al. | Jun 2007 | A1 |
20070257867 | Kasai | Nov 2007 | A1 |
20070257868 | Kasai | Nov 2007 | A1 |
20080007494 | Kim et al. | Jan 2008 | A1 |
20080157828 | Kawasaki et al. | Jul 2008 | A1 |
20080158112 | Kawasaki et al. | Jul 2008 | A1 |
20080259000 | Kawasaki | Oct 2008 | A1 |
20090015571 | Kawasaki et al. | Jan 2009 | A1 |
20090033599 | Kawasaki et al. | Feb 2009 | A1 |
20090066615 | Kawasaki | Mar 2009 | A1 |
20090085908 | Kawasaki et al. | Apr 2009 | A1 |
20090102853 | Kawasaki et al. | Apr 2009 | A1 |
20090109144 | Goden et al. | Apr 2009 | A1 |
20090121980 | Kawasaki et al. | May 2009 | A1 |
20090135110 | Nakamura et al. | May 2009 | A1 |
20090231239 | Goden et al. | Sep 2009 | A1 |
20090289966 | Ikeda et al. | Nov 2009 | A1 |
20100026677 | Shikina et al. | Feb 2010 | A1 |
20100073267 | Akimoto et al. | Mar 2010 | A1 |
20100128160 | Maru et al. | May 2010 | A1 |
20100328365 | Ikeda et al. | Dec 2010 | A1 |
20110025653 | Ikeda et al. | Feb 2011 | A1 |
20110090210 | Sasaki et al. | Apr 2011 | A1 |
Number | Date | Country |
---|---|---|
1521719 | Aug 2005 | CN |
1770246 | May 2006 | CN |
1 429 312 | Jun 2004 | EP |
11-282417 | Oct 1999 | JP |
2001-134229 | May 2001 | JP |
2001-159877 | Jun 2001 | JP |
2004-3411144 | Dec 2004 | JP |
2005-157322 | Jun 2005 | JP |
2006-030516 | Feb 2006 | JP |
2008-268981 | Nov 2008 | JP |
2008-015516 | Dec 2008 | JP |
Number | Date | Country | |
---|---|---|---|
20090015571 A1 | Jan 2009 | US |