Patent Application
20080165119
This invention generally relates to an active matrix for flat panel displays and more specifically to write circuitry for active matrix displays.
There is a large variety of different types of displays presently used in the flat panel display field. Included among these different types are liquid crystal displays (LCDs), plasma displays, electroluminescent displays (ELDs), electrophoretic displays (EPDs), electrochromic displays (ECDs), etc. In general, each of these different types have somewhat different applications but may overlap and be competitive at the edges of a particular use or application. For example, plasma displays are used in large television monitors while LCDs are becoming more adaptable to mid-range monitors. Generally, LCDs are widely used in small displays, such as telephones, hand-held devices and the like.
New classes of display technologies have been developed to exhibit memory characteristics, i.e. when an applied voltage is removed from a pixel the state of the pixel remains the same. Electrophoretic materials include particles that move through or rotate within a suspending material. Electrophoretic displays (EPDs) change color and reflectivity based on charged moving particles. One major advantage of EPDs is the low manufacturing cost due to high production throughput associated with the use of flexible substrates. To take advantage of this low cost display technology, it is essential that the driving or controlling circuitry is also low cost.
One EPD material that is used as an example in the present application is one in which charged particles move within a layer of suspending material to one surface or the other when an electric field of a specific polarity is applied across the layer. In a typical example, the particles are white colored and positively charged so that they are drawn to a surface having a negative voltage applied relative to the opposed surface. In this example, the material appears to turn white when the relative negative voltage is applied to the viewing surface.
Once the particles are attracted to the surface by the negative voltage, they remain adjacent to the surface even when the negative voltage is removed. This is referred to as having a memory. Even Brownian movement appears to have little or no effect on the particles. Further, as an example, the suspending material can be light absorbing so that when the white particles are drawn away from the surface, i.e. by applying a positive voltage to the viewing surface and a negative voltage to the opposed surface, the material appears to be dark or with different colors, depending on the absorbing spectrum of the suspending material. Therefore, a display is produced by providing electrodes on opposite sides of an array of electrophoretic cells and activating the electrodes to cause each of the cells to be light or dark or to change color.
In the prior art, one of the main types of electrophoretic displays includes the use of a segmented drive, i.e. no active matrix. This particular arrangement is only useful for very small displays having few pixels. When a display incorporating a large number of pixels is desired, the segmented drive becomes extremely complicated and, therefore, extremely costly. Similarly, a passive matrix, while it is the simplest and cheapest to fabricate, is not an option for large displays because of the crosstalk. The problem is the fact that a threshold voltage at which the switching of electrophoretic material begins normally lies anywhere in a broad range and can vary substantially with temperature. This characteristic eliminates a passive matrix as a potential embodiment.
Another type of electrophoretic display used in the prior art is an active matrix using thin film transistors (TFTs). This structure has been primarily copied from the liquid crystal (LCD) field. In the typical embodiment, a common electrode is supplied on one surface of the electrophoretic material (i.e. the viewing side) and an electrode with a thin film transistor (TFT) attached is supplied on the other side. A TFT is a complicated device and its fabrication cost is high relative to EPDS. For a TFT active matrix associated with EPDs, the dominant cost is in the TFT backplane
One way to reduce the cost of the backplane is to implement active matrices using much simpler thin film diodes. However, two major problems arise. In all such active matrices, the thin film diodes must be bidirectional, i.e. essentially two diodes in parallel oriented with opposite polarities. Usually, the full voltage required to switch electrophoretic material from one state to the other is relatively large. Depending upon the specific construction and the materials used, the voltage required to switch a cell to light from dark or to dark from light can be tens of volts, e.g. from ten to eighty volts. For this TFD switching circuit to operate correctly, the turn-on voltage of the bidirectional diode must be much greater than the full switching voltage of the electrophoretic material. Thus, an active matrix using bidirectional TFDs would require a very large operating voltage that would make the cost of drivers prohibitive.
A major disadvantage of writing directly to the active matrix is the limited speed in writing to each EPD in each line. The writing is done one line at a time without memory. The speed of writing a line is dictated by the speed of the EPD which is on the order of 100 ms or more. Therefore, the line time window is controlled by the response time of the EPD. The frame time is determined by multiplying the line time by the number of lines. To write a display with hundreds of lines, the frame time is too long (up to minutes). While this might be satisfactory for some applications, many applications require a much faster write time.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved active matrix for flat panel displays of various types with a much faster write time.
Briefly, to achieve the desired objects of the instant invention in accordance with a preferred embodiment thereof, provided is a display with memory that includes an electrophoretic flat display panel with a common transparent conductive electrode positioned on a major viewing surface. An active matrix with an array of conductive pads is positioned on a reverse side of the panel and each conductive pad defines a pixel in conjunction with the common transparent conductive electrode. The active matrix includes conductive select lines and data lines. A diode and a storage capacitor electrically couple each conductive pad to a data line and a select line, respectively, such that each conductive pad is separately addressable by a unique combination of select line and data line. Each of the conductive pads is electrically coupled to a common reset terminal, which in this embodiment is the common transparent conductive electrode, by the intrinsic capacitance of the cell.
The desired objects of the instant invention and others are further achieved through a method of writing data to an electrophoretic flat panel display with memory including the step of providing an electrophoretic flat display panel including an active matrix with an array of conductive pads positioned on the reverse side of the flat display panel so that each conductive pad defines a pixel in conjunction with a common transparent conductive electrode positioned on the major viewing surface. In the provided panel, the active matrix includes select lines and data lines with a data input diode and a storage capacitor connecting each conductive pad to one of the data lines and to one of the select lines, respectively, such that each pixel is separately addressable by a unique combination of select line and data line. The method further includes a step of resetting all of the pixels initially into a dark state by applying a VEPD+Von signal to the reset terminal (the common transparent conductive electrode), a signal equal to zero volts to all select lines, and a Von signal to all data lines, where VEPD is a voltage required to change states of the pixel and Von is the turn on voltage of the data input diode. The method further includes a step of writing data into the storage capacitor of a selected pixel by applying a zero voltage signal on the select line of the selected pixel, applying a signal equal to VEPD+Von to all select lines of pixels not selected, retaining a signal equal to Von+VEPD on the reset terminal, and applying a signal to the data line equal to a voltage between Von and VEPD+Von representative of a desired brightness.
The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the drawings, in which:
Turning now to the drawings, attention is first directed to
A backplane 20 is laminated to the rear surface of panel 12 and contains an active matrix including an array of conductive pads 22. Data lines 24 extend vertically between adjacent columns of conductive pads 22, with one data line 24 for each column of conductive pads 22, and select lines 26 extend horizontally between adjacent rows of conductive pads 22, with one select line for each row of conductive pads 22. It will of course be understood that there is no connection between data lines 24 and select lines 26 on the surface of panel 20. Also, it should be understood that the positions of the select lines and data lines are for purposes of this explanation and that the lines could be reversed or positioned differently if desired. Each conductive pad 22 is connected to one data line 24 of the plurality of vertically extending data lines 24 by a thin film diode 26, as illustrated in
A common transparent conductive plane 28 is deposited on the upper or visible surface of display panel 12. Because conductive plane 28 is common, no alignment of cells and backplane 20 is required during manufacture. Thus, manufacturing is greatly simplified since there are no electrical connections between display panel 12 and backplane 20 and no critical alignment is necessary. For example, display panel 12 and backplane 20 could be manufactured separately and laminated together later or backplane 20 could be formed directly on the back of display 12. It will be understood from the following description that backplane 20 can be formed using virtually any convenient material as a substrate. For example, the substrate can include glass, quartz, silicon, PCB, PET, polyimide (PI), aluminum foil, SS foil, etc.
Display 10 includes m horizontal select lines 16 and n vertical data lines 24 cooperating to divide panel 12 into an array of m×n pixels or cells each including one of the m×n conductive pads 22. As is understood in the art, each pixel or cell is addressed (or selected) through the specific select line 16 and the data line 24 connected to the specific conductive pad 22 on the lower surface. Further, by applying a predetermined voltage to the specific conductive pad 22 the selected cell or pixel can be switched into a dark or light state as will be explained in more detail below.
It will be understood that the driver circuitry includes additional circuits (not shown) which are designed to select cells or pixels in some predetermined order and to apply preselected driving voltages in accordance with some selected data to be displayed. These additional circuits are well known in the art and are dependent upon specific applications so that further disclosure is not necessary to the understanding of the present invention and, therefore, will not be undertaken herein.
Referring additionally to
Here it should be understood that any voltages applied to the cell which lie between −Vth and +Vth have no visible effect on the cell (i.e. no change in brightness). This area of operation is responsible for the memory in electrophoretic cells. Also, one of the major problems with the use of electrophoretic materials is the fact that the exact position or voltage of −Vth and +Vth can vary substantially (i.e. as much as a volt), depending upon the electrophoretic material used and the temperature during operation.
Storage capacitors 30 are relatively large and may, for example, be deposited under the reverse side of each conductive pad 22. This is easily accomplished by depositing a first plate for each capacitor on the surface of backplane 20, depositing a dielectric layer on the first plate, and then depositing conductive pad 22 over the dielectric. In this fashion storage capacitor 30 is automatically connected to conductive pad 22 and only a connection between select line 16 and the first plate is required. Here it will be noted, the intrinsic capacitance of the cell 14, herein designated 32 (and referred to in the text below as CEPD) is a relatively small capacitance between each conductive pad 22 and conductive plane 28. It is well known that the intrinsic capacitance of the electrophoretic cell CEPD is very small because of the relatively thick electrophoretic material in display panel 12 and, therefore, cannot be used as a storage capacitance. Also, the capacitance of storage capacitor 30, herein designated Cst, is more than ten times greater than the capacitance of diode 26 and preferably greater than twenty times as much.
A current-voltage curve for thin film diode 26 in active matrix 10 is illustrated in
In a preferred embodiment, diode 26, which is an asymmetric diode as explained above, is a printed diode such as Ta/TaO2. Printed diodes can be fabricated on flexible substrates and are very convenient to manufacture. Also, printed diodes can be conveniently implemented in series by fabricating and connecting multiple diodes laterally or vertically. As an example, multiple diodes can be fabricated vertically by simply printing extra layers of materials. Printed diodes and the fabrication of flat panel displays is discussed in detail in copending United States Patent Application entitled “TFD Active Matrix”, bearing patent application Ser. No. 11/430,075, filed on May 8, 2005, and incorporated herein by reference. Also, it is well known in the art that diodes, such as the thin film diodes discussed herein, have an inherent capacitance.
To understand the operation more fully, a schematic drawing of a cell 14 is illustrated in
After the reset, all lines are unselected by holding the voltage on the rows or select lines 16 at VEPD+Von (17 volts). The voltage at node B (the inner terminal of storage capacitor 30) is raised to VEPD+Von (17 volts) and the voltage across cell 14 is now zero, which holds cell 14 in the dark state of the reset.
Data is written into storage capacitor 30 by a column driver on data line 24 (node A). Select line 16 (node C) of the cell being written is at zero volts and all unselected lines are maintained at VEPD+Von (17 volts). Also, common conductive plane 28 (node D) is maintained at VEPD+Von (17 volts). The data on data line 24 (node A) is between Von (2 volts and a dark cell) and VEPD+Von (17 volts and a bright cell). Thus, storage capacitor 30 of the selected cell is charged very rapidly to the write voltage on data line 24. For all unselected cells, the voltage on select lines 16 (node C) is at VEPD+Von (17 volts) and diode 26 is reverse biased so that the voltage on storage capacitor 30 is not affected (since the capacitance of diode 26 is much smaller than storage capacitor 30). Thus, data can be written to the various cells at a very high rate because the voltage can be written at a very high rate and the voltage on each of the cells is maintained after the cell is no longer on a selected line. The rate of writing is limited by the charging capacity of diode 26 instead of the response time of the cell 14.
After the writing process, the voltage across storage capacitor 30 is between 0 volts and VEPD volts, depending on the written data (desired state or brightness of the cell). But, as the voltage on select line 16 changes from 0 volts to VEPD+Von, as select line 16 changes from a selected cell to an unselected cell, the voltage on the inner node of storage capacitor 30 (node B) becomes VEPD+Von or 2VEPD+Von, depending on the written data, and the voltage across cell 14 becomes zero or VEPD, depending on the written data. Thus, the written data is actually applied to cell 14 after the cell is changed to an unselected cell.
Referring additionally to
Turning now to
A backplane 200 is laminated to the rear surface of display panel 120 and contains an active matrix including an array of conductive pads 220. Select lines 160B extend horizontally between adjacent rows of conductive pads 220, with one data line 160B for each row of conductive pads 220. Select lines 160B on backplane 200 are electrically connected to select lines 160A on display panel 120 and are hereinafter referred to generally as select lines 160. Data lines 240 extend vertically between adjacent columns of conductive pads 220, with one data line 240 for each column of conductive pads 220. Also, display panel 120 and backplane 200 are aligned so that the relatively broad select lines 160A are positioned generally in overlying relationship to rows of conductive pads 220, with one select line 160A for each row of conductive pads 220. Thus, the combination of conductive pads 220, select lines 160, and data lines 240 divide display panel 120 into rows and columns of cells or pixels.
It should be understood that the positions of the select lines and data lines are for purposes of this explanation and that the lines could be reversed or positioned differently if desired. Display panel 120 and backplane 200 could be manufactured separately and laminated together later or backplane 200 could be formed directly on the back of display 120. It will be understood from the following description that backplane 200 can be formed using virtually any convenient material as a substrate, for example, the substrate can include glass, quartz, silicon, PCB, PET, polyimide (PI), aluminum foil, SS foil, etc.
Each conductive pad 220 is connected to one data line 240 of the plurality of vertically extending data lines 240 by a thin film diode 260, as illustrated in
Display 100 includes m horizontal select lines 160 and n vertical data lines 240 cooperating to divide panel 120 into an array of m×n pixels or cells each including one of the m×n conductive pads 220. As is understood in the art, each pixel or cell is addressed (or selected) through the specific select line 160 and the data line 240 connected to the specific conductive pad 220 on the lower surface. Further, by applying a predetermined voltage to the specific conductive pad 220 the selected cell or pixel can be switched into a dark or light state as will be explained in more detail below.
It will be understood that the driver circuitry includes additional circuits (not shown) which are designed to select cells or pixels in some predetermined order and to apply preselected driving voltages in accordance with some selected data to be displayed. These additional circuits are well known in the art and are dependent upon specific applications so that further disclosure is not necessary to the understanding of the present invention and, therefore, will not be undertaken herein.
To understand the operation of this embodiment more fully, a schematic drawing of a cell 140 is illustrated in
After the reset, storage capacitor 300 can be optionally charged to zero volts by setting all select lines 160 to zero volts and all data lines 240 to Von or 2 volts. Setting the charge on all of the storage capacitors 300 at zero volts can further decrease the time required to write data into display 100 and simplify the data being written.
Data is written into storage capacitor 300 by the column driver represented by data line 240. In the select stage or mode, the voltage on the select line 160 (node C) of the cell being written or selected is at zero volts and all other select lines 160 (node C) of the cells not selected are at VEPD+Von (17 volts) and the reset voltage (node D) is at Von+2VEPD. The voltage on data line 160 (node A) is between Von (dark) and VEPD+Von (bright). The voltage on storage capacitor 300 is quickly raised to the selected voltage (between Von and VEPD+Von) that is present at node A and the associated pixel or cell ultimately rises to the selected voltage from 0 volts to VEPD (dark to bright). For pixels not on the select line (unselected), the row voltage (node C) is at Von+VEPD, both diodes 260 and 320 are reverse biased and the voltage at the storage capacitor 300 is not affected if the capacitance of the diode 260 and 320 is much smaller than the capacitance of storage capacitor 300.
Because the RC time is very short for the large storage capacitor, the write time is very short. Thus, data can be written to display 100 at a very high rate because the voltage can be written at a very high rate and the voltage on each electrophoretic cell 140 is maintained when the pixel is not on the select line. The rate of writing in display 100 is limited by the charging capacity of diode 260 instead of the response time of the electrophoretic cells 140. Here it will be noted, the On/Off ratio of display 100 is greater than 10N, where N is the number of scan lines in the display.
Referring additionally to
Thus, two embodiments of a new and novel active matrix with write memory for a flat panel display have been disclosed. The active matrix with memory is especially useful and convenient when using electrophoretic material in the display panel. The write time is substantially reduced so that data can be written to relatively large display panels in relatively short times. Also, the preferred embodiment incorporates only one diode (a data input diode) in each pixel which substantially improves the fabrication process. While a specific polarity of diodes and signals is illustrated in the figures for purposes of explanation, it will be understood that the polarity of components and signals can be easily reversed if desired.
Various changes and modifications to the embodiment herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.
