Patent Application
20080024172
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements.
Systems and methods for actively compensated buffering for high speed current mode logic data paths are disclosed. The following description is presented to enable any person skilled in the art to make and use the invention. Descriptions of specific embodiments and applications are provided only as examples and various modifications will be readily apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed herein. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
Particular circuit layouts and circuit components may be given for illustrative purposes. This is done for illustrative purposes to facilitate understanding only and one of ordinary skill in the art may vary the design and implementation parameters and still remain within the scope of the invention.
Generally this description relates to the design and manufacture of integrated semiconductor circuits. In particular, circuits that provide actively compensated buffering for high speed current mode logic data paths are discussed. The systems and methods described herein can be applied to any high speed current mode logic (CML) design to expand bandwidth and boost edge slew rate. Typical applications include, but are not limited to, PCI Express, HDMI/DVI, DisplayPort, Serial ATA, SONET, Rapid IO, and XAUI.
In one example, the circuits and methods boost the signal edge slew rate in order to expand the data path frequency bandwidth, thereby increasing data transfer speed. Active components in the form of additional transistors are added to a CML buffer circuit to boost high frequency gain and thereby increase the overall frequency bandwidth. The system is advantageously used to provide a simple and efficient solution to expand bandwidth and boost signal edge slew rates in high speed CML data paths. The system provides an effective solution for very high speed CML design using a cost efficient approach with limited design effort.
In one example of the invention, a current mode logic circuit includes a first MOS transistor and a second MOS transistor. The first MOS transistor has a first MOS transistor gate, a first MOS transistor source, and a first MOS transistor drain. The second MOS transistor has a second MOS transistor gate, a second MOS transistor source, and a second MOS transistor drain. A first data input terminal is coupled to the first MOS transistor gate and a second data input terminal is coupled to the second MOS transistor gate. A first current source is coupled to the first MOS transistor source and the second MOS transistor source. A first load resistor coupled to the first MOS transistor drain and a second load resistor is coupled to the second MOS transistor drain.
The circuit further includes a third MOS transistor and a fourth MOS transistor. The third MOS transistor has a third MOS transistor gate, a third MOS transistor source, and a third MOS transistor drain. The third MOS transistor gate is coupled to the second MOS transistor gate. The fourth MOS transistor has a fourth MOS transistor gate, a fourth MOS transistor source, and a fourth MOS transistor drain. The fourth MOS transistor gate is coupled to the first MOS transistor gate. A capacitor is coupled between the third MOS transistor source and the fourth MOS transistor source. A first output terminal is coupled to the first MOS transistor drain and the fourth MOS transistor drain. A second output terminal is coupled to the second MOS transistor drain and the third MOS transistor drain.
In one example of the invention, an actively compensated CML circuit includes a CML buffer circuit and a bandwidth expansion circuit. The CML buffer circuit includes a first MOS transistor and a second MOS transistor in a differential pair configuration. A first load resistor is coupled to a first MOS transistor drain at a first output terminal and a second load resistor is coupled to a second MOS transistor drain at a second output terminal. The bandwidth expansion circuit is coupled to the CML buffer circuit in a source follower configuration. The bandwidth expansion circuit includes a third MOS transistor and a fourth MOS transistor. A third MOS transistor gate is coupled to a second MOS transistor gate, a fourth MOS transistor gate is coupled to a first MOS transistor gate, a third MOS transistor drain is coupled to the second output terminal, and a fourth MOS transistor drain is coupled to the first output terminal. A capacitor is coupled across a third MOS transistor source and a fourth MOS transistor source. The fourth MOS transistor and the third MOS transistor generate a high pass function at the first output terminal and the second output terminal.
Referring to
The CML buffer circuit 50 utilizes NMOS transistors M12 and M24 as a differential logic pair. The gate electrode of NMOS transistor M12 is connected to input line IN+ 14, the source electrode is connected to constant-current source I112, and the drain electrode is connected to output line Out-18 and load element R16. The gate electrode of NMOS transistor M24 is connected to input line IN− 16, the source electrode is connected to constant current source 1112, and the drain electrode is connected to output line Out+ 20 and load element R28.
The operation of the CML buffer circuit 50 will next be explained with reference to
Referring again to
In operation, circuit 100 provides a simple and efficient solution for an actively compensated CML buffer. The differential pair of NMOS transistor M12 and NMOS transistor M24 is the main amplifier stage, and the pair of transistors NMOS transistor M322 and NMOS transistor M424 is in a source follower configuration. The input signal at input line IN+ 14 and input line IN− 16 is directly fed to the gates of NMOS transistor M322 and NMOS transistor M424. As a result of the source follower configuration, a signal copy is replicated at the sources of NMOS transistor M322 and NMOS transistor M424. The current flowing through the capacitor C 30 is proportional to the derivative of the voltage across the capacitor. Since the voltage across capacitor C 30 is the replica of the input signal, the current through capacitor C 30 is the derivative of the input signal with a scaling coefficient.
The current summations at load resistor R16 resulting from NMOS transistor M12 and NMOS transistor M424, and at load resistor R28 from NMOS transistor M24 and NMOS transistor M322 generate a high pass function, resulting in a gain boost at high frequencies and thereby expanding the frequency bandwidth. In particular, the current resulting from NMOS transistor M322 and NMOS transistor M424 generate a high pass function.
The currents flowing through R1 and R2 result in a differential voltage V(Out+, Out−) at Out+ 20 and Out− 18:
V(Out+,Out−)=A0*V(IN+,IN−)+A1*d/dt[V(IN+,IN−)]
where V(IN+,IN−) and V(Out+,Out−) are the differential voltages at input and out respectively, A0 and A1 are constant gain coefficients, and d/dt denotes derivative operation. The second component of V(Out+,Out−), A1*d/dt[V(IN+,IN−)], results from the addition of bandwidth expansion circuit 60 and corresponds to an increased edge slew rate. As described below, the increased edge slew rate corresponds to an increased overall frequency bandwidth of circuit 100 relative to CML buffer circuit 50 alone.
The above formula for V(Out+,Out−) is a time domain description of the relationship between input signal and output signal. It can also be presented in frequency domain as
Vo(s)/Vi(s)=A0+A1*s
where Vi(s) and Vo(s) are the Laplace transforms of the input and output signals, and s is the Laplace operator. It is known that this transfer function presents a high pass function. The high pass function operates to expand the overall frequency bandwidth of circuit 100.
Compared to the prior art circuit illustrated in
The ground-referenced CML buffer circuit 300 is a buffer circuit taking PMOS transistors M1102 and M2104 as a differential logic pair. The gate electrode of PMOS transistor M1102 is connected to input line IN+ 114, the source electrode is connected to constant-current source 11112, and the drain electrode is connected to output line Out− 118 and load element R1106. Load element R1106 is also coupled to a ground 107. The gate electrode of PMOS transistor M2104 is connected to input line IN− 116, the source electrode is connected to constant current source I1112, and the drain electrode is connected to output line Out+ 120 and load element R2108. Load element R2108 is also coupled to ground 107. Constant current source I1112 is coupled to a supply voltage Vdd 110.
Referring again to
Although example circuit configurations have been described in certain example of the invention, one of ordinary skill in the art will recognize that except as otherwise described herein other configurations and components may be used to perform similar functions. While the exemplary embodiments of the present invention are described and illustrated herein, it will be appreciated that they are merely illustrative and that modifications can be made to these embodiments without departing from the spirit and scope of the invention. Thus, the scope of the invention is intended to be defined only in terms of the following claims as may be amended, with each claim being expressly incorporated into this Description of Specific Embodiments as an embodiment of the invention.
