Claims
- 1. A computer system comprising a computer power management system and a plurality of computer system circuits including a CPU circuit, a plurality of input/output circuits, a system memory, a clock circuit, and a system bus which directly couples said CPU circuit with said input/output circuits and with said system memory, said computer system identifying at least predetermined ones of said plurality of computer system circuits by unique circuit addresses; said power management system comprises:
- an activity monitor directly connected to said system bus; said activity monitor further including:
- a memory circuit for storing at least one particular address range data defining an address for a particular one of said computer system circuits that is controllable by said power management system;
- an address detector operatively coupled to said system bus for receiving an address communicated over said system bus and to said memory circuit for receiving said or each address range data stored in said memory circuit and for comparing said received addresses with said or each stored address range data and for generating an address detection signal upon detecting the occurrence on said system bus of an address that is within said or each stored address range; and
- logic means, coupled to said address detector, for receiving said address detection signal and for generating an ACTIVITY signal in response to receipt of at least one address detection signal indicating occurrence on said system bus of at least one address that is within one of said stored address range;
- an activity timer, coupled to said activity monitor to receive said ACTIVITY signal and:
- (i) in response to receipt of said ACTIVITY signal, resetting said activity timer to a predetermined initial condition, and
- (ii) in response to failing to receive said ACTIVITY signal within a first predetermined period of time, generating a first TIMEOUT signal identifying that a predetermined time period has elapsed without occurrence of an activity involving one of said plurality of computer system circuits for which one of said address range data is stored in said memory circuit;
- a mode controller, for controlling an operating mode condition of at least one of said computer system circuits and being responsive to said activity monitor to control transition of said computer system circuit from a first MODE to a second MODE in response to receipt of said first TIMEOUT signal, and to control transition of said computer system circuit from said second MODE to said first MODE in response to receipt of said ACTIVITY signal; and
- a power conservation circuit responsive to said mode controller which selectively places a first group of said computer system circuit into said first MODE and places a second group comprising fewer of said computer system circuits than the first group into said second MODE, said second mode having a lower power consumption than said first mode so that power consumption of said computer system is reduced in response to the inactivity of the computer system without compromising computer system performance when activity is present including being responsive to an input from a user of the computer;
- said activity means, said activity timer, said mode controller, and said power conservation circuit are connected together such that said ACTIVITY signal is propagated to said mode controller by hardwired logic circuitry and said computer system circuit transitions between said second and first MODEs substantially instantaneously with generation of said ACTIVITY signal and limited only by the propagation delay of signals within said hardwired logic circuitry.
- 2. The computer system of claim 1, wherein:
- said at least one particular address range data comprises a plurality of address range data;
- said address detector comprises a plurality of logic circuits operating in parallel for performing a logical comparison between each said stored address range data and every address reference appearing on said bus to generate a plurality of detection signals; and
- said ACTIVITY signal generated by said logic means is generated by the logical ORing of said plurality of detection signals so that an address occurring on said system bus within any one of said plurality of predetermined address ranges generates sad ACTIVITY signal.
- 3. The computer system of claim 2, wherein said power management system further comprises:
- means selectably coupleable to said memory circuit over said system bus for designating and storing said plurality of address range data items into said memory circuit.
- 4. The computer system of claim 3, wherein said memory circuit comprises a data storage register storing said address range data item.
- 5. The computer system of claim 3, wherein said activity monitor, said mode controller, said power conservation circuit, and said activity timer are implemented in hardware distinct from said CPU hardware and operate substantially independently from operating system or application program software executing with said computer system.
- 6. The computer system of claim 5, wherein said power management system further comprises an index register for storing pointers to said memory circuit storing address range data, and wherein said means for designating and storing said address range data is selectable coupled to said system bus only when enabled by said index register, thereby preventing inadvertent access to said memory circuit by operating system or application program execution on said computer system.
- 7. The computer system of claim 1 wherein:
- said activity timer generates a second TIMEOUT signal when no ACTIVITY signal is received from said activity monitor within a second predetermined time period after receiving said first TIMEOUT signal;
- said mode controller controlling transition of one of said or each computer system circuit from said second MODE to a third MODE in response to said second TIMEOUT signal; and
- said power conservation circuit places a third group comprising fewer of said computer system circuits than the second group into said third MODE, said third mode having a lower power consumption than said second mode, thereby further reducing the power consumption of said computer system in response to the continued inactivity of said computer system.
- 8. The computer system in claim 1, further comprising activity mask means for selectively storing an identified address range for which occurrence of an address on said system bus is to be ignored independent of said plurality of predetermined address range data items stored in said memory circuit; said activity mask means preventing generation of said detected address signal by said activity detector.
- 9. The computer system of claim 8, wherein said activity mask means comprises a mask memory storage register for storing said address ranges to be ignored, and further comprising programming means selectably coupleable to said mask memory register for designating and storing said address ranges to be ignored.
- 10. The computer system in claim 1, wherein said power conservation circuit comprises a power switching circuit, responsive to said mode controller which couples a power source for energizing said computer system circuits to said first group of computer system circuits in said first MODE, and couples said power source to a second group comprising fewer of said computer system circuits than the first group in said second MODE.
- 11. The computer system in claim 10, wherein said power switching circuit further comprises:
- a plurality of power data storage registers, said plurality corresponding to the number of operating MODES configured for said system and each particular one of said plurality of power data register being associated with a particular operating MODE, each said power data storage register storing only one of either an ON or OFF power state indicator for said or each computer system device during operation in said particular operating MODE; and
- a plurality of switch means, each said switch means operatively connected between said power source and one of said computer system device for alternatively passing or blocking electrical power from said power source to said computer system device;
- said switch means being responsive to said power state indicator pass electrical power from said power source to said computer system device when said power state indicator is ON, and to block electrical power to said computer system device when said power state indicator is OFF.
- 12. The computer system in claim 1, wherein said power conservation circuit comprises a clock controller circuit, responsive to said mode controller which couples a first clock signal source to said first group of computer system circuits in said first MODE, and couples a second clock signal to a second group in said second MODE, said second clock frequency having a lower clock frequency than said first clock so that operation of said second group of computer circuits consumes less power than said first group in said first mode.
- 13. The computer system in claim 12, wherein said power conservation circuit further comprises clock switching means for selectively coupling either said first clock signal source or said second clock signal source to selected ones of said computer circuits.
- 14. The computer system in claim 1, wherein said power conservation circuit comprises a computer system circuit clock controller circuit and a power switching circuit, each responsive to said mode controller, said power conservation circuit couples a power source for energizing said computer system circuits and couples a first clock signal source for operating said computer system circuits to said first group of computer system circuits in said first MODE, and couples said power source and couples a second clock signal to a second group comprising fewer of said computer system circuits than the first group in said second MODE.
- 15. The apparatus in claim 1, wherein said memory circuit is a memory circuit separate from said system memory.
- 16. The computer system of claim 1, wherein said transition between said second and first MODE occurs within approximately 1 second of activity resulting in generation of said ACTIVITY signal.
- 17. The computer system of claim 1, wherein said transition between said second and first MODE occurs within approximately 50 milliseconds of activity resulting in generation of said ACTIVITY signal.
- 18. The computer system of claim 1, wherein said transition between said second and first MODE occurs within approximately one clock cycle of activity resulting in generation of said ACTIVITY signal.
- 19. The computer system of claim 1, wherein said computer power management system and said plurality of computer system circuits are co-located with said power management system and wherein each of said power management system and said plurality of computer system circuits are powered by a common battery power source.
- 20. A power management system for use in a computer system comprising a plurality of computer system devices including a CPU device, a plurality of peripheral devices, a system memory, and a system bus which couples said CPU device with said peripheral devices and with said system memory, said computer system identifying at least a predetermined one of said plurality of computer system devices by unique device address; said power management system comprises:
- an activity monitor directly connected to said system bus; said activity monitor further including:
- a memory device for storing at least one particular address range data defining an address for a particular one of said computer system devices that is controllable by said power management system;
- an address detector operatively coupled to said system bus for receiving addresses communicated over said system bus and to said memory device for receiving said or each address range data stored in said memory device and for comparing said received addresses with said or each stored address range data and for generating an address detection signal indicating the occurrence on said system bus of an address within said or each stored address range; and
- logic means, coupled to said address detector for receiving said or each address detection signal and for generating an ACTIVITY signal in response to at least one detection signal indicating occurrence on said system bus of at least one addresses that is within one of said or each particular address range;
- an activity timer, coupled to said activity monitor to receive said ACTIVITY signal and:
- (i) in response to receipt of said ACTIVITY signal, resetting said activity timer to a predetermined initial condition, and
- (ii) in response to failing to receive said ACTIVITY signal within a first predetermined period of time, generating a first TIMEOUT signal identifying that a predetermined time period has elapsed without occurrence of an activity involving one of said computer system devices for which one of said address range data is stored in said memory device;
- a mode controller, for controlling an operating mode condition of at least one of said computer system devices and being responsive to said activity monitor; said mode controller controlling transition of at least one of said computer system devices from a first MODE to a second MODE in response to receipt of said first TIMEOUT signal, and controlling transition of said or each computer system device from said second MODE to said first MODE in response to receipt of said ACTIVITY signal; and
- a power conservation device responsive to said mode controller which selectively places a first group of said or each computer system device into said first MODE and places a second group comprising fewer of said computer system devices than the first group into said second MODE, said second mode having a lower power consumption than said first mode so that power consumption of said computer system is reduced in response to the inactivity of the computer system without compromising computer system performance when activity is present;
- said activity means, said activity timer, said mode controller, and said power conservation circuit are connected together such that said ACTIVITY signal is propagated to said mode controller by hardwired logic circuitry and said computer system circuit transitions between said second and first MODEs substantially instantaneously with generation of said ACTIVITY signal and limited only by the propagation delay of signals within said hardwired logic circuitry.
- 21. The computer system of claim 20, wherein:
- said at least one particular address range data comprises a plurality of address range data;
- said detector comprises a plurality of logic circuits operating in parallel for performing a logical comparison between of each said stored address range data and every address reference appearing on said bus to generate a plurality of detection signals; and
- said ACTIVITY signal generated by said logic means is generated by the logical ORing of said plurality of detection signals so that an address occurring on said system bus within any one of said plurality of predetermined address ranges generates said ACTIVITY signal.
- 22. The computer system of claim 21, wherein said power management system further comprises:
- means selectably coupleable to said memory circuit over said system bus for designating and storing said plurality of address range data items into said memory circuit.
- 23. The computer system of claim 22, wherein said memory circuit comprises a data storage register storing said address range data item.
- 24. The computer system of claim 22, wherein said activity monitor, said mode controller, said power conservation circuit, and said activity timer are implemented in hardware distinct from said CPU hardware and operate substantially independently from operating system or application program software executing with said computer system.
- 25. The computer system of claim 24, wherein said power management system further comprises an index register for storing pointers to said memory circuit storing address range data, and wherein said means for designating and storing said address range data is selectably coupled to said system bus only when enabled by said index register, thereby preventing inadvertent access to said memory circuit by operating system or application program execution on said computer system.
- 26. The computer system of claim 20, wherein:
- said activity timer generates a second TIMEOUT signal when no ACTIVITY signal is received from said activity monitor within a second predetermined time period after receiving said first TIMEOUT signal;
- said mode controller controlling transition of said or each computer system circuit from said second MODE to a third MODE in response to said second TIMEOUT signal; and
- said power conservation circuit places a third group comprising fewer of said computer system circuits than the second group into said third MODE, said third mode having a lower power consumption than said second mode, thereby further reducing the power consumption of said computer system in response to the continued inactivity of said computer system.
- 27. A method for operating a computer system having a plurality of computer system circuits including a CPU, an input/output circuit, and a memory for storing data and instructions, and a system bus directly connected to each of said CPU, input/output circuit, and memory, said computer system capable of being operated in any one of a plurality of functional power modes; said method comprises the steps of:
- storing a plurality of address selection data bits identifying an address range of a plurality of said computer system circuits selected for activity monitoring in said memory;
- monitoring addresses propagated on the system bus;
- generating an ACTIVITY indicator if an address propagated on the system bus is an address identified by the stored address selection data bits;
- generating a first TIMEOUT indicator when no ACTIVITY indicator is generated within a first predetermined time period;
- switching the functional power mode of the computer system from a first MODE to a second MODE in response to the first TIMEOUT indicator, said switching from said first MODE to said second MODE capable of occurring substantially instantaneously with receipt of said first TIMEOUT indicator;
- coupling a power supply to a first predetermined group of the computer system circuits when the computer system is in the first MODE;
- coupling the power supply to a second predetermined group comprising fewer of the computer system circuits than the first predetermined group when the computer system is in the second MODE;
- whereby the power consumption of the computer system is controlled in response to the activity of the computer system.
- 28. The method of claim 27, further comprising the steps of switching the power mode of the computer system from said second MODE to said first MODE in response to the ACTIVITY indicator, said switching from said second MODE to said first MODE capable of occurring substantially instantaneously with receipt of said ACTIVITY indicator, said ACTIVITY indicator propagated by hardwired logic circuits such that the only delay in said power mode switching from said second MODE to said first MODE is a delay associated with propagation of said ACTIVITY indicator through said logic circuits.
- 29. The method of claim 27 further comprising the steps of:
- generating a second TIMEOUT indicator when no ACTIVITY signal is generated within a second predetermined period after generating the firs TIMEOUT indicator;
- switching the power mode of the computer system from the second MODE to a third MODE in response to the second TIMEOUT signal;
- and coupling the power supply to a third predetermined group comprising fewer of the computer system circuits than the second predetermined group when the computer system is in the third MODE.
- 30. The method of claim 29 further comprising the step of switching the power mode of the computer system from the third MODE to the first MODE in response to the ACTIVITY indicator.
- 31. An activity monitor for use in a computer system having a plurality of computer system devices including a processor and an input/output device, and a bus which directly connects said processor with said input/output device and with said activity monitor, said computer system identifying at least one of said plurality of computer system devices by a device address communicated over said bus; said activity monitor further comprising:
- a memory configured for storing an address range data defining a particular range of device addresses;
- detector means, operatively coupled to said bus for monitoring address references communicated over said bus and to said memory for reading said stored address range data, and for comparing said address references with said address range data to generate an activity signal indicating that an address communicated over said bus was within the address range specified by one of said stored address range data;
- an activity timer, operatively coupled to said detector means to receive said activity signal if generated, and either: (i) in response to receipt of said activity signal within a first predetermined period of time, resetting said activity timer to a predetermined condition, and (ii) in response to failing to receive said activity signal within said first predetermined period of time, generating a first timeout signal;
- a mode controller, operatively coupled to said activity timer by a first hard-wired logic circuit to receive said first timeout signal and to said detector means by a second hard-wired logic circuit to receive said activity signal, for controlling an operating condition of at least one of said computer system devices;
- said mode controller controlling transition of at least one of said or each computer system device from a first mode to a second mode in response to receipt of said first timeout signal, and controlling transition of at least one of said or each computer system device from said second mode to said first mode in response to receipt of said activity signal; said first mode to second mode and said second mode to first mode transitions respectively occurring substantially simultaneously with said generation of said activity signal and said timeout signal.
- 32. The activity monitor in claim 31, wherein said mode controller generates a mode control signal; wherein said computer system further comprises a power conservation circuit responsive to said mode control signal, which selectively places a predetermined one of said computer system devices into said second operating mode condition, said second operating mode condition consuming less power than said first operating mode condition.
- 33. The activity monitor in claim 32, wherein said second operating mode condition for said particular computer system device is an operating condition selected from the group consisting of: (a) said particular device is powered-down, (b) said device is operated at a clock rate that is less than the maximum clock rate at which said device may be operated, and (c) combinations thereof.
- 34. The activity monitor in claim 32, further comprising:
- an activity mask register storing an excluded address range operatively coupled to said detector for communicating said excluded address range to said detector and identifying a range of device addresses for which references communicated over said bus are to be ignored;
- mask logic means for preventing generation of an activity signal based on activity associated with said computer system device having an address within said excluded address range.
- 35. The activity monitor in claim 31, wherein said activity range data defines a single device address.
- 36. The activity monitor in claim 31, wherein said activity range data defines a plurality of device address.
- 37. In a computer system having a plurality of computer system devices including a processor, an input/output device, a memory, and a bus directly connecting said processor, said input/output device, and said memory, and wherein said computer system identifies at least one of said plurality of computer system devices by a device address communicated over said bus; a method for monitoring computer system device activity comprising the steps of:
- storing an address range data defining a particular range of device addresses;
- detecting the occurrence of an address reference on said bus that is within said particular range of device addresses, said detection including the steps of:
- monitoring address references communicated over said bus;
- comparing each said address reference with said stored address range data; and
- generating an activity signal indicating that an address reference communicated over said bus was within the address range specified by said stored address range data;
- initializing a timer upon every generation of said activity signal;
- storing a first timeout duration;
- incrementing said timer to generate an elapsed time indicator;
- comparing said elapsed time indicator with said first timeout duration;
- generating a first timeout signal when said elapsed time indicator exceeds said first timeout duration; and
- controlling an operating condition of at least one of said computer system devices in response to said generation of said first timeout signal and said generation of said activity signal by: (i) controlling transition of said or each computer system device from a first mode to a second mode in response to receipt of said first timeout signal, and (ii) controlling transition of said or each computer system device from said second mode to said first mode in response to receipt of said activity signal;
- said transition from said first mode to said second mode occurring substantially simultaneously with receipt of said timeout signal, said timeout signal propagated by first hard-wired logic circuits such that the any time delay in said power mode transition from said first mode to said second mode is a delay associated with propagation of said timeout signal through said hard-wired logic circuits;
- said transition from said second mode to said first mode occurring substantially simultaneously with receipt of said activity signal, said activity signal propagated by second hard-wired logic circuits such that the any time delay in said power mode transition from said second mode to said first mode is a delay associated with propagation of said activity signal through said hard-wired logic circuits; and
- said step of controlling including predefining an operating condition for each of said computer devices in each of said first and second modes, prestoring a plurality of device control bits in a storage register for controlling a power consumption of said devices, and selectively multiplexing said control bits corresponding to said first mode or to said second mode to a plurality of switches to control said operating mode.
- 38. The method in claim 37, wherein said step of controlling further comprises the step of generating a mode control signal;
- selectively configuring a predetermined one of said computer system devices into said second operating mode condition in response to generation of said mode control signal, said second operating mode condition consuming less power than said first operating mode condition.
- 39. The method in claim 38, wherein said step of selectively configuring further comprises configuring said predetermined one of said computer system devices to power-off.
- 40. The method in claim 39, wherein said step of selectively configuring further comprises configuring said predetermined one of said computer system devices to operate at a clock rate that is less than the maximum clock rate at which said device may be operated.
- 41. The method in claim 39, further comprising:
- storing a predetermined excluded address range defining a range of addresses for which references communicated over said bus are to be ignored;
- preventing generation of said activity signal based on activity associated with said computer system device having an address within said excluded address range.
- 42. The method in claim 37, wherein said transition from said first mode to said second mode occurring within about 1 second of receipt of said timeout signal, and said transition from said second mode to said first mode occurring within from approximately 25 milliseconds to approximately 1 second of receipt of said activity signal.
- 43. The method in claim 42, wherein said transition from said first mode to said second mode is programmably controllable from about 1 second to about 15 seconds with a resolution of about 1 second.
- 44. The method in claim 37, wherein said transition from said first mode to said second mode occurring within less than about 50 milliseconds of receipt of said timeout signal, and said transition from said second mode to said first mode occurring within less than about 50 milliseconds of receipt of said activity signal.
- 45. A computer system comprising a power management system and a plurality of computer system circuits including a processor circuit, a plurality of input/output circuits, a system memory, and a system bus which directly couples said processor circuit with said input/output circuits and with said system memory, said computer system identifying each of said plurality of computer system circuits by a unique circuit address; said power management system comprises;
- an activity monitor directly connected to said system bus including:
- a memory circuit for storing at least one device address range which includes a device address for a particular one of said computer system circuits;
- an address detector coupled to said system bus to receive an address communicated over said system bus and to said memory circuit for receiving sad address range and for comparing said received addresses with said store address range and for generating an address detection signal upon detecting the occurrence of a circuit address on said system bus that is within said address range;
- a logic circuit, coupled to said address detector, for receiving said address detection signal and for generating an ACTIVITY signal in response to receipt of said address detection signal; and
- an activity timer, coupled to maid activity monitor to receive said ACTIVITY signal and: (i) in response to receipt of said ACTIVITY signal, resetting said activity timer to a predetermined initial condition, (ii) in response to failing to receive said ACTIVITY signal within a first predetermined period of time, generating a first TIMEOUT signal identifying that a predetermined time period has elapsed without occurrence of an activity involving one of said plurality of computer system circuits for which one of said address range data is stored in said memory circuit, and (iii) said activity timer generates a second TIMEOUT signal when no ACTIVITY signal is received from said activity monitor within a second predetermined time period after receiving said first TIMEOUT signal;
- a mode controller, for controlling an operating mode condition of at least one of said computer system circuits and being responsive to said activity monitor to control transition of said computer system circuit from a first MODE to a second MODE in response to receipt of said first TIMEOUT signal, to control transition of at least one of of said computer system circuits from said second MODE to a third MODE in response to said send TIMEOUT signal, and to control transition of said computer system circuit from either said second MODE or said third mode to said first MODE in response to receipt of said ACTIVITY signal;
- a power conservation circuit responsive to said mode controller which selectively places a first group of said computer system circuit into said first MODE and places a second group comprising fewer of said computer system circuits than the first group into said second MODE, said second mode having a lower power consumption than said first mode, and selectively places a third group comprising fewer of said computer system circuits than the second group into said third MODE, said third mode having a lower power consumption than said second mode, thereby further reducing the power consumption of said computer system in response to the continued inactivity of said computer system;
- said power conservation circuit including a first register storing first switch control signals for controlling operation of said computer devices in said first mode, a second register storing second switch control signals for controlling operation of said computer devices in said second mode, a third register storing third switch control signals for controlling operation of said computer devices in said third mode, and a control register for receiving said first or said second switch control signals, and a signal selector circuit for selecting which of said first, second, and third switch control signals are communicated to said control register;
- whereby power consumption of said computer system is reduced in response to the actual monitored inactivity of said computer system devices without compromising computer system performance when activity is present.
- 46. A computer system comprising a power management system and a plurality of computer system circuits including a CPU circuit, a plurality of input/output circuits, a system memory, and a system bus which directly couples said CPU circuit with said input/output circuits and with said system memory, said computer system identifying at least predetermined ones of said plurality of computer system circuits by unique circuit addresses; said power management system comprises:
- an activity monitor directly connected to said system bus; said activity monitor further including:
- a memory circuit for storing at least one particular address range data defining an address for a particular one of said computer system circuits that is controllable by said power management system;
- an address detector operatively coupled to said system bus for receiving an address communicated over said system bus and to said memory circuit for receiving said or each address range data stored in said memory circuit and for comparing said received addresses with said or each stored address range data and for generating an address detection signal upon detecting the occurrence on said system bus of an circuit address that is within said or each stored address range; and
- logic means, coupled to said address detector, for receiving said address detection signal and for generating an ACTIVITY signal in response to receipt of at least one address detection signal indicating occurrence on said system bus of at least one address that is within one of said stored address range;
- an activity timer, coupled to said activity monitor to receive said ACTIVITY signal and:
- (i) in response to receipt of said ACTIVITY signal, resetting said activity timer to a predetermined initial condition, and
- (ii) in response to failing to receive said ACTIVITY signal within a first predetermined period of time, generating a first TIMEOUT signal identifying that a predetermined time period has elapsed without occurrence of an activity involving one of said plurality of computer system circuits for which one of said address range data is stored in said memory circuit;
- a mode controller, for controlling an operating mode condition of at least one of said computer system circuits and being responsive to said activity monitor to control transition of said computer system circuit from a first MODE to a second MODE in response to receipt of said first TIMEOUT signal, and to control transition of said computer system circuit from said second MODE to said first MODE in response to receipt of said ACTIVITY signal; and
- a power conservation circuit responsive to said mode controller which selectively places a first group of said computer system circuit into said first MODE and places a second group comprising fewer of said computer system circuits than the first group into said second MODE, said second mode having a lower power consumption than said first mode so that power consumption of said computer system is reduced in response to the inactivity of the computer system without compromising computer system performance when activity is present; and
- wherein said power management system operates independently of said CPU, said mode controller controls an operating mode condition of said CPU, and wherein said second mode is a power conservation mode that reduces power consumption by said CPU.
CROSS REFERENCE RELATED U.S. PATENT APPLICATION
This application is a continuation of application Ser. No. 08/285,169 filed Aug. 3, 1994, which is a continuation of application Ser. No. 08/017,975 filed Feb. 12, 1993 now U.S. Pat. No. 5,396,635, which is a continuation of application Ser. No. 07/908,533 filed Jun. 29, 1992 which is a continuation of application Ser. No. 07/532,314 filed Jun. 1, 1990.
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Continuations (4)
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285169 |
Aug 1994 |
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17975 |
Feb 1993 |
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Jun 1992 |
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Patent Grant
5799198
