Patent Application
20120200440
The disclosure of Japanese Patent Application No. 2011-23791 filed on Feb. 7, 2011 including the specification, drawings and abstract is incorporated herein by reference in its entirely.
The present invention relates to an A/D converter and a semiconductor device, and more particularly to a continuous-time sigma-delta A/D converter and a semiconductor device using the same.
In electronic devices, a process of converting an analog signal into a digital signal is conducted by an analog-digital converter (hereinafter referred to as “A/D converter”). As an example of the A/D converter, a continuous-time delta-sigma A/D converter using, for example, a delta-sigma converter has been known (Japanese Unexamined Patent Application Publication No. 2006-333053). In the continuous-time delta-sigma A/D converter, an integrator formed of a resistor and a capacitor is used. For that reason, no sampling is required so that a bandwidth of an amplifier can be relaxed. This results in such a feature that the continuous-time delta-sigma A/D converter can operate at a relatively high speed.
Hereinafter, a description will be given of the normal continuous-time delta-sigma A/D converter with reference to
The integrator 41 includes an amplifier AMP41, a resistor Ri, and a capacitor Cs. An inverting input of the amplifier AMP41 is coupled to an input X through the resistor Ri. Also, an input and an output of the amplifier AMP41 are coupled to each other through the capacitor Cs. A non-inverting input of the amplifier AMP41 is grounded (GND). The comparator 42 includes an amplifier AMP42. An non-inverting input of the amplifier AMP42 is coupled to an output of the amplifier AMP41. A non-inverting input of the amplifier AMP41 is grounded (GND). An output of the amplifier AMP42 is coupled to an output Y. The feedback D/A converter 43 includes a D/A converter decoder 44, a resistor RDAC, and a switch 45. The D/A converter decoder 44 supplies differential signals (φ+ and φ−) obtained by decoding the output Y according to a sampling clock SCLC to the switch 45. The switch 45 supplies a voltage +Vref or −Vref to the inverting input of the amplifier AMP41 through resistor RDAC according to the differential signals.
In the continuous-time delta-sigma A/D converter 400, if jitter occurs in the sampling clock SCLC of the feedback D/A converter 43, noise (jitter component) is superimposed on a charge amount fed back by the feedback D/A converter 43. This results in such a problem that the performance of an overall system is deteriorated.
As a measure against this problem, there has been known, for example, a continuous-time delta-sigma A/D converter in which a switched capacitor including a resistor and a capacitor is disposed in a feedback D/A converter (Maurits Ortmanns, et al. “A Continuous-Time Sigma-Delta Modulator with Reduced Jitter Sensitivity”, Proc. ESSCIRC, 2002, pp. 287-290.
In the above-mentioned continuous-time delta-sigma A/D converter, an integrator includes a resistor and a capacitor. For that reason, the integrator has an RC time constant determined according to the resistor and the capacitor. The RC time constant is a significant parameter for determining a noise shaping characteristic of the continuous-time delta-sigma A/D converter. For that reason, variations (hereinafter referred to as “RC variations”) in a resistance value and a capacitance value, which are attributable to manufacturing variations or temperature change, cause an S/N ratio of an output signal to be deteriorated.
As a method of correcting the RC variations, a configuration providing a circuit for correcting the RC variations has been generally known (Japanese Unexamined Patent Application Publication No. 2009-284130).
In this situation, the digital signal S2 is set to a value allowing a product of the resistance value of the resistor 72 and the capacitance value of the capacitor 62 to be kept constant. For that reason, when the digital signal S2 is input to a programmable filter 51, the RC variations of the filter 51 are corrected so that a cutoff frequency of the filter 51 can be maintained. This method is intended to keep the cutoff frequency of the filter constant by correcting the RC variations, but may be also applied to a reduction in the RC variations of the continuous-time delta-sigma A/D converter.
However, the present inventors have found out that a technique for correcting the RC variations of the continuous-time delta-sigma A/D converter by the above-mentioned correcting circuit poses a problem. In this technique, it is essential to provide another correcting circuit in addition to the circuit to be corrected in the RC variations (for example, the filter 51 in
According to one aspect of the present invention, there is provided a semiconductor device including: a delta-sigma modulator that can change a time constant of an internal circuit according to a control signal; a switching circuit that selectively inputs any one of an input signal and a given reference voltage to the delta-sigma modulator; and a control circuit that is coupled to an output of the delta-sigma modulator and generates the control signal. In the semiconductor device according to the aspect of the present invention, the switching circuit applies the given reference voltage to the delta-sigma modulator. The control circuit monitors the output of the delta-sigma modulator, and can adjust the time constant of the internal circuit of the delta-sigma modulator according to the control signal so that the output becomes a desired value.
According to another aspect of the present invention, there is provided a A/D converter, including: an integrator that includes a first resistor and a first capacitor, and has a time constant determined according to the first resistor and the first capacitor; a quantizer that quantizes an output of the integrator; a feedback D/A converter that converts a digital signal from the quantizer into an analog signal, and feeds back the converted analog signal to the integrator; a first switch that selectively supplies an input amplitude voltage or a first reference voltage from a reference voltage generator to the integrator; and a control circuit that controls the switching operation of the first switch, and controls the time constant of the integrator according to a digital output generated according to the digital signal from the quantizer. In the A/D converter according to the aspect of the present invention, the control circuit controls the first switch to supply the reference voltage to the integrator. The control circuit monitors the digital output, and can adjust the time constant of the integrator so that the digital output becomes a desired value.
The A/D converter and a semiconductor device simple in configuration can be provided which can keep a constant noise shaping characteristic without depending on manufacturing variations or a temperature change.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the respective drawings, identical elements are denoted by the same reference symbols, and repetitive description will be omitted as needed.
First, a semiconductor device 1000 according to a first embodiment will be described.
The A/D converter 100 includes a delta-sigma modulator 101, an input changeover switch 11, and a control logic circuit 5. The delta-sigma modulator 101 includes an integrator 21, a quantizer 4, and a feedback digital-analog converter (hereinafter referred to as “feedback D/A converter”) 31.
The input changeover switch 11 receives a reference voltage Vrefc from the reference voltage generator 6. Also, the input changeover switch 11 receives an input amplitude voltage Vin from the external. The input changeover switch 11 outputs any one of reference voltage Vrefc and the input amplitude voltage Vin to the integrator 21 according to a control signal Scon from the control logic circuit 5. At least one of the reference voltages is applied to the input changeover switch 11 from the reference voltage generator 6.
The integrator 21 includes a variable resistor R21, an amplifier AMP, and a capacitor C21. The integrator 21 is coupled between an output of the input changeover switch 11 and an input of the amplifier AMP. The variable resistor R21 has a resistance value controlled according to a control signal Rcon from the control logic circuit 5. An output of the amplifier AMP is connected to an input of the quantizer 4. The capacitor C21 is connected between the input and the output of the amplifier AMP.
The quantizer 4 quantizes an output from the integrator 21, and outputs a quantized PDM (pulse density modulation) signal PDM to the control logic circuit 5 and the feedback D/A converter 31. In this example, the PDM signal PDM is a digital signal having a pulse density modulated according to a magnitude of the input signal.
The feedback D/A converter 31 is configured by a resistor R31, a switch SW, and a capacitor C31 which are coupled in series between the input of the amplifier AMP and the ground. The switch SW is switched by the PDM signal PDM from the quantizer 4. With this configuration, the switch SW couples the resistor R31 and the capacitor C31, or applies a reference voltage Vref from the reference voltage generator 6 to the capacitor C31, to charge the capacitor C31.
The control logic circuit 5 includes a digital output generator 5a and a comparator 5b. The digital output generator 5a has, for example, a decimation filter that is a DSP (digital signal processor). The digital output generator 5a receives the PDM signal PDM from the quantizer 4, and converts the received PDM signal PDM into a digital output (digital code) DO through the decimation filter. The comparator 5b compares an expected value stored in advance with a value of the digital output DO. The comparator 5b generates the control signals Scon, Rcon, and Vcon according to the comparison result.
The reference voltage generator 6 receives the control signal Vcon from the control logic circuit 5, and applies the reference voltage Vrefc of a value corresponding to the control signal Vcon to the input changeover switch 11. Also, the reference voltage generator 6 applies the reference voltage Vref to the switch SW of the feedback D/A converter 31. The reference voltage generator 6 can also control a value of the reference voltage Vref according to the control signal Vcon.
Subsequently, a relationship between the input and the output of the delta-sigma modulator 101 will be described.
In the case of the delta-sigma modulator 101, when it is assumed that an input amplitude voltage is Vin, a unit time is Ts (clock period), and a resistance value of the variable resistor R21 is Rin, the input X per the unit time is represented by the following Expression (1).
Also, when it is assumed that the capacitance value of the capacitor C31 is Cdac, the feedback amount V per the unit time is represented by the following Expression (2).
V=Cdac×Vref
As described above, the digital output DO is proportional to X/Y. Accordingly, the digital output DO is represented by the following Expression (3).
A case in which the known reference voltage Vrefc is input instead of the input amplitude voltage Vin will be studied. The reference voltage Vrefc is a constant voltage generated by a band gap reference circuit. Hence, the reference voltage Vrefc is maintained at a constant value not depending on the manufacturing variations or the temperature change. In this case, the resistance value Rin of the variable resistor R21, the capacitance value Cdac of the capacitor C31, and the value of the reference voltage Vref are held constant, the digital output DO becomes a given expected value.
The reference voltage Vref is a constant value generated by the band gap reference circuit as with the reference voltage Vrefc. Hence, the reference voltage Vref is maintained at a constant value not depending on the manufacturing variations or the temperature change. Accordingly, the variation of the digital output DO depends on only the variations (hereinafter referred to as “RC variations”) of the resistance value Rin of the variable resistor R21 and the capacitance value Cdac of the capacitor C31, which are attributable to the manufacturing variations and the temperature change.
Subsequently, the operation of the semiconductor device 1000 according to this embodiment will be described. The control logic circuit 5 calibrates the delta-sigma modulator 101 according to a calibration start signal (not shown) from the external. For calibration, the comparator 5b sets the value of the reference voltage Vrefc output from the reference voltage generator 6 according to the control signal Vcon. Then, the comparator 5b switches the connection of the input changeover switch 11 to the reference voltage Vrefc side according to the control signal Scon.
Thereafter, the digital output generator 5a monitors the PDM signal PDM in a state where the reference voltage Vrefc is applied to the integrator 21. In this example, the expected value of the digital output DO to the set reference voltage Vrefc (input X) is stored in the comparator 5b in advance. The comparator 5b compares the digital output DO with the expected value. The comparator 5b adjusts the resistance value of the variable resistor R21 in the integrator 21 according to the comparison result. That is, the control logic circuit 5 can adjust the RC time constant of the integrator 21.
If the digital output DO is smaller than the expected value, the comparator 5b makes the resistance value of the variable resistor R21 smaller. On the other hand, if the digital output DO is larger than the expected value, the comparator 5b makes the resistance value of the variable resistor R21 larger so that the value of the digital output DO becomes the expected value. As a result, the control logic circuit 5 determines the resistance value of the variable resistor R21 so that the value of the digital output DO matches the expected value.
If the adjustment of the resistance value of the variable resistor R21 has been completed, the comparator 5b switches the input changeover switch 11 to the input amplitude voltage Vin side according to the control signal Vcon to complete the calibration operation.
The variable resistor R21 is configured by multiple resistors R, and the number of resistors R coupled in series or in parallel is changed so that the resistance value of the variable resistor R21 can be changed. In this configuration, the resistance value of the variable resistor R21 is discretely changed.
According to this configuration, the delta-sigma modulator can be calibrated by a control logic circuit with a simple configuration. For that reason, there is no need to additionally provide the circuit for correcting the RC variations illustrated in
Subsequently, a semiconductor device 2000 according to a second embodiment will be described.
The integrator 22 has a resistor R22, the amplifier AMP, and a variable capacitor C22. The resistor R22 is coupled between the output of the input changeover switch 11 and the input of the amplifier AMP. The output of the amplifier AMP is connected to the input of the quantizer 4. The variable capacitor C22 is coupled between the input and the output of the amplifier AMP. The variable capacitor C22 has a capacitance value controlled according to the control signal Ccon1 from the control logic circuit 5.
The feedback D/A converter 32 has a configuration in which the capacitor C31 of the feedback D/A converter 31 is replaced with a variable capacitor C32. The variable capacitor C32 has a capacitance value controlled according to the control signal Ccon2 from the control logic circuit 5. The other configurations of the feedback D/A converter 32 are identical with those of the feedback D/A converter 31, and therefore their description will be omitted.
Subsequently, the operation of the semiconductor device 2000 according to this embodiment will be described. In this embodiment, the resistance value of the resistor R22 is Rin, the capacitance value of the variable capacitor C22 is Cf, and the capacitance value of the variable capacitor C32 is Cdac. Hence, even in the semiconductor device 2000, the above Expressions (1) to (3) are established.
The control logic circuit 5 calibrates the delta-sigma modulator 201 according to a calibration start signal (not shown) from the external. For calibration, the comparator 5b sets the value of the reference voltage Vrefc output from the reference voltage generator 6 according to the control signal Vcon. Then, the comparator 5b switches the connection of the input changeover switch 11 to the reference voltage Vrefc side according to the control signal Scon.
Thereafter, the digital output generator 5a monitors the PDM signal PDM in a state where the reference voltage Vrefc is applied to the integrator 22. In this example, the expected value of the digital output DO to the set reference voltage Vrefc (input X) is stored in the comparator 5b in advance. The comparator 5b compares the digital output DO with the expected value. The comparator 5b adjusts the capacitance value Cdac of the variable capacitor C32 in the feedback D/A converter 32 according to the comparison result.
If the digital output DO is smaller than the expected value, the comparator 5b makes the capacitance value Cdac of the variable capacitor C32 smaller so that the value of the digital output DO approaches the expected value. On the other hand, if the digital output DO is larger than the expected value, the comparator 5b makes the capacitance value Cdac of the variable capacitor C32 larger so that the value of the digital output DO approaches the expected value.
Also, the capacitance value Cdac of the variable capacitor C32 and the capacitance value Cf of the variable capacitor C32 in the integrator 22 have the same variations. Hence, the comparator 5b adjusts the capacitance value Cf of the variable capacitor C22 in correspondence with the adjustment range of the capacitance value Cdac of the variable capacitor C32. That is, the control logic circuit 5 can adjust the RC time constant of the integrator 22.
If the areas of the variable capacitors C22 and C32 are equal to each other, the comparator 5b adjusts the capacitance value Cf of the variable capacitor C22 by the adjustment range of the capacitance value Cdac of the variable capacitor C32. Also, if the areas of the variable capacitors C22 and C32 are different from each other, the comparator 5b adjusts the capacitance value Cf of the variable capacitor C22 by an amount obtained by multiplying the adjustment range of the capacitance value Cdac of the variable capacitor C32 by an area ratio of the variable capacitor C22 to the variable capacitor C32. As a result, the control logic circuit 5 determines the capacitance values of the variable capacitors C22 and C32 so that the value of the digital output DO matches the expected value.
If the adjustment of the capacitance value of the variable capacitors C22 and C32 has been completed, the comparator 5b switches the input changeover switch 11 to the input amplitude voltage Vin side according to the control signal Vcon to complete the calibration operation.
The variable capacitor C32 is configured by multiple capacitors C, and the number of capacitors C coupled in series or in parallel is changed so that the capacitance value of the variable capacitor C32 can be changed. In this configuration, the capacitance value Cdac of the variable capacitor C32 is discretely changed. This is also applied to the variable capacitor C22.
Hence, according to this configuration, the semiconductor device 2000 having the same effects as those of the A/D converter 100 can be provided.
Subsequently, a semiconductor device 3000 according to a third embodiment will be described.
The input changeover switch 12 has three inputs to which the reference voltage Vrefc, the reference voltage −Vrefc, and the input amplitude voltage Vin are input, respectively. The input changeover switch 12 outputs any one of the reference voltage Vrefc, the reference voltage −Vrefc, and the input amplitude voltage Vin to the integrator 21 according to the control signal Scon from the control logic circuit 5.
That is, in this embodiment, two kinds of calibration operation can be conducted on the reference voltage Vrefc and the reference voltage −Vrefc.
As illustrated in
That is, according to this configuration, the reference voltages Vrefc and −Vrefc are applied to conduct calibration, thereby enabling the characteristic of the delta-sigma modulator 101 to match the characteristic line L62. Therefore, according to this configuration, there can be provided the semiconductor device that can correct not only the RC variations (inclination of the characteristic line L61), but also the deviation of the characteristic other than the RC variations.
Subsequently, a semiconductor device 4000 according to a fourth embodiment will be described.
According to this configuration, the number of reference voltages generated by the reference voltage generator 6 can be reduced. As a result, the configuration of the reference voltage generator 6 can be simplified, and the circuit scale of the reference voltage generator 6 can be suppressed.
The present invention is not limited to the above embodiments, but can be appropriately changed without departing from the subject matter of the invention. For example, as with the fourth embodiment, even in the first to third embodiments, the same reference voltage may be applied to the input changeover switch and the switch of the feedback D/A converter. Also, as with the third embodiment, in the first, second, and fourth embodiments, the input changeover switch 11 can be replaced with the input changeover switch 12.
The first and second embodiments can be appropriately combined together to adjust the resistance value of the variable resistance and the capacitance value of the variable capacitor. Also, the input changeover switch 12 according to the third embodiment can be applied to the configuration for adjusting the resistance value of the variable resistance and the capacitance value of the variable capacitor, combining the configurations of the first and second embodiments together. Further, even in this configuration, as with the fourth embodiment, the same reference voltage may be applied to the input changeover switch and the switch of the feedback D/A converter.
In the above embodiments, the configuration using the first-order integrator that is the simplest integrator has been described as the continuous-time delta-sigma A/D converter. However, the present invention is not limited to this example. That is, a D/A converter using a second-order or higher integrator can be configured. Also, in the above-mentioned embodiments, the configuration of a single end has been described for simplifying the description. However, the same effects can be also obtained in a differential configuration.
In the above embodiments, the control logic circuit has been described as an independent circuit block. However, the control logic circuit may be incorporated into another logic circuit disposed within the semiconductor device. As usual, in the case of the continuous-time delta-sigma A/D converter, a decimation filter that converts the PDM signal PDM into a digital code is disposed at an output side of the quantizer. Accordingly, for example, the control logic circuit may be incorporated into the logic circuit in which the decimation filter is provided.
In the above embodiments, the reference voltage generator is disposed outside of the A/D converter, but may be disposed, for example, inside of the A/D converter.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-023791 | Feb 2011 | JP | national |
