ADAPTABLE DATA MODULATION IN MEMORY SYSTEMS

TECHNICAL FIELD

Implementations of the disclosure relate generally to memory sub-systems, and more specifically, to adaptable data modulation in memory systems.

BACKGROUND

A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various implementations of the disclosure.

FIG. 1 illustrates an example computing system that includes a memory sub-system in accordance with one or more aspects of the present disclosure.

FIG. 2 is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system, in accordance with one or more aspects of the present disclosure.

FIG. 3 schematically illustrates charge example distributions of memory cell charge levels, in accordance with aspects of the present disclosure.

FIG. 5 schematically illustrates an example method of data modulation implemented by a memory controller operating in accordance with aspects of the present disclosure.

FIG. 6 schematically illustrates an example method of data demodulation implemented by a memory controller operating in accordance with aspects of the present disclosure.

FIG. 7 illustrates an example machine of a computer system within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to adaptable data modulation in memory systems. A memory sub-system can include one or more storage devices, memory modules, or a combination of storage devices and memory modules. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more memory components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory sub-system can utilize one or more memory devices, including any combination of the different types of non-volatile memory devices and/or volatile memory devices, to store the data provided by the host system. In some implementations, a memory sub-system can be represented by a solid-state drive (SSD), which can include one or more non-volatile memory devices. In some implementations, the non-volatile memory devices can be provided by negative-and (NAND) type flash memory devices. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. A non-volatile memory device is a package of one or more dice. Each die can include one or more planes. A plane is a portion of a memory device that includes multiple memory cells. Some memory devices can include two or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. “Block” herein shall refer to a set of contiguous or non-contiguous memory pages. A “block” can refer to a unit of the memory device used to store data and can include a group of memory cells. An example of a “block” is an “erasable block,” which is the minimal erasable unit of memory, while “page” is a minimal writable unit of memory. Each page includes a set of memory cells. A memory cell is an electronic circuit that stores information.

A memory device can include multiple memory cells arranged in a two-dimensional grid. The memory cells are formed onto a silicon wafer in an array of columns and rows. A memory cell includes a capacitor that holds an electric charge and a transistor that acts as a switch controlling access to the capacitor. Accordingly, the memory cell can be programmed (written to) by applying a certain voltage, which results in an electric charge being held by the capacitor. The memory cells are joined by wordlines, which are conducting lines electrically connected to the control gates of the memory cells, and bitlines, which are conducting lines electrically connected to the drain electrodes of the memory cells.

Depending on the cell type, each memory cell can store one or more bits of binary information and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. A memory cell can be programmed (written to) by applying a certain voltage to the memory cell, which results in an electric charge being held by the memory cell, thus allowing modulation of the voltage distributions produced by the memory cell. A set of memory cells referred to as a memory page can be programmed together in a single operation, e.g., by selecting consecutive bitlines.

Precisely controlling the amount of the electric charge stored by the memory cell allows establishing multiple logical levels, thus effectively allowing a single memory cell to store multiple bits of information. A read operation can be performed by comparing the measured threshold voltages (Vt) exhibited by the memory cell to one or more reference voltage levels in order to distinguish between two logical levels for single-level cell (SLCs) and between multiple logical levels for multi-level cells. Each logical level can be translated into a corresponding binary representation of the content of the memory cell. In an illustrative example, a Gray code can be employed for translating the cell charge levels (voltage levels) into their respective binary representations and vice versa. A Gray code refers to an encoding in which adjacent numbers have a single digit different by one.

Memory access operations (e.g., a programming (write) operation, an erase operation, etc.) can be executed with respect to sets of the memory cells, e.g., in response to receiving memory access commands from the host. A memory access operation can specify the requested memory access operation (e.g., write, erase, read, etc.) and a logical address, which the memory sub-system would translate to a physical address identifying a set of memory cells (e.g., a block).

In order to improve endurance of a memory device, the data to be written to the memory device can be modulated to achieve a desired distribution of the charge levels in the memory cells addressable by a given wordline and, in some implementations, also in the memory cells addressable by neighboring wordlines of the given wordline. While a random data pattern encoded by a Gray code would result in uniform distribution of the memory cell charge levels (such that the number of memory cells at an arbitrary chosen charge level being roughly equal to the number of memory cells at any other charge level), employing various non-uniform distributions of memory cell charge levels (i.e., distributions in which the number of memory cells at one charge level can differ by at least a predefined value from the number of memory cells at another charge level) might result in better endurance of the memory device.

Implementations of the present disclosure implementing a flexible modulation technique that would be adaptable to accommodate various desired charge level distributions depending upon, e.g., the target location of data on the memory device.

In an illustrative example, the data to be written to a memory device (e.g., host data) can include one or more original translation units (e.g., pages). Each original translation unit can be split into multiple original data segments of a predefined size. A data modulation operation can then be performed on each original segment by combining (e.g., by an exclusive disjunction (“XOR”) operation) the original segment with a modulation mask (i.e., a sequence of bits) that is derived from a corresponding seed value. The seed value defining a modulating transformation that would result in the desired charge level distribution of the modulated data can be chosen, e.g., from a predefined set of seed values. Accordingly, a given seed value can be identified by its index (position) within a linear array of seed values, which can be stored in the metadata area of the memory sub-system, thus allowing identifying and efficient retrieval of seed values by their respective positions within the linear array.

Thus, the modulation operation can be applied to each segment of the original translation unit thus producing a corresponding modulated segment. Each modulated segment can be concatenated with a corresponding identifier of the seed value that has been used by the modulation operation. The modulated segments, each concatenated with its respective seed identifier, can be concatenated together to form a modulated translation unit, which can be further encoded before having been written to its target location of the memory device. Storing the seed identifier in association with the modulated data segment would facilitate the reverse transformation when a read operation is performed with respect to the modulated data, as described in more detail below.

Thus, the adaptable modulation scheme implemented in accordance with aspects of the present disclosure results in desired distributions (e.g., uniform or non-uniform distributions having desired shapes and/or parameters) of charge levels in memory cells addressable by a given wordline, as well as in memory cells addressable by neighboring wordlines of the given wordline.

Various aspects of the methods and systems are described herein by way of examples, rather than by way of limitation. The systems and methods described herein can be implemented by hardware (e.g., general purpose and/or specialized processing devices, and/or other devices and associated circuitry), software (e.g., instructions executable by a processing device), or a combination thereof.

FIG. 1 illustrates an example computing system 100 that includes a memory sub-system 110 in accordance with some implementations of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.

A memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory module (NVDIMM).

The computing system 100 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

The computing system 100 can include a host system 120 that is coupled to one or more memory sub-systems 110. In some implementations, the host system 120 is coupled to different types of memory sub-system 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory sub-system 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110.

The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. The host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130) when the memory sub-system 110 is coupled with the host system 120 by the physical host interface (e.g., PCIe bus). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. FIG. 1 illustrates a memory sub-system 110 as an example. In general, the host system 120 can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The memory devices 130,140 can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device 140) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device 130) include negative-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell. In some implementations, each of the memory devices 130 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some implementations, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 can be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory components such as 3D cross-point array of non-volatile memory cells and NAND type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

A memory sub-system controller 115 (“controller”) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include a digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller 115 can be a processing device, which includes one or more processors (e.g., processor 117), configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

In some implementations, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, in another implementation of the present disclosure, a memory sub-system 110 does not include a memory sub-system controller 115, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130 as well as convert responses associated with the memory devices 130 into information for the host system 120.

The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some implementations, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory sub-system controller 115 and decode the address to access the memory devices 130.

In some implementations, the memory devices 130 include local media controllers 135 that operate in conjunction with memory sub-system controller 115 to execute operations on one or more memory cells of the memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some implementations, memory sub-system 110 is a managed memory device, which includes a raw memory device 130 having control logic (e.g., local media controller 135) on the die and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

Notably, due to certain physical properties of memory cells of the memory devices 130, certain non-uniform distributions of cell charge levels can result in higher reliability and/or improved endurance of the memory cells, as compared to the reliability and endurance resulting from uniform charge level distributions.

In one embodiment, the memory sub-system 110 includes a memory interface 113. Memory interface 113 is responsible for handling interactions of memory sub-system controller 115 with the memory devices of memory sub-system 110, such as memory device 130. For example, memory interface 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed. For example, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

In some implementations, the memory sub-system 110 includes a data modulation component 134, which can perform data modulation in order to achieve the desired distributions of the memory cells charges in the memory cells addressable by a given wordline and, in some implementations, also in the memory cells addressable by neighboring wordlines of the given wordline. In an illustrative example, the data modulation component can transform the data to be written to one or more memory devices 130, e.g., by applying, to the data, one or more transformations, such that the transformed data, when converted to corresponding voltage levels, would result in the desired distributions of the memory cells charges in the memory cells addressable by a given wordline and, in some implementations, also in the memory cells addressable by neighboring wordlines of the given wordline, as described in more detail herein above.

In an illustrative example, at least part of the functionality of the data modulation component 134 can be performed by the memory interface 113. In another illustrative example, at least part of the functionality of the data modulation component 134 can be performed by the local media controller 135. In some implementations, data modulation component 134 is implemented by firmware, hardware components, or a combination of the above.

In some implementations, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

FIG. 2 is a simplified block diagram of a first apparatus, in the form of a memory device 130, in communication with a second apparatus, in the form of a memory sub-system controller 115 of a memory sub-system (e.g., memory sub-system 110 of FIG. 1), according to an implementation. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The memory sub-system controller 115 (e.g., a controller external to the memory device 130), can be a memory controller or other external host device.

Memory device 130 includes an array of memory cells 104 logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a wordline) while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bitline). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. Memory cells (not shown in FIG. 2) of at least a portion of array of memory cells 104 are capable of being programmed to one of at least two target data states.

Row decode circuitry 108 and column decode circuitry 111 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 204. Memory device 130 also includes input/output (I/O) control circuitry 112 to manage input of commands, addresses and data to the memory device 130 as well as output of data and status information from the memory device 130. An address register 114 is in communication with I/O control circuitry 112 and row decode circuitry 108 and column decode circuitry 111 to latch the address signals prior to decoding. A command register 124 is in communication with I/O control circuitry 112 and local media controller 135 to latch incoming commands.

A controller (e.g., the local media controller 135 internal to the memory device 130) controls access to the array of memory cells 104 in response to the commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations and/or erase operations) on the array of memory cells 204. The local media controller 135 is in communication with row decode circuitry 108 and column decode circuitry 111 to control the row decode circuitry 108 and column decode circuitry 111 in response to the addresses.

The local media controller 135 is also in communication with a cache register 218. Cache register 118 latches data, either incoming or outgoing, as directed by the local media controller 135 to temporarily store data while the array of memory cells 104 is busy writing or reading, respectively, other data. During a programming operation (e.g., a write operation), data can be passed from the cache register 118 to the data register 121 for transfer to the array of memory cells 204; then new data can be latched in the cache register 118 from the I/O control circuitry 212. During a read operation, data can be passed from the cache register 118 to the I/O control circuitry 112 for output to the memory sub-system controller 115; then new data can be passed from the data register 121 to the cache register 218. The cache register 118 and/or the data register 121 can form (e.g., can form a portion of) a page buffer of the memory device 130. A page buffer can further include sensing devices (not shown in FIG. 2) to sense a data state of a memory cell of the array of memory cells 204, e.g., by sensing a state of a data line connected to that memory cell. A status register 122 can be in communication with I/O control circuitry 112 and the local memory controller 135 to latch the status information for output to the memory sub-system controller 115.

Memory device 130 receives control signals at the memory sub-system controller 115 from the local media controller 135 over a control link 132. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be further received over control link 132 depending upon the nature of the memory device 130. In some implementations, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller 115 over a multiplexed input/output (I/O) bus 136 and outputs data to the memory sub-system controller 115 over I/O bus 136.

For example, the commands can be received over input/output (I/O) pins [7:0] of I/O bus 136 at I/O control circuitry 112 and can then be written into command register 224. The addresses can be received over input/output (I/O) pins [7:0] of I/O bus 136 at I/O control circuitry 112 and can then be written into address register 214. The data can be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 112 and then can be written into cache register 218. The data can be subsequently written into data register 121 for programming the array of memory cells 204.

In an implementation, cache register 118 can be omitted, and the data can be written directly into data register 220. Data can also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference can be made to I/O pins, they can include any conductive node providing for electrical connection to the memory device 130 by an external device (e.g., the memory sub-system controller 115), such as conductive pads or conductive bumps as are commonly used.

In some implementations, additional circuitry and signals can be provided, and that the memory device 130 of FIG. 2 has been simplified. It should be recognized that the functionality of the various block components described with reference to FIG. 2 can not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of FIG. 2. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of FIG. 2. Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) can be used in the various implementations.

As noted herein above, certain non-uniform distributions of cell charge levels can result in higher reliability and/or improved endurance of the memory cells, as compared to the reliability and endurance resulting from uniform charge level distributions.

FIG. 3 schematically illustrates charge example distributions of memory cell charge levels, in accordance with aspects of the present disclosure. In FIG. 3, plot 320 is an example non-uniform distribution of QLC logical levels over the frequency domain, and plot 310 is an example uniform distribution of QLC logical levels over the frequency domain. As schematically illustrated by FIG. 3, the desired non-uniform distribution 320 for the chosen example wordline can have the inner QLC levels (e.g., 1-14) within a certain frequency range (e.g., between 0.6 and 0.7), while the outer QLC levels (e.g., levels 0 and 15) would fall within a substantially lower range (e.g., between 0.3 and 0.4), such that the center of the frequency range of the outer QLC levels is by at least a predefined value (e.g., 0.3) lower than the center of the frequency range of the inner QLC levels. In some implementations, the desired distribution of the data can be predefined for each location of the memory device based on the characteristic features of the location (e.g., based on the wordline position on a die, such as at the edge of the die or distant from the edge by at least one neighboring wordline).

FIG. 4 schematically illustrates an example adaptable data modulation technique, which can be employed for performing a memory write operation by a controller operating in accordance with aspects of the present disclosure. The data to be written to a memory device (e.g., host data) can include one or more original translation units (e.g., pages) 410 of a predefined size L (e.g., 4K bits). The translation unit can be represented by one or more logical level pages 420A-420D, e.g., the lower page (LP), the upper page (UP), the extra page (XP), and the top page (TP) for QLC memory.

As noted herein above, data modulation can be performed by applying a modulation operation 440 to each original translation unit 410 of the data to be written to a memory device in order to achieve desired (e.g., predefined) charge level distributions in the corresponding modulated translation unit 450.

In some implementations, each original translation unit 410 can be split into multiple original data segments 430A-430K of a predefined size W<L. Data modulation operation 440 can be performed by combining (e.g., by an exclusive disjunction (“XOR”) operation) an original segment of data 430 with a modulation mask (i.e., a sequence of bits) represented by a random vector R of the same size:

D_t=D₀XOR R

- where D_tis the transformed (modulated) segment of data and D₀is the original segment of data.

Vector R can be produced by a randomizer (e.g., a hardware-based randomizer circuit or a software-implemented randomizer module) which, once initialized by a seed value of a predefined size (e.g., 42 bits), would generate a pseudo-random vector R of a specified size. Seeding the randomizer by the same value would result in the same output sequence of pseudo-random vectors.

In some implementations, the randomizer may be seeded before generating each pseudo-random vector R for transforming a single original data segments 430A-430K. Alternatively, a seeded randomizer may be utilized for generating multiple pseudo-random vectors R for transforming multiple original data segments 430A-430K.

For each original segment of data 430A-430K, once its target location on the memory device is determined, the controller can choose a corresponding seed value, which would result in the desired memory cell charge level distribution in the corresponding modulated segment of data 460A-460K to be written to the target location of the memory device.

The seed value defining a transformation that would result in the desired charge level distribution of the modulated data can be chosen, e.g., from a predefined set of seed values. In an illustrative example, for a given segment of data, the controller can apply the above-described transformation with each seed value of the predefined set of seed values and choose the seed value that would result in the minimum, among all seed values, difference between the desired charge level distribution and the charge level distribution resulting from applying the seed value to the given segment of data.

In an illustrative example, the set of seed values can include a predefined number (e.g., N=16) of randomly generated values. The number of seed values can be chosen to allow a sufficient number of candidate modulated data variants in order to achieve the desired distribution of the data written to the target location of the memory device.

In some implementations, the set of seed values can be stored in a linear array in the metadata area of the memory sub-system. Accordingly, a given seed value can be identified by its index (position) within the stored linear array of seed values, thus allowing identifying and efficient retrieval of seed values by their respective positions within the linear array.

Referring again to FIG. 4, each original segment 430A-430K of the original translation unit 410 is transformed by operation 420 into a corresponding modulated data segment 460A-460K of the same size as the original segment 430A-430K. Each modulated data segment 460A-460K is concatenated with a corresponding identifier 470A-470K of the seed value that has been used for transforming the data segment. The modulated segments 460A-460K, each concatenated with its respective seed identifier 470A-470K, can be concatenated together to form a modulated translation unit 450, which can be further encoded before having been written to its target location of the memory device. Storing the seed identifier in association with the modulated data segment would facilitate the reverse transformation when a read operation is performed with respect to the modulated data, as described in more detail below.

The seed value stored in the memory device represents the modulation overhead. The size of the seed value is ceil(log₂(N)) bits, where ceil(x) is a function that returns the smallest integer value that is larger than or equal to x, and N is the number of seed values in the set of seed values employed by the memory sub-system for performing data modulation operations. In an illustrative example, the set of seed values includes 16 seed values, and the modulation overhead would be log₂(16)=4 bits.

While in the illustrative example of FIG. 4 seed value identifiers 470A-470K follow the corresponding modulated data segments 460A-460K, in other implementations, various other arrangements of the data items are possible, e.g., seed value identifiers 470A-470K preceding the corresponding modulated data segments 460A-460K, seed value identifiers 470A-470K grouped together and following or preceding a group of corresponding modulated data segments 460A-460K, and so on.

A read operation would involve reading, from the memory device, the modulated translation unit 450 including its constituent modulated segments 460A-460K and their respective seed identifiers 470A-470K. Each modulated segments 460A-460K can then be transformed to the corresponding original segment 430A-430K by performing the reverse modulation operation, thus restoring the original translation unit 410.

In some implementations, the reverse modulation operation can involve combining (e.g., by an exclusive disjunction (“XOR”) operation) each modulated segment of data 460A-460K with the modulation mask represented by a vector R produced by the randomizer (e.g., a hardware-based randomizer circuit or a software-implemented randomizer module) seeded by the corresponding seed value identified by the seed value identifier 470A-470K stored on the memory device in association with the modulated segment of data 460A-460K:

D₀=D_tXOR R.

FIG. 5 schematically illustrates an example method 500 of data modulation implemented by a memory controller operating in accordance with aspects of the present disclosure. The method 500 can be performed by processing logic that can include hardware (e.g., general purpose or specialized processing devices, circuitry, dedicated logic, programmable logic, microcode, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or various combinations thereof. In some implementations, method 500 can be performed by a single processing thread. Alternatively, method 500 can be performed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In an illustrative example, the processing threads implementing method 500 can be synchronized (e.g., using semaphores, critical sections, and/or other thread synchronization mechanisms). Alternatively, the processing threads implementing method 500 can be executed asynchronously with respect to each other. In some implementations, the method 500 is performed by the memory sub-system controller 115 and/or the local media controller 135 of FIG. 1. Operations of the method 500 can be specified by a sequence of command codes, which the processing logic can retrieve from a dedicated storage location. Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated implementations should be understood only as examples, and the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in various implementations. Thus, not all operations are required in every implementation.

As schematically illustrated by FIG. 5, at operation 510, the processing device implementing the method (e.g., a memory sub-system controller) receives a unit (e.g., a translation unit, such as a page) of data to be written to the memory device.

At operation 520, the processing device splits the unit of data into multiple segments of a predefined size, such that concatenation of all segments would produce the original unit of data, as described in more detail herein above.

At operation 530, the processing device transforms each segment of the unit of data by a modulation operation using a modulation mask derived from a corresponding seed value. In an illustrative example, the modulation operation involves combining (e.g., by an exclusive disjunction (“XOR”) operation) an original segment of data with the modulation mask. The modulation mask can be represented by a pseudo-random vector (i.e., a sequence of bits of a specified size), which can be derived from the seed value. The seed value defining a modulating transformation that would result in the desired charge level distribution of the modulated data can be chosen, e.g., from a predefined set of seed values. A given seed value can be identified by its index (position) within a linear array of seed values that can be stored in the metadata area of the memory sub-system, as described in more detail herein above.

At operation 540, the processing device generates a modulated unit of data, which includes the modulated segments together with the corresponding seed identifiers. Each seed identifier references a seed value that has been used for modulating a respective original segment. In an illustrative example, each modulated segment can be concatenated with the corresponding seed identifier. The modulated segments, each concatenated with its respective seed identifier, can be concatenated together to form a modulated translation unit, which can be further encoded before having been written to its target location of the memory device, as described in more detail herein above.

At operation 550, the processing device stores the modulated unit of data on a memory device, and the method terminates.

FIG. 6 schematically illustrates an example method 600 of data demodulation implemented by a memory controller operating in accordance with aspects of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., general purpose or specialized processing devices, circuitry, dedicated logic, programmable logic, microcode, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or various combinations thereof. In some implementations, method 600 can be performed by a single processing thread. Alternatively, method 600 can be performed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In an illustrative example, the processing threads implementing method 600 can be synchronized (e.g., using semaphores, critical sections, and/or other thread synchronization mechanisms). Alternatively, the processing threads implementing method 600 can be executed asynchronously with respect to each other. In some implementations, the method 600 is performed by the memory sub-system controller 116 and/or the local media controller 136 of FIG. 1. Operations of the method 600 can be specified by a sequence of command codes, which the processing logic can retrieve from a dedicated storage location. Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated implementations should be understood only as examples, and the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in various implementations. Thus, not all operations are required in every implementation.

As schematically illustrated by FIG. 6, at operation 610, the processing device implementing the method (e.g., a memory sub-system controller) reads a modulated unit (e.g., a translation unit, such as a page) of data.

At operation 620, the processing device splits the modulated unit of data into multiple modulated segments of a predefined size, such that concatenation of all segments would produce the modulated unit of data, as described in more detail herein above.

At operation 630, the processing device demodulates each modulated segment by a demodulation operation using a modulation mask derived from a corresponding seed value. In an illustrative example, the demodulation operation involves combining (e.g., by an exclusive disjunction (“XOR”) operation) the modulated segment of data with the modulation mask. The modulation mask, which can be represented by a pseudo-random vector (i.e., a sequence of bits) is derived from the corresponding seed value (e.g., by a hardware randomizer circuit or a software randomizer module). An identifier of the seed value (e.g., its index position within a linear array of seed values that can be stored in the metadata area of the memory sub-system) can be retrieved from the modulated segment, as described in more detail herein above.

At operation 640, the processing device generates a demodulated unit of data, which includes the demodulated segments concatenated together, as described in more detail herein above.

FIG. 9 illustrates an example machine of a computer system 1000 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some implementations, the computer system 1000 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform the operations of a controller (e.g., to perform operations corresponding to data modulation component 134 of FIG. 1, including method 500 of data modulation and/or method 600 of data demodulation). In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1018, which communicate with each other via a bus 1030.

Processing device 1002 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 1002 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. The computer system 1000 can further include a network interface device 1009 to communicate over the network 1020.

The data storage system 1018 can include a machine-readable storage medium 1024 (also known as a computer-readable medium, such as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein. The instructions 1026 can also reside, completely or at least partially, within the main memory 1004 and/or within the processing device 1002 during execution thereof by the computer system 1000, the main memory 1004 and the processing device 1002 also constituting machine-readable storage media. The machine-readable storage medium 1024, data storage system 1018, and/or main memory 1004 can correspond to the memory sub-system 110 of FIG. 1.

In some implementations, the instructions 1026 include instructions to implement functionality corresponding to data modulation component 134 of FIG. 1, including method 500 of data modulation and/or method 600 of data demodulation. While the machine-readable storage medium 1024 is shown in an example implementation to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

All of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some implementations, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

In the foregoing specification, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

ADAPTABLE DATA MODULATION IN MEMORY SYSTEMS

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