Patent Application
20060119430
The present invention relates generally to the field of communications, and more particularly to high-speed electronic signaling within and between integrated circuit devices.
Integrated circuits fabricated using modem deep submicron processes operate at relatively low supply voltages, but may be required to inter-operate with legacy devices that operate at relatively higher voltages. Unfortunately, the higher voltages of such legacy devices present serious reliability problems for the thin-oxide field-effect transistors (FETs) made available by advanced processes and preferred for high-speed communication. Circuits that support communication at higher voltages in support of legacy devices therefore employ high-voltage-tolerant devices, such as thick-oxide transistors, in place of higher performance devices.
Driver 103 is AC coupled to receiver 110 in the depicted example using a pair of capacitors 120 and 125, though the coupling may be direct in other embodiments. Embodiments of receiver 110 and channel 115 are well known in the art, so a detailed discussion of those devices is omitted here for brevity. Likewise, core logic 130 may be any circuitry that develops signals to be conveyed from IC 105 via channel 115, so a detailed treatment of logic 130 is also omitted. Termination voltage Vtt and supply voltage Vdd, sourced between respective power-supply terminals Vtt and Vdd and ground, are 1.8 volts and 1.0 volts, respectively, but embodiments of the invention can be used with other combinations of supply voltages.
Each of cascode amplifiers 135 and 140 includes a respective input terminal coupled to core logic 130 via lines Vn and Vp, a cascode terminal Vcas, a first current-handling terminal coupled to one of a pair of differential output nodes 145 and 150, and a second current-handling terminal coupled to ground potential via a tail transistor 155. The first current-handling terminals of cascode amplifiers 135 and 140 are coupled to termination voltage Vtt via a respective pair of termination elements (loads) 160 and 165. The bias level on cascode terminals Vcas is actively controlled by a pair of resistors 170 and 175 that apply the common-mode voltage across output nodes 145 and 150 to node Vcas, the cascode terminal of both amplifiers 135 and 140. In some embodiments a third resistor 176 may be employed to adjust the Vcas bias voltage toward a voltage reference, such as one of the power-supply nodes. In
The operation of driver 103 is similar to that of a conventional differential stage. In essence, driver 103 amplifies the difference between input signals Vn and Vp, providing the amplified result across output nodes 145 and 150. The cascode transistors in amplifiers 135 and 140 provide some voltage gain, albeit at the expense of some added output capacitance. Resistors 170 and 175 should generally be large relative to termination elements 160 and 165, 500 ohms vs. 50 ohms in one embodiment, so that their effect on termination impedance and required output current is negligible.
The widths of the input and cascode transistors can be adjusted to change the output characteristics of driver 103. Increasing the width of the cascode transistors relative to the switching transistors increases the output capacitance of driver 103, which in turn tends to reduce high-frequency performance of the driver. However, increasing the width of the cascode transistors allows the switching transistors of cascode amplifiers 135 and 140 to be drawn smaller, thereby reducing the load on core logic 130 and the power consumed by the core logic in driving signals Vp/Vn. On the other hand, decreasing the width of the cascode transistors relative to the switching transistors reduces output capacitance, improving the high-frequency performance of the driver, but at the expense of higher power consumption in core logic 130. In a typical embodiment, the cascode transistors may be drawn twice as wide as the input transistors, for example, to provide a good compromise between power consumption and high-frequency performance.
Driver 103, despite the use of voltage-sensitive transistors, is relatively insensitive to various fault conditions that might otherwise overstress the output transistors. Types of overstress typically encountered include hot-electron degradation, which may occur when transistors pass high drain current in the presence of high drain-to-bulk voltages, or dielectric breakdown, which may occur when excessive voltage is applied across the gate dielectric. The active cascode bias levels provided by resistors 170 and 175 (and resistor 176, if employed) prevent both types of overstress in a variety of fault conditions.
Fault Condition: Output Shorted to Vtt
One over-voltage condition occurs when one or both of output nodes 145 and 150 is shorted to supply voltage Vtt, as by an errant connection, when the corresponding cascode amplifier is biased on (e.g., when voltage Vn is at or near voltage Vdd). Node 145 might be shorted to supply voltage Vtt when cascode amplifier 135 is biased on, for example. In that instance, resistor 170 pulls node Vcas high enough to turn on both cascode transistors, irrespective of the voltage on node 150 (provided node 150 remains between zero and 1.8 volts). The two transistors of cascode amplifier 135 would therefore both conduct current to ground via tail transistor 155. Because the two transistors are in series, each drops a considerable portion of the voltage between respective terminal element 160 and tail transistor 155. The resistor network that includes resistors 170, 175, and optionally 176 can be optimized so that the transistors of cascode amplifiers 135 and 140 each drop about half of the voltage between respective terminal element 160 and tail transistor 155, and thus equally share the overstress to maintain the drain-to-bulk voltage of each transistor within safe limits. This sharing of the voltage drop prevents hot electron degradation. In some embodiments, the transistors in each cascode amplifier are formed in floating P-wells, which are doped regions on IC 105 that are electrically insulated from supply terminals Vtt and ground. This practice minimizes the drain-to-bulk voltage of each of the transistors in each of cascode amplifiers 135 and 140.
Fault Condition: Output Shorted to Ground
Another over-voltage condition occurs when one of output nodes 145 and 150 is shorted to the lower supply voltage (e.g., ground), as by an errant connection, when the corresponding cascode amplifier is biased on. Node 145 might be shorted to ground when cascode amplifier 135 is biased on, for example. In that instance, resistor 170 pulls node Vcas below one volt irrespective of the voltage on node 150 (again assuming node 150 remains between zero and 1.8 volts). Maintaining a low voltage on cascode terminal Vcas maintains a low enough potential across the gates of the cascode transistors to avoid dielectric breakdown.
Errant connections are not the only manner of shorting nodes 145 to voltages that, without the active cascode biasing provided by transistors 170 and 175, might damage the output transistors. At start-up, for example, capacitors 120 and 125 may be discharged before supply voltage Vtt is available. In that case, capacitors 120 and 125 may appear to driver 103 as shorts to ground for the time interval required to charge them to their final operating voltages. Other fault conditions occur, for example, when channel 115 is disconnected, or when termination supply voltage Vtt is available before core supply voltage Vdd. Driver 103 can be optimized to protect the transistors of amplifiers 135 and 140 under all such conditions.
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the output of driver 103 can be differential or single ended. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved.
An output of the design process for an integrated circuit, or a portion of an integrated circuit, may be a computer-readable medium (e.g., a magnetic tape or an optical or magnetic disk) encoded with data structures or other information defining circuitry that may be physically instantiated as an integrated circuit or portion of an integrated circuit. These data structures are commonly written in Caltech Intermediate Format (CIF) or GDSII, a proprietary binary format. Those of skill in the art of mask preparation can develop such data structures from schematic diagrams of the type detailed above.
While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example:
