Patent Application
20190041885
The present invention relates to linear voltage regulators, particularly to bulk-biased linear voltage regulators.
The demands for portable electronics, such as smart phones, bluetooth headphones and so on, are growing fast. Since most of these devices integrate many power supply-sensitive circuits onto a single integrated chip, a constant, clean and accurate supply is very necessary. Linear voltage regulators (e.g. Low Drop-Out (LDO) regulators) can provide a well-specified and stable dc-voltage. They are also widely-used in the integrated System-on-Chip (SoC) designs, which require power management circuits to optimize the power consumption of different analog, digital or Radio Frequency (RF) blocks independently. Throughout this disclosure, the terms “LDO linear voltage regulator” and “LDO” may be used interchangeably depending on the context.
The area, voltage conversion efficiency, and load transient response performance are critical properties of LDO regulators. Since most portable devices are distinguished by small sizes and low energy consumption, power management circuits like LDO regulators are required to occupy small area of the printed circuit board (PCB) or even integrated with other circuits on the same chip. On the other hand, since most mobile electronics use batteries as their only power source, the battery life time becomes one of the main concerns. The conversion efficiency of a power management circuit directly affects the battery life time. As linear regulators, LDOs, can only generate supply voltages lower than the batteries' output voltages. The voltage conversion efficiency of an LDO circuit can be calculated according to equation (1), assuming negligible quiescent current consumption by the LDO circuitry.
From the above equation, it is clear that the smaller the dropout voltage (VDO) of an LDO regulator (the difference between input voltage and output voltage of the LDO) is, the higher the voltage conversion efficiency is. However, the smaller dropout requires an area increase of the power device (pass device) of the LDO. This results in an efficiency-area tradeoff. Moreover, as the technology advances, the sizes of CMOS devices become smaller and the maximum allowed voltages for the circuits built by these devices are also becoming much lower. Thus, the expected voltage variation at the gate of the pass device is limited. This results in a limited current capability for a given device size, if controlled only by its gate voltage. In addition, the outputs of the LDO regulators are expected to be stable when the load currents change. The overshoot/undershoot of the output voltage should be as small as possible. These new application requirements on LDO regulators present great challenges for circuit designers.
Bulk bias techniques have been used in the design of LDO regulators to reduce the chip size, while maintaining the same performance as the conventional LDO regulators. Equation (2) represents a relationship between the threshold voltage (VTH) of a PMOS transistor and its bulk to source voltage (VBS) as an example of the effect of bulk voltage:
VTH=VTH0−γ(√{square root over (|2ϕF|+VBS)}−√{square root over (|2ϕF|)}) (2),
where VTH0 represents the threshold voltage with VBS=0, and γ and ϕF are technology-dependent parameters for a p-channel transistor.
As shown in Equation (2), a forward bulk bias voltage (Positive VBS) will lower the threshold voltage (VTH) of the pass device in the LDO regulator. In an example disclosed by Y. S. Koo (“A design of low-area low drop-out regulator using body bias technique,” IEICE Electronics Express 10, No. 19 (2013): 20130300-20130300), a forward bulk bias is used to lower the VTH and reduce the transistor size within a certain current range. The bulk of the pass transistor of this LDO regulator is adaptively-biased with the input supply (its voltage is a constant shift of the input supply voltage), but it is constant with the load current. In an example disclosed by H. E. Cho and Y. S. Koo (“A Design of Wide-Bandwidth LDO Regulator with High Robustness ESD Protection Circuit.” Journal of Power Electronics 15, no. 6 (2015): 1673-1681), the LDO regulator also employs a forward bulk-biased voltage to lower the VTH, but it also uses a constant bias voltage.
Although, achieving a silicon area improvement for the same current capability, the above improvements did not address the following:
Embodiments of the invention relate to voltage regulators that use adaptive bulk-bias techniques to improve their PSR, load regulation, and load transient performance on top of the output current capability. The adaptive bulk-bias techniques can overcome the problems related to the prior art techniques mentioned above.
PSR, load transient response, and maximum output current are important performance parameters of an LDO regulator. Prior improvement methods usually focused on one of these factors. The adaptive bulk-bias technique disclosed in the present invention is capable of improving multiple or all these parameters of an LDO regulator.
First, the adaptive bulk-bias technique lowers the threshold (Vth) of the pass transistor of an LDO regulator, resulting in increased output current capability without making other changes to the LDO regulator. Second, in a fast load transition process, the output voltage of the error amplifier of an LDO regulator does not need to change too much due to a lowered threshold of the pass transistor. As a result, the load transient response of the LDO is improved. Third, the adaptive bulk-biased technique increases the output impedance (Rout) of the LDO regulator when the load is high, which improves its PSR in the high load situation. Finally, a combination adaptive bulk-bias scheme can further improve the load transient performance of an LDO regulator. A combination adaptive bulk-bias scheme combines both a fast and a slow bias signal paths to compensate for output spikes caused by the fast load transition.
One aspect of the invention relates to ow-dropout (LDO) voltage regulators. An LDO regulator in accordance with one embodiment of the invention includes an adaptive bias source for generating a bulk-bias signal to a pass device in the LDO voltage regulator, wherein the adaptive bias source generates the bulk-bias signal based on a signal obtained at an output of the LDO voltage regulator.
In accordance with embodiments of the invention, the signal may include a current signal, which is proportional to a current at the output of the LDO voltage regulator, and/or a feedback signal from a feedback path connected between the adaptive bias source and the output of the LDO voltage regulator for sensing negative and/or positive spikes.
One aspect of the invention relates to methods for voltage regulation using a low dropout (LDO) voltage regulator that comprises an adaptive bias source connected to a pass device. A method in accordance with one embodiment of the invention comprises: sensing a signal at an output of the LDO voltage regulator; generating a bulk-bias signal from the adaptive bias source based on a magnitude of the signal sensed at the output; and supplying the bulk-bias signal to the pass device to regulate the voltage at the output of the LDO voltage regulator.
In accordance with embodiments of the invention, the signal may comprise a current signal, which is proportional to a current at the output, and/or a feedback signal that relates to negative and/or positive spikes at the output.
Other aspects of the invention will be apparent from the following detailed description and the appended claims.
Embodiments of the present invention are illustrated with the above-identified drawings and the following description. In the description, like or identical reference numerals are used to identify common or similar elements. The drawings are not necessarily to scale and certain features may be shown exaggerated in scale or in schematic in the interest of clarity and conciseness.
Embodiments of the invention relate to an inventive method to improve the power supply rejection (PSR), load regulation, and load transient performance of voltage regulators by adding a load-adaptive bulk-bias to the pass devices of voltage regulators.
Because a strong forward bulk-bias voltage can lead to a high leakage current through the p-n junction diode in the pass devices (p-channel or n-channel MOSFETs), the value of this bulk-bias voltage is limited to a certain value in order to prevent this high leakage current. Simulation and experiments can be performed to obtain this maximum bulk-bias limit for devices of different technologies.
When the output current of an LDO regulator is moderate or high, the pass device works in the saturation or linear region of MOS transistor. Its drain current (ID), the gate to source voltage (VGS), and drain to source voltage (VDS) are related by equations (3) and (4).
where μn is the charge-carrier effective mobility, W is the gate width, L is the gate length, Cox is the gate oxide capacitance per unit area, λ is the channel-length modulation parameter, ID is the drain current of the device, VGS is the gate-to-source voltage, Vth is the threshold voltage of the device, VGS is the drain-to-source voltage and VDSsat is the saturation voltage, which equals VGS-Vth.
Adding a bulk-bias voltage to the pass device, Vth will decrease as mentioned in the background section. No matter whether the pass device works in the linear region or in the saturation region, a drop in Vth will increase ID, which is also the output current of the LDO regulator, while other parameters like area (W and L) and VGS maintain their original values. Another benefit is that VDSsat (VDS in the saturation region) also decreases due to the reduction of Vth. Thus, the dropout of the LDO regulator can be smaller than that of the LDO regulator without bulk-bias. For many applications in which external supply voltage is very close to the output voltage of the LDO regulators (small headroom), this improvement is very helpful.
In accordance with embodiments of the invention, one or more of the modules and elements shown in the example of
As noted above, using a bulk bias helps the gate voltage to increase the pass device current capability. At the same time, it reduces the required gate voltage at low output current value. This results in an increase in the dynamic range of the gate voltage, which may add more requirements on the error amplifier design.
Power supply rejection (PSR) of an LDO regulator can be improved by adding bulk-bias to the pass device.
where gm is the transconductance of the pass device, Rout is the output impedance of the LDO, R1 and R2 are the resistors of the potential divider of the LDO.
It can be seen as VTH is lowered by adding a bulk-bias voltage, the gain of the pass device will increase, which improves the PSR of the LDO regulator at low frequency.
However, bulk bias technique degrades the PSR performance of a voltage regulator at low output current values.
In accordance with embodiments of the invention, using an adaptive bulk-bias technique injects a zero bulk bias voltage at low output currents, while injecting a higher bulk bias voltage at high output currents, thereby achieving optimum PSR across all output current variations.
The load transient response of an LDO regulator can also be improved by adding a forward adaptive bulk-bias to the pass device. When the load current changes, voltage overshoots and undershoots are usually produced on the output of an LDO regulator. The amplitudes of the overshoots and undershoots are affected by the VGS voltage difference of the pass device before and after the load current changes. If the difference is small, then when other parameters are the same, the overshoots and undershoots will be small.
Another way to improve the load transient performance is to add a transient adaptive bulk-bias signal through a fast feedback path (e.g. faster than 1 μs) from the output of the regulator.
The circuits described above are implementation examples. Same methods and/or ideas may be applied to voltage regulators (switching and linear) using different pass devices (such as PMOS, NMOS, PFET, NFET, PFIN, and NFIN, wherein P and N denotes p-type and n-type, MOS refers to metal-oxide-semiconductor, FET refers to field-effect transistor, and FIN refers to fin field-effect transistor).
In accordance with embodiments of the invention, one or more of the modules and elements shown in the example of
As noted above,
The circuit shown in
In accordance with embodiments of the invention, one or more of the modules and elements shown in the example of
Advantages of embodiments of the invention may include one or more of the following: Embodiments of the invention, by applying adaptive bulk-bias technique to the pass device (or power device) of a voltage regulator that changes its voltage value with the regulator output current. In addition, implementation of a fast transient path that changes the bulk-bias of the pass device (or power device) instantaneously as a result of an instantaneous change in the output current and output voltage of the regulator. Moreover, a combination of both techniques is presented.
Embodiments of the invention have been illustrated with a limited number of examples. One skilled in the art would appreciate that other variations and modifications are possible without departing from the scope of the invention. Therefore, the scope of protection of this invention should only be limited by the appended claims.
