ADAPTIVE CLOCK SIGNAL MANAGEMENT

Abstract

Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.

Description

Claims

1. A clock subsystem, comprising: an oscillator configured to provide a clock signal at either a first frequency or a second frequency; anda controller coupled to the oscillator and configured to: determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input; andprovide a signal to the oscillator to produce the clock signal at the desired frequency.

2. The clock subsystem of claim 1, wherein the controller is further configured to provide an indication of the clock signal to an analog-to-digital converter.

3. The clock subsystem of claim 2, wherein the oscillator is configured to provide the clock signal at the desired frequency to the analog-to-digital converter.

4. The clock subsystem of claim 3, wherein, in response to determining that the clock signal is at the desired frequency based on the indication, the analog-to-digital converter is configured to convert an analog signal using the clock signal.

5. The clock subsystem of claim 1, wherein the power mode input is in one among a regular-power mode state and a low-power mode state.

6. The clock subsystem of claim 5, wherein the multiple inputs further comprises a logic input comprising multiple states, and wherein at least one state of the multiple states influences the desired frequency when the power mode input is in the regular-power mode state and at least one other state of the multiple states influences the desired frequency when the power mode input is in the low-power mode state.

7. The clock subsystem of claim 1, wherein the analog-to-digital converter input is in one among a convert state and a rest state, and wherein the analog-to-digital converter input enters the convert state when the controller of the clock subsystem receives a request to produce the clock signal for an analog-to-digital converter.

8. A system, comprising: an analog-to-digital converter (ADC) subsystem; anda clock subsystem coupled to the ADC subsystem and configured to provide a clock signal;wherein the ADC subsystem is configured to, in response to a trigger to convert an analog signal to a digital signal, request the clock subsystem to produce the clock signal at a desired frequency; andwherein the clock subsystem is configured to: determine the desired frequency based on the request from the ADC subsystem;produce, via an oscillator unit of the clock subsystem, the clock signal at the desired frequency; andprovide the clock signal to the ADC subsystem.

9. The system of claim 8, wherein the clock subsystem comprises the oscillator unit configured to provide the clock signal at either a first frequency or a second frequency and a clock controller coupled to the oscillator unit and configured to control the oscillator unit.

10. The system of claim 8, wherein the ADC subsystem comprises circuitry configured to convert analog signals to digital signals based on the clock signal and an ADC controller coupled to the circuitry and configured to instruct the circuitry to convert the analog signal to the digital signal.

11. The system of claim 10, wherein the circuitry of the ADC subsystem is further configured to provide the digital signal to one among the peripheral or a further peripheral.

12. The system of claim 8, wherein the desired frequency corresponds to a sampling rate capable of converting the analog signal to the digital signal.

13. The system of claim 8, wherein the desired frequency is further based on a state of each input of multiple inputs to the clock subsystem, and wherein the multiple inputs comprise a power mode input and a logic input.

14. The system of claim 13, wherein the power mode input is in one among a regular-power mode state and a low-power mode state, and wherein the logic input is in one among multiple frequency states, and wherein at least one frequency state of the multiple frequency states influences the desired frequency when the power mode input is in the regular-power mode state and at least one other frequency state of the multiple frequency states influences the desired frequency when the power mode Input is in the low-power mode state.

15. A method, comprising: in an analog-to-digital converter, in response to a trigger to convert an analog signal to a digital signal, requesting a clock subsystem to produce a clock signal at a desired frequency;in the clock subsystem, producing the clock signal at the desired frequency based on the request and providing an indication of the clock signal to the analog-to-digital converter; andin the analog-to-digital converter, in response to determining that the clock signal is at the desired frequency based on the indication, instructing circuitry to convert the analog signal to the digital signal.

16. The method of claim 15, further comprising, in the clock subsystem, providing the clock signal at the desired frequency to the circuitry.

17. The method of claim 15, wherein the clock subsystem comprises an oscillator configured to provide the clock signal at the desired frequency, and a clock controller coupled to the oscillator and configured to control the oscillator.

18. The method of claim 15, wherein producing the clock signal at the desired frequency is further based on a state of each input of multiple inputs to the clock subsystem, and wherein the multiple inputs comprise a power mode input and a logic input.

19. The method of claim 18, wherein the power mode input is in one among a regular-power mode state and a low-power mode state.

20. The method of claim 19, wherein the logic input is in one among multiple frequency states, and wherein at least one frequency state of the multiple frequency states influences the desired frequency when the power mode input is in the regular-power mode state and at least one other frequency state of the multiple frequency states influences the desired frequency when the power mode input is in the low-power mode state.