Patent Application
20240223354
The present disclosure is directed in general to a system and method for processing cryptographic data in electronic devices and, specifically, to a system and method for providing improved side channel protection in devices implementing lattice-based cryptography schemes.
Digital cryptography schemes play an important role in the world's data communication infrastructure. Such schemes underpin important authentication and transaction validation infrastructures in the form of digital certificates to secure digital transactions occurring on the Internet or across other communication networks. Often, such authentication and validation systems are implemented by devices participating in Internet of Things (IOT) networks or other types of sensors, actuators, and appliances, to transmit and receive data and to validate the authenticity of received instructions and commands.
To provide robust authentication and validation schemes in the face of new technology, recent significant advances in quantum computing have accelerated the research into postquantum cryptography schemes: cryptographic algorithms that run on classical computers but are still secure even when faced with an adversary with access to quantum computing resources. This demand is driven by interest from standardization bodies. This research involves evaluating potential lattice-based cryptography schemes as potential replacements for elliptic curve cryptography digital signatures (e.g., ECDSA), notably for embedded use cases. Similar to their elliptic-curve-cryptography-based counterparts, however, such lattice-based cryptography schemes can be targeted by algebraic side-channel attacks exploiting the leakage of a single bit of the random secret value.
A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter of the application and uses of such embodiments. As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation or embodiment described herein as exemplary, or an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
The signing operation of a digital signature scheme generates a cryptographic signature value for a given message using a secret cryptographic key. If, while implementing the digital signature scheme, the value of the secret key is leaked or otherwise made accessible to third parties, that potential for third party knowledge of the secret key would invalidate the security properties provided by that digital signature scheme.
Some proposed post-quantum computing digital signature schemes have been shown to leak portions of the scheme's secret signing keys and/or the schemes secret masking vectors that are used to obfuscate the scheme's secret signing keys during signature processing via side-channel leakage. Side-channel leakage attacks may involve an attacker observing power consumption or electro-magnetic emissions of particular communication pins of various components of the device to detect voltage fluctuations enabling the attacker to extract data bits that are indicative of private key or secret masking values being processed by the device using side-channel analysis. Devices such as IoT devices, where the attacker has physical access to the device, may be particularly susceptible to these types of attacks as an attacker is free to access the internal components of the device. Additionally, attackers may be able to modify the operating conditions of the device, or otherwise alter components of the device, so that the data indicative of the device's private keys and secret masking values may be accessed.
In some such attacks, it may not be necessary for an attacker to know all the bits of a private key in order to break the digital signature scheme. For example, partial key or secret masking vector exposure attacks can allow an attacker to recover an entire private key from only a partial knowledge of the key's or secret masking value's bits. For example, in a similar manner to their elliptic-curve-cryptography-based counterparts, lattice-based cryptography schemes can be attacked using algebraic side-channel attacks that exploit the leakage of a single bit of the scheme secret masking vector's value. Here, the secret masking vector refers to a random and non-repeating value that is utilized by a digital signature scheme to protect the scheme's private keys each time a particular private key is used to sign a data input.
In some such lattice-based cryptography schemes, the index of the targeted bit in the masking vector can affect the effectiveness of such an attack. For example, it has been shown that the secret signing key s1 employed by the DILITHIUM digital signature scheme can be recovered by extracting only a single bit of the masking vector y's coefficients from side-channel leakage that occurs over a number of signature generations. In this attack, the index of that single bit can affect how difficult it is to determine the value of the secret key. In the DILITHIUM scheme, knowledge of the value of the 8th bit of the masking vector is the most useful for an attacker and requires an achievable minimum number of signatures (e.g., about 3000 signatures) in order for an attacker to retrieve the value of the scheme's private key. For each bit index increment (e.g., for the ninth bit of the secret masking vector value and so on), the number of required signatures for a successful attack and recovery of the private key increases dramatically.
In general, when applying these types of attacks to the DILITHIUM digital signature, the bits targeted in the side-channel attack tend to be the 8th to about the 19th bit of the secret masking value vector y. However, the bit values at different bit indexes in the secret masking vector y do not provide the same degree of usefulness to an attacker when attempting to recover a corresponding secret key s1. For example, knowledge of the 8th bit of the secret masking vector y enables the secret key s1 to be recovered with only about 3,000 signatures, four times as many signatures are required to recover the secret key s1 if only the 9th bit of the secret masking vector y is known, and so on. If only the 19th bit of the secret masking vector y is known, for example, 239 signature values are required.
In evaluating the security of a particular digital signature scheme, that security is evaluated based on the weakest link in the chain, which in this specific case is the 8th bit of the scheme secret masking vector y. Standard masking techniques will generally protect all bits equally of a value, meaning that the same cost (e.g., in terms of computing power) is spent on protecting all bits each time the value is used, despite not all of those bits requiring the same level of protection.
Consequently, the present disclosure provides an adaptive bit masking technique that improves (i.e., reduces) the cost of protecting the secret masking vector y in a digital signature scheme, such as DILITHIUM, by enabling more efficient masking of the secret masking vector's y's bit values. In an embodiment, this improvement may be achieved by taking into account the weakness of the individual bit indexes of the secret masking vector y (i.e., with the 8th bit being the weakest in the DILITHIUM scheme) and applying appropriate levels of protection (i.e., bit masking) across the bits of the secret nonce y to reduce the amount of randomness needed and thereby improve the robustness of the digital signature scheme's implementation.
In this disclosure, various embodiments of the present approach for improving bit protection against side-channel attacks are presented with respect to the DILITHIUM digital signature scheme, however, it should be understood that the present approach may be utilized to provide more efficient bit masking for any communication protocols to provide improved security. As such, the generalized version of this approach can be applied to other digital signature schemes (and encryption schemes in general) that may be vulnerable to bit leakage attacks, such as qTESLA or other schemes that utilize Fiat-Shamir with aborts signatures or comprise lattice-based signature schemes.
The present approach can be tailored to provide an adequate (and quantifiable) amount of improved security against bit leakage attacks without expending computing resources on protecting or masking bits that are of minimum use to an attacker. That can be useful in devices with limited computing resources (e.g., IoT devices or other devices with constrained memory and processing resources) where algorithmic efficiency is an important aspect when designing a bit masking algorithm. Important metrics for these types of bit masking implementations can include the number of operations required to implement the algorithm and the number of fresh random elements required for the masking scheme.
In the present approach, adaptive masking enables the most vulnerable bits of the target value to be protected, as such, the more susceptible a bit index is to an attack, the more that bit index is protected. As such, unnecessary computing time and random value generation requirements are minimized when protecting (i.e., masking) less vulnerable bits.
When signing a message using the DILITHIUM digital signature scheme or other similar cryptographic signature schemes, the signature algorithm relies upon a secret masking vector y when generating an output signature. To protect the secret masking vector y value, during processing the masking vector y is mathematically decomposed into a number of shares yi to reduce the likelihood that the entire value y can be retrieved by an attacker. Decomposition involves converting a secret value (i.e., y) into a plurality of other values that, taken individually provide no information about the secret value, but can be utilized as a whole to perform mathematical operations (e.g., cryptographic operations) that are equivalent to using the secret value to perform the operation. In this manner, the secret value itself is not utilized when performing the cryptographic operation. As such, the shares yi can then be used iteratively to accurately calculate a digital signature without exposing the true value of the secret masking vector y.
When generating the individual adaptive shares yi of the original vector y, the present disclosure provides an approach for generating different numbers of adaptive shares for different bit indexes in y, where the number of adaptive shares for each bit index are adjusted to provide different levels of protection to the different bit indexes of the value y (where the bits have different levels of vulnerability) to provide improved protection against side channel attacks.
In describing the present bit masking system, the following variables and/or functions are defined:
q: Modulus—a value that may be a prime number or a power of 2 that species the ranges of values that are used by the algorithm.
y: one arbitrary coefficient of y.
d: The number of standard masking shares.
d′: The number of adaptive masking shares.
d″: The total number of masking shares, which is equivalent to the sum of d+d′+1.
xi: ith bit of variable x.
xj: jth share of variable x.
x←S: x is randomly and uniformly picked from the set S.
I: A list that identifies the indexes of the bits of the value y that are to be hardened using adaptive shares.
Δ(i): A list that identifies for each bit index that is being protected (as specified by the list I), the number of adaptive shares that will be used to additionally harden the protection of the ith bit in the value y.
Max(S): The function computing the maximum value in a set S.
With these variables and/or functions established, the present approach for adaptive bit masking utilizes a combination of standard masking with specifically constructed shares to adaptively protect different bits of the sensitive value y. To this end, the approach generates d standard shares, and then generates d′ specifically crafted shares to harden specific bits at specific indexes.
With the d′ and d′ values determined, at line 3 the algorithm enters a loop that iterates through values of j from 0 to d−1 where, for each value of j, a random standard share is generated according to the expression g←{0, 1, . . . , q−1}, where yj represents the set of random standard shares. As such, the loop formed by lines 3, 4, and 5 in the algorithm of
In line 6, the algorithm initializes to zero values a set of additional adaptive shares according to the expression ∀d≤j<d″, yj=0. As such, at the completion of line 6 a number of adaptive shares yj equal to d′ (also equal to d″ minus d minus 1 based on line 2) have been initiated. In the algorithm, the initiation of a share involves setting the share value equal to 0.
Line 7 of the algorithm creates a loop in which the value i iterates through the values of each bit index that has been designated for hardening in the list I. For each bit to be hardened, line 8 creates a sub-loop in which the value j is iterated from 0 through the corresponding number of adaptive shares Δ(i) for the bit index designated by the variable i. In line 9, for each adaptive share a value r is generated as a random bit having a value of 0 or 1 and in line 10 the value equal to r*2i is added to the adaptive share yj+d to mask the bit at index i (the multiplication by the value 2i causes the bit value r to be added to the adaptive share at the bit index i).
At line 13, after the adaptive shares have been generated for each bit designated in/for hardening, a final share value yd″−1 is calculated as the original value y minus the sum of all shares y0 through yd″−2 modulus q. Specifically, line 13 of the algorithm corresponds to the computation of an additional last share value yd″−1 that allows for the reconstruction of the value y such that the sum of all of its shares are equal to its value. Otherwise, without this last share, we would be performing the following computations on the shares of a random value instead of y. The modulus operation in line 13 is dictated by the DILITHIUM signature scheme because later steps in the algorithm are performed modulus q and expect inputs modulus q.
At line 14 the method ends by returning the values of all shares y0 through yd″−1, which can then be utilized to execute a cryptographic operation, such as signing an input data set or a message or other form of data.
With the values returned in step 14, conventional techniques may be utilized to compute signature values using the shares of y. Such operations that utilize the shares of y are masked, for which algorithms are either straightforward, known or described in the literature or prior art. As such, existing signature scheme implementations may use the adaptive shares generated in accordance with this disclosure (and the algorithm of
In conventional bit masking approaches, bit masking with d′ shares requires (d+d′)┌log2(q)┐ bits of randomness because each bit being masked is protected by the same number of shares. In contrast, the approach illustrated in
An example of the present bit masking approach and its corresponding benefits are now presented with specific reference to the DILITHIUM digital signature scheme. It should be understood, however, that embodiments of the present bit masking approach may be utilized in conjunction with other types of digital signature schemes that are vulnerable to bit leakage attacks during a data signing process.
In the present example, the following values for auxiliary variables and functions are utilized.
q: prime modulus. It is equal to q=223−213+1.
n: number of polynomial coefficients, which is set to 256.
l: number of polynomials in the vector y. In this example l is equal to 4, 5 and 7 for National Institute of Standards and Technology (NIST) security levels 2, 3 and 5, respectively.
In embodiments of the DILITHIUM digital signature scheme, the 8th bit of the secret value y, if known to an attacker, renders the signature scheme most vulnerable to an attacker. Bits with greater indexes are increasingly less vulnerable to an attacker. As such, bits with greater indexes do not require the same level of protection as implemented by varying number of shares being assigned to the respective bits. Consequently, by selecting particular parameters to be utilized by the present bit masking approach, where the parameters specify which bits of the value y require adaptive masking, it is possible to implement a desired level of side-channel security and protection for the signature scheme. Generally, as the side-channel security level of the scheme increases, the computing cost of implementing the scheme increases, so it can be possible to establish a set of parameters for the invention that achieves a desired level of side-channel security, while requiring minimal computing resource requirements (e.g., memory and processing power) enabling the scheme to be implemented by resource-constrained devices, such as IoT devices.
In specific examples, as detailed below, parameters may be selected to achieve desired levels of security for the DILITHIUM digital signature scheme to protect against an attacker in possession of, for example, 220. 240 and 270 signatures. In these specific examples, low order bits are not masked (hence d=0), while bits that can be exploited for bit leakage attacks (i.e., bits of the secret masking vector y with indexes of 7 (equating to the 8th bit) or greater are protected with adaptive shares in accordance with the algorithm depicted in
In a first example, to provide adequate protection in the event that an attacker has access to 220 signatures, the following parameters may be established: I2
In a second example, to provide adequate protection in the event that an attacker has access to 240 signatures, the following parameters may be established: I2
In a third example, to provide adequate protection in the event that an attacker has access to 270 signatures, the following parameters may be established: I2
Specifically,
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Data processing system 620 may be a system-on-a-chip (SoC) implemented on a single integrated circuit, or it may be a combination of chips. In other embodiments, data processing system 620 may be implemented within an integrated circuit that may include another type of circuit such as an ASIC (application specific integrated circuit), FPGA (field programmable gate array), or the like, that can provide execute instructions. In one embodiment, data processing system 620 may include metal-oxide semiconductor (MOS) transistors fabricated using a conventional complementary metal-oxide semiconductor (CMOS) process. In another embodiment, data processing system 620 may include other transistor types, such as bipolar, and may be manufactured with a different process.
Data processing system 620 includes communication bus 622, processor(s) 624, memory 626, and cryptography co-processor 632. Bus 622 may be a conventional bus having a plurality of conductors for communicating address, data, and control information. In other embodiments, bus 622 may be an interconnect structure such as for example, a crossbar switch or other form of interconnect system. Processor(s) 624 is bi-directionally connected to bus 622. Processor(s) 624 may include one or more of any type of processing element, a processor core, microprocessor, microcontroller, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), digital signal processor, and the like. There can be any number of processors.
Memory 626 is bi-directionally connected to bus 622. Memory 626 can be one or more of any type of volatile or non-volatile memory and is generally non-transitory. Examples of memory types include non-volatile memories such as flash, one-time programmable (OTP), EEPROM (electrically eraseable programmable read only memory), and the like. Volatile memory types include static random-access memory (SRAM) and dynamic random-access memory (DRAM). The memory may be used for storing instructions and/or data.
In various embodiment, memory 626 may store data values and structure utilized when processor 624 implements the present adaptive bit masking approach. Such values stored by memory 626 may include the values y, q, d, I, and {∀iϵI,Δ(i)}, and others, which are described in detail above.
An optional user interface 628 can be bi-directionally connected to bus 622 and may be connected to one or more devices for enabling communication with a user such as an administrator. For example, user interface 628 may be enabled for coupling to a display, a mouse, a keyboard, or other input/output device. User interface 628 may also include a network interface having one or more devices for enabling communication with other hardware devices external to data processing system 620.
Instruction memory 630 may include one or more non-transitory machine-readable storage media for storing instructions for execution by processor(s) 624. In other embodiments, both memories 626 and 630 may store data upon which processor(s) 624 may operate. Memories 626 and 630 may also store, for example, instructions that, when executed by processor 624 (e.g., in combination with co-processor 632), causes processor(s) 624 to execute cryptographic functions for implementing a digital signature scheme, performing encryption and/or decryption, and/or performing data verification and validation applications. Memories 626 and 630 may be implemented in a secure hardware element and may be tamper resistant.
Co-processor 632 is bi-directionally connected to bus 622. Co-processor 632 may be a special type of a co-processor optimized for running post-quantum encryption/decryption security software configured to implement one or more digital signature schemes that may include lattice based signature schemes such as DILITHIUM and qTESLA. Accordingly, and in accordance with the described embodiments, co-processor 632 may be used to generate adaptive shares to provide improved security to secret bit masking values y utilized during execution of a digital signature scheme, as discussed above and illustrated in the algorithm of
Network communication interface 634 is bi-directionally connected to bus 622 and is configured to transmit and receive data via a suitable communications network. In various embodiments, communications interface 634 may include a wired or wireless network adapter configured to communicate over a wired or wireless connection with a local area network. In other embodiments, communications interface 634 may be configured to communicate over a wide area network, such as a cellular network (e.g., LTE, 4G, 5G, etc.). Communications interface 634 is configured to transmit and receive data, such as cryptographic signatures, such as those described herein, to remove computing system that may, in turn, elect to validate and or otherwise utilize the cryptographic signatures. In various embodiments, for example, data processing system 620 may be configured to calculate a message signature for a data packet generated by processor(s) 624 of data processing system 620. In that case, both the signature and the data packet may be transmitted to a remote computer system that may, in turn, use the cryptographic signature to confirm the authenticity of the received data packet.
As used herein, the term “non-transitory machine-readable storage medium” will be understood to exclude a transitory propagation signal but to include all forms of volatile and non-volatile memory. When software is implemented on a processor, the combination of software and processor becomes a single specific machine. Although the various embodiments have been described in detail, it should be understood that the invention is capable of other embodiments and its details are capable of modifications in various obvious respects.
In some aspects, the techniques described herein relate to a device, including: a computer-readable memory; and an integrated circuit (IC) including a processor configured to implement a lattice-based digital signature scheme, wherein the lattice-based digital signature scheme enables computation of a digital signature of an input data value using a secret bit masking vector y and wherein different bits in the secret bit masking vector y have different levels of vulnerability to a side channel leakage attack conducted using a communication pin of the integrated circuit, the processor being configured to: access the computer-readable memory to determine a first number of shares, decompose the secret bit masking vector y into a first set of share values, wherein a number of share values in the first set of share values is equal to the first number of shares, access the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the secret bit masking vector y, for each bit index in the set of bit indexes, calculate an adaptive share value in which the bit value associated with the bit index is masked, and generate a cryptographic signature value associated with the input data value using each of the first set of share values and the adaptive share value.
In some aspects, the techniques described herein relate to a device, including: a computer-readable memory; and an integrated circuit including a processor configured to implement a cryptographic operation, wherein the cryptographic operation enables computation of a cryptographic result using a bit masking value y, the processor being configured to: access the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the bit masking value y, for each bit index in the set of bit indexes, calculate an adaptive share value in which the bit value associated with the bit index is masked, and execute a cryptographic operation using the adaptive share value.
In some aspects, the techniques described herein relate to a method operating a device to implement a lattice-based digital signature scheme, wherein the lattice-based digital signature scheme enables computation of a digital signature of an input data value using a bit masking value y and wherein different bits in the bit masking value y have different levels of vulnerability to a side channel leakage attack conducted using a communication pin of an integrated circuit, the method including: accessing a computer-readable memory to determine a first number of shares; decomposing the bit masking value y into a first set of share values, wherein a number of share values in the first set of share values is equal to the first number of shares; accessing the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the bit masking value y; for each bit index in the set of bit indexes, calculating an adaptive share value in which the bit value associated with the bit index is masked; and generating a digital signature value associated with the input data value using each of the first set of share values and the adaptive share value.
Although the examples have been described with reference to automotive radar systems, the systems and methods described herein may be implemented in conjunction with other types of radar systems. Devices or components described as being separate may be integrated in a single physical device. Also, the units and circuits may be suitably combined in one or more semiconductor devices. That is, the devices described herein may be implemented as a single integrated circuit, or as multiple integrated circuits.
The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments.
As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.
The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.
As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).
The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
