Patent Application
20080192378
Embodiments of the present invention relate generally to memory storage devices; and, more particularly, embodiments of the present invention relate to noise components within a magnetic recording channel.
As is known, many varieties of memory storage devices (e.g. disk drives), such as magnetic disk drives are used to provide data storage for a host device, either directly, or through a network such as a storage area network (SAN) or network attached storage (NAS). Typical host devices include stand alone computer systems such as a desktop or laptop computer, enterprise storage devices such as servers, storage arrays such as a redundant array of independent disks (RAID) arrays, storage routers, storage switches and storage directors, and other consumer devices such as video game systems and digital video recorders. These devices provide high storage capacity in a cost effective manner.
The structure and operation of hard disk drives is generally known. Hard disk drives include, generally, a case, a hard disk having magnetically alterable properties, and a read/write mechanism including Read/Write (RW) heads operable to write data to the hard disk by locally alerting the magnetic properties of the hard disk and to read data from the hard disk by reading local magnetic properties of the hard disk. The hard disk may include multiple platters, each platter being a planar disk.
All information stored on the hard disk is recorded in tracks, which are concentric circles organized on the surface of the platters. Data stored on the disks may be accessed by moving RW heads radially as driven by a head actuator to the radial location of the track containing the data. To efficiently and quickly access this data, fine control of RW hard positioning is required. The track-based organization of data on the hard disk(s) allows for easy access to any part of the disk, which is why hard disk drives are called “random access” storage devices.
Since each track typically holds many thousands of bytes of data, the tracks are further divided into smaller units called sectors. This reduces the amount of space wasted by small files. Each sector holds 512 bytes of user data, plus as many as a few dozen additional bytes used for internal drive control and for error detection and correction.
With increases in data density stored to the hard disk, the effects of noise components within the channel are increased.
Embodiments of the present invention are directed to systems and methods that are further described in the following description and claims. Advantages and features of embodiments of the present invention may become apparent from the description, accompanying drawings and claims.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like features and wherein:
Embodiments of the present invention are illustrated in the FIGS., like numerals being used to refer to like and corresponding parts of the various drawings.
Embodiments of the present invention provide a system and method to support Viterbi branch metric calculations that support magnetic read channel operations. In magnetic recording channel, noise components in readback signals are correlated and user pattern dependent due to media noise, front-end equalizer and nonlinearity factors. In order to optimize the performance of sequence detector, data-dependent noise predictive (DDNP) filters (or called whiteners) and data-dependent bias compensation terms are used in Viterbi branch metric calculation. DDNP settings (including whiteners and biases) are obtained using on-the-fly DDNP adaptation. On-the-fly adaptation provides a ‘self-contained’ feature that allows one to ‘automatically’ acquire DDNP settings through internal channel circuits.
On-the-fly DDNP adaptation will be supported in three scenarios: self-scan mode during manufacturing, pre-read mode when a drive is seeking for particular sector to read and normal read mode. In self-scan mode during manufacturing, DDNP will be calibrated for every zone and the calibrated settings will be stored in zone tables, and later loaded to channel registers so that in read mode users can start with very good initial settings. Known NRZ data pattern, such as a pseudo-random sequence generated by a linear feedback shift register (LFSR), will be used in self-scan calibration. It is desired to do a speedy zone calibration, say on the order of one revolution. For 1″ drives, there are around 50˜100 4 k-byte sectors from ID to OD on a track.
DDNP adaptation is also desired to continuously track any environment changes when HDDs are shipped out of factories, such as in pre-read mode and normal read mode. Since in read mode, NRZ estimates rather than known data patterns will be applied in adaptation, slow loop would work better by dialing in small loop updating gain.
Disk drive unit 100 further includes one or more read/write (RW) heads 104 that are coupled to arm 106 that is moved by actuator 108 over the surface of the disk 102 either by translation, rotation or both. The head assembly may also be referred to as a head gimbal assembly (HGA) that positions a RW head, which in some embodiments may be a thin-film magnetic head, to record and read magnetic information into and from a recording surface of a hard disk or recording medium rotating at high speed. Pre-amplifier (within the RW head or located between the RW head and the disk controller) may be used to condition the signals to and from the RW head. Disk controller 130 is included for controlling the read and write operations to and from the drive, for controlling the speed of the servo motor and the motion of actuator 108, and for providing an interface to and from the host device.
Disk controller 130 further includes a processing module 132 and memory module 134. Processing module 132 can be implemented using one or more microprocessors, micro-controllers, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or any devices that manipulates signal (analog and/or digital) based on operational instructions that are stored in memory module 134. When processing module 132 is implemented with two or more devices, each device can perform the same steps, processes or functions in order to provide fault tolerance or redundancy. Alternatively, the function, steps and processes performed by processing module 132 can be split between different devices to provide greater computational speed and/or efficiency.
Memory module 134 may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache memory, and/or any device that stores digital information. Note that when the processing module 132 implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory module 134 storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Further note that, the memory module 134 stores, and the processing module 132 executes, operational instructions that can correspond to one or more of the steps or a process, method and/or function illustrated herein.
Disk controller 130 includes a plurality of modules, in particular, device controllers 105, processing module 132, memory module 134, read/write channel 140, disk formatter 125, and servo formatter 120 that are interconnected via bus 136 and bus 137. The host interface 150 can be connected to only the bus 137 and communicates with the host device 50. Each of these modules can be implemented in hardware, firmware, software or a combination thereof, in accordance with the broad scope of the present invention. While a particular bus architecture is shown in
In one possible embodiment, one or more modules of disk controller 130 are implemented as part of a system on a chip (SoC) integrated circuit. In an embodiment, this SoC integrated circuit includes a digital portion that can include additional modules such as protocol converters, linear block code encoding and decoding modules, etc., and an analog portion that includes device controllers 105 and optionally additional modules, such as a power supply, etc. In a further embodiment, the various functions and features of disk controller 130 are implemented in a plurality of integrated circuit devices that communicate and combine to perform the functionality of disk controller 130.
When the drive unit 100 is manufactured, disk formatter 125 writes a plurality of servo wedges along with a corresponding plurality of servo address marks at equal radial distance along the disk 102. The servo address marks are used by the timing generator for triggering the “start time” for various events employed when accessing the media of the disk 102 through read/write heads 104.
In a possible embodiment, wireless communication device 53 is capable of communicating via a wireless telephone network such as a cellular, personal communications service (PCS), general packet radio service (GPRS), global system for mobile communications (GSM), and integrated digital enhanced network (iDEN) or other wireless communications network capable of sending and receiving telephone calls. Further, wireless communication device 53 is capable of communicating via the Internet to access email, download content, access websites, and provide steaming audio and/or video programming. In this fashion, wireless communication device 53 can place and receive telephone calls, text messages such as emails, short message service (SMS) messages, pages and other data messages that can include attachments such as documents, audio files, video files, images and other graphics.
Data recorded on magnetic disk platters in a drive follow a complex analog path from being initially “read” to final digitization in a read-channel. The feature-rich analog front end (AFE) of a read channel integrates multiple technologies in a single design used for horizontal (also known as longitudinal) recording techniques and higher capacity perpendicular recording. However, perpendicular recording may exhibit increased asymmetry when compare to horizontal recording which is symmetric with even symmetry. This may increase the processing demands placed on the AFE.
In the magnetic recording channel of a hard disk drive (HDD) or like media storage, noise components in the readback signals are correlated and user pattern dependent due to media noise, front-end equalizer and nonlinearity factors. In order to optimize the performance of sequence detector, data-dependent noise predictive (DDNP) filters (often referred to as whiteners) and data-dependent bias compensation terms are used in Viterbi branch metric calculation. There are generally two approaches to obtain DDNP settings (including whiteners and biases): (1) offline calibration; (2) and on-the-fly (OTF) DDNP adaptation. In offline calibration approach, noise statistics are collected in channel and passed to an offline processor, where the Yule-Walker sole solution or other may be applied involving matrix inversion operations to calculate DDNP filter coefficients. The DDNP-Viterbi ideal branch values are then calculated based on DDNP filters and biases. While the offline calibration approach involves inconvenient interactions between channel and offline processor, the OTF adaptation is a more ‘self-contained’ feature that users can turn on to ‘automatically’ acquire DDNP settings through internal channel circuits. This feature may be utilized in at least the following three scenarios: (1) self-scan mode during manufacturing; (2) pre-read mode when a drive is seeking for particular sector to read; and (3) normal read mode. In self-scan mode during manufacturing, DDNP may be calibrated for every zone and the calibrated settings may be stored in zone tables, and later loaded to channel registers so that in read mode users can start with good initial settings. Known NRZ data pattern, such as a pseudo-random sequence generated by a linear feedback shift register (LFSR), may be used in self-scan calibration.
In one particular embodiment, the DDNP filter bank contains 8 different 3-tap filters dependent on 4-NRZ bits for Longitudinal targets and 3-tap Perpendicular targets; for 2-tap Perpendicular targets, the DDNP filter bank contains 4 different 3-tap filters dependent on 3-NRZ bits; both with polarity symmetry enabled. For example, the NRZ pattern ‘0000’ shares the same filter as the NRZ pattern ‘1111’ as both are non-transition pattern. The bias compensation term is dependent on 5-NRZ bits for Longitudinal targets and 3-tap Perpendicular targets with totally 32 different bias values; and 4-NRZ bits for 2-tap Perpendicular targets with totally 16 different bias values. Each DDNP filter coefficient or DDNP bias is readable/writable through a SIF/PIF register.
Other block inputs may include DDNP_enable signal, C_UPDATE signal, and Updating gain signals. The DDNP_enable signal is an ‘AND’ signal between a register set bit ‘ADAPT_ENABLE’ and a signal coming from another channel block. No adaptation should be performed during preamble with only single-tone signal available. Therefore, DDNP adaptation should be held until syncmark found signal becomes active. However, in the normal read mode (when Viterbi preliminary decisions are used to reconstruct signals), if Euclidean-distance based syncmark detection delivers syncmark found signal earlier than the first non-preamble preliminary NRZ decision from Viterbi detector, the adaptation has to be further held until Viterbi delivers its earliest non-preamble NRZ decision. Whether this would happen depends on the latency of syncmark detection versus the latency in Viterbi detection plus the intrinsic latency from preliminary decisions as well as when Viterbi trellis would start after a read gate rises. If known data pattern is used for signal reconstruction, the DDNP adaptation could be enabled right after syncmark is found.
The C_UPDATE signal is a SIF/PIF programmable register bit that allows users to control whether to recalculate Viterbi branch mean values. The default value for this bit should be 1, i.e., recalculate Viterbi branch mean values for every read gate. However, in some special testing mode, users may want to intentionally introduce gain mismatch between Viterbi branch mean values and targets by not updating Viterbi branch mean values when target changes. In such cases, ‘C_UPDATE’ is set to 0.
The Updating gain signals: ‘TAP_UG’, ‘GTAP_UG’ and ‘BIAS_UG’ are signals that control the updating gains of tap adaptation, gain scaling adaptation and bias adaptation sub-blocks respectively. Gain multiplication is implemented by right shifting accumulation term and aligning it in the accumulator.
As shown in
Other Block Output Signals of the adaptation block include saturation flags. Saturation flags are flags indicating whether saturation occurs during adaptation for 1st tap of DDNP filters and biases respectively. Any element in the corresponding bank saturates, the flag would be set. The 1st tap of DDNP filters could overflow when the reference pattern does not yield minimum power among all NRZ conditions. Biases could overflow/underflow when the uncompensated offset at the FIR output is too large.
The whitener coefficient adaptation applies quantized-LMS method. In order to avoid the adaptation converging to a trivial solution as all-zero filters, the main tap (1st tap) is not adapted in this adaptation sub-block. Therefore, the hardware implementation as showed in
Also, the same NRZ pattern used to calculate ERR_W should be used in the adaptation driven by the same ERR_W signal. Therefore, NRZ_adapt_sel is a delayed version of NRZ_cal_sel as D(NRZ_cal_sel,NRZ_adapt_sel)=D(NRZ_cal_sel,ERR_W) so that NRZ_adapt_sel is properly aligned with ERR_W. Besides, any hardware implementation latencies involved in slicing circuit, accumulation circuits, etc should also be taken into consideration properly. Since whitened noise power used in Viterbi branch metric calculation is also data-dependent, the main tap may be scaled (thus the output signal gain and power) so that each whitener provides uniform power over different data patterns. One step further, a reference pattern can be used to ‘define’ a reference power and the whitened noise power for all other patterns can be normalized to the reference one.
Embodiments of the present invention provide a data-dependent noise predictive (DDNP) adaptation module operable to support Viterbi branch metric calculations within a hard disk drive (HDD) controller. This DDNP adaptation module includes a DDNP filter tap coefficient adaptation module, a DDNP filter gain scaling module, and a DDNP bias compensation module. The combination of the DDNP filter tap coefficient adaptation module, the DDNP filter gain scaling module, and the DDNP bias compensation module is operable to receive an error signal and a NRZ pattern and produce tap coefficients. A whitened error signal calculation module coupled to the DDNP filter tap coefficient adaptation module, the DDNP filter gain scaling module, and the DDNP bias compensation module, the whitened error signal calculation module operable to calculate a whitened error signal based on the error signal, NRZ pattern, and tap coefficients. This whitened error signal is used to support the Viterbi branch metric calculations.
As one of average skill in the art will appreciate, the term “substantially” or “approximately”, as may be used herein, provides an industry-accepted tolerance to its corresponding term. Such an industry-accepted tolerance ranges from less than one percent to twenty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. As one of average skill in the art will further appreciate, the term “operably coupled”, as may be used herein, includes direct coupling and indirect coupling via another component, element, circuit, or module where, for indirect coupling, the intervening component, element, circuit, or module does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As one of average skill in the art will also appreciate, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two elements in the same manner as “operably coupled”. As one of average skill in the art will further appreciate, the term “compares favorably”, as may be used herein, indicates that a comparison between two or more elements, items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1.
Although the present invention is described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention as described by the appended claims.
The present U.S. Utility patent application claims priority pursuant to 35 U.S.C. § 119(e) to the following U.S. Provisional Patent Application which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility patent application for all purposes: 1. U.S. Provisional Application Ser. No. 60/889,799, entitled “ADAPTIVE DATA-DEPENDENT NOISE PREDICTION,” (Attorney Docket No. BP5832), filed Feb. 17, 2007, pending.
| Number | Date | Country | |
|---|---|---|---|
| 60889799 | Feb 2007 | US |
