Adaptive digital filter, and method of renewing coefficients thereof

Abstract

An adaptive digital filter has a series of delay elements for imparting a unit delay of one sampling interval to successive input data samples in order to concurrently obtain a set of data samples of different sampling items. Each set of data samples are multiplied by respective coefficients, and the resulting multiplier outputs are added together into a filter output for comparison with a reference signal. The coefficients are renewed a preassigned number of times during each sampling interval, and the last renewed coefficients are used for each new set of data samples. For such coefficient renewal, a plurality of arithmetic circuits are connected in parallel for simultaneously performing the necessary computations for the renewal of all the coefficients.

Description

BACKGROUND OF THE INVENTION

This invention relates to an adaptive filter which is a type of digital filter used for noise canceling, system modeling, among other applications, and to a method of renewing its coefficients for each new set of input data samples.

A variety of algorithms have been devised and used for adaptive data processing. Examples are the least mean square (LMS) algorithm and the recursive least square (RLS) algorithm. The LMS algorithm in particular has been used most extensively by virtue of a smaller amount of computations required, simplicity of circuitry, and ease of implementation, even though it is poorer in convergence than the other algorithms.

FIG. 1 of the attached drawings shows a prior art adaptive digital filter based on the LMS algorithm. It has an input terminal 10 for receiving input data samples x(k) at constant sampling intervals. The input terminal 10 is connected to a series of L (integer of more than one) delay elements M.sub.1, M.sub.2, . . . M.sub.L which successively impart a unit delay of one sampling interval to the input data samples x(k). Accordingly, (L+1) input data samples x(k), x(k-1), x(k-2), . . . x(k-L) of different sampling intervals are obtained concurrently on (L+1) lines C.sub.0 -C.sub.L, respectively, which are connected respectively to the input terminal 10 and to the outputs of the delay elements M.sub.1 -M.sub.l. Multipliers A.sub.0, A.sub.1, . . . A.sub.L multiply the input data samples x(k)-x(k-L) by respective coefficients w.sub.0 (k), w.sub.1 (k), . . . w.sub.L (k), thereby producing outputs x(k)w.sub.0 (k), x(k-1)w.sub.1 (k), . . . x(k-L)w.sub.L (k). These outputs x(k)w.sub.0 (k)-x(k-L)w.sub.L (k) are all directed into an adder 12 thereby to be added together into an output y(k). This output y(k) is then applied to a difference detector 14, which produces a difference signal e(k) representative of the difference between the adder output y(k) and a reference signal d(k).

The adder output y(k) and the difference detector output e(k) can be expressed as:

y(k)=w.sub.0 (k)x(k)+w.sub.1 (k)x(k-1) . . . +w.sub.L (k)x(k-L)(1) e(k)=d(k)-y(k). (2).

In adaptive digital filters in general, the coefficients w.sub.0 (k)-w.sub.L (k) are renewed for each sampling interval as by a digital signal processor. Each set of input data samples x(k)-x(k-L) on the lines C.sub.0 -C.sub.L are multiplied by each renewed set of coefficients. New coefficients at discrete time k are obtained by the equation:

wi(k)=wi(k-1)+2 .mu.e(k-1)x(k-1) (3) where k-1=discrete time of the sampling interval preceding that of the time k i=variable indicating the 0'th to L'th of the lines C.sub.0 -C.sub.L wi(k-1)=coefficients of the preceding sampling interval e(k-1)=difference signal of the preceding sampling interval x(k-1)=input data of the preceding sampling interval .mu.=constant called stepsize.

The stepsize constant is defined by the formula:

0<.mu.<1/.lambda..sub.max ( 4) where .lambda..sub.max =maximum of the eigenvalues of the correlation matrix of the input data x(k).

Theoretically, the stepsize .mu. should be as great as possible purely for the purpose of speeding the convergence of the LMS algorithm. However, actually, the stepsize has the upper limit determined by the formula (4) above. Too great a value of the stepsize is also undesirable from the standpoint of system stability.

A solution to this problem is found in the article entitled "Performance Improvement of LMS Algorithm" by Takahashi in pp. 19-24 of the Vol. 74-A, No. 1 issue of The Transactions of the Institute of Electronics, Information and Communication Engineers published Jan. 25, 1991, by the Institute of Electronics, Information and Communication Engineers of Tokyo, Japan. Essentially, Takahashi teaches a coefficient renewal method that does not rely on the difference signal e(k) but which is based upon the similarity between LMS and the Hopfield neural network model. For more details on neutral networks, reference may be had to the article entitled "Neural Networks for Computation: Number Representations and Programming Complexity" by Takeda et al. in the Volume 25, Number 18 issue of Applied Optics published by the Optical Society of America.

The Hopfield neural network model is shown in FIG. 2 in order to make clear its relationship with the present invention. The Hopfield model consists of a multiplicity of mutually interconnected nonlinear devices called neurons. The states of these neurons are characterized by their outputs that take binary values 0 and 1. The dynamics of neurons in the Hopfield model can be described in both discrete and continuous spaces. The strengths of interconnections between neurons are symmetrical. Input U.sub.i to each neuron i is defined as: ##EQU1## where N=number of neurons

T.sub.ij =elements of an interconnection matrix representing the strengths of connections I.sub.i =bias input of each neuron i.

The output V.sub.i of each neuron i is renewed as follows in the discrete model: ##EQU2##

If the strengths T.sub.ij of interconnections are symmetrical, that is, if T.sub.ij =T.sub.ji, then the network energy E expressed by the following equation will reduce to a minimum with the network operation: ##EQU3##

In order to associate the Hopfield model with the prior art adaptive filter of FIG. 1, the output of each neuron at the time k may be expressed as the sum of the function g[U.sub.i (k)] and the neuron output V.sub.i (k-1) at the time (k-1): ##EQU4##

The function (g) is defined as follows for correspondence with the LMS algorithm: ##EQU5##

The thus defined network energy can be expressed by the following equation, which is the same as Equation (7): ##EQU6##

The network energy as defined by Equation (10) changes as follows when the output of each neuron i changes from V.sub.i (k-1) to V.sub.i (k) from time (k-1) to time k: ##EQU7##

From the relations of Equation (9), the change of the network energy is always negative, with the energy decreasing with network operation. The square of the difference signal e(k) may be used as follows in order to apply the model of Equation (8) to the prior art adaptive filter of FIG. 1: ##EQU8##

The energy E in Equation (12) is the quadratic function of the coefficients of the prior art adaptive filter at the time k and has a single minimum value. The output V in Equation (10) correspond to the coefficients w in Equation (12), and T.sub.ij and I.sub.i in Equation (10) correspond respectively to -2x(k-i)x(k-j) and 2d(k)x(k-i). Let the former be T.sub.ij (k) and the latter I.sub.i (k). Then ##EQU9##

The term d.sup.2 (k) in Equation (12) is constant and so negligible.

In the Takahashi article cited above, T.sub.ij (k) and I.sub.i (k) are computed to renew the coefficients W.sub.0 (k)-W.sub.L (k) of the prior art FIG. 1 adaptive filter. More specifically, Takahashi teaches a coefficient renewal method for an adaptive digital filter of the kind comprising: (a) means for supplying a reference signal k(k) at predetermined sampling times; (b) means for supplying samples of input data, associated with the reference signal, at the predetermined sampling times; and (c) data processing means for concurrently providing (L+1) input data samples, from 0'th to L'th, by successively imparting a unit delay of one predetermined sampling interval to the input data samples, for multiplying the 0'th to L'th input data samples by 0'th to L'th coefficients w.sub.0 (k), w.sub.1 (k), . . . w.sub.L (k), respectively, and for adding all the multiplied data samples into an output y(k).

Takahashi's method comprises the steps of: (a) computing, from the (L+1) input data samples and the reference signal at any one sampling time k:

T.sub.ij (k)=-2x(k-i)x(k-j) I.sub.i (k)=2d(k)x(k-i) where i and j=variable denoting the digits from 0'th to L'th T.sub.ij (k)=(L+1).sup.2 values used in renewal computation of the coefficients I.sub.i (k)=(L+1) values used in renewal computation of the coefficients x(k-i)=(L+1) data samples selected successively from the concurrently obtained (L+1) samples x(k-j)=(L+1) data samples selected successively from the concurrently obtained (L+1) samples; (b) renewing, on the bases of the above computed T.sub.ij (k) and I.sub.i (k) and the coefficients w.sub.0 (k)-w.sub.L (k) at the sampling time k, the coefficients n times, where n is an integer of at least two, during a time interval from the sampling time k to the next sampling time (k+1) according to the equation: ##EQU10## where w.sub.i n-1=values of the (L+1) coefficients before being renewed at each of the n renewals w.sub.i n(k)=values of the (L+1) coefficients after being renewed at each of the n renewals w.sub.j n-1(k)=(L+1) coefficients before being renewed; and (c) using the values of the coefficients obtained at the n'th renewal as the coefficients for the next sampling time (k+1).

The range of values of the stepsize constant for the convergence of Takahashi's modified LMS algorithm is the same as that for the conventional LMS algorithm, set forth in Equation (4). However, since Takahashi method teaches n renewals of the coefficients during each sampling interval, the time constant is 1/4 .mu.n.lambda. which is 1/n of the time constant, 1/4 .mu..lambda., of the conventional LMS algorithm. This advantage has been offset, however, by a relatively large amount of computations required for coefficient renewal.

SUMMARY OF THE INVENTION

The present invention seeks to simplify and speed the computations required for coefficient renewal in an adaptive digital filter system of the type under consideration.

According to the invention, stated in brief, there are provided as many arithmetic circuits as there are a set of coefficients to be renewed. Thus the n renewals of the coefficients for each set of data samples can be carried out in parallel or concurrently. The process of such coefficient renewal is materially simplified as the coefficients renewed at each of the n renewals during each sampling interval can be used as initial values to be renewed at the next renewal.

The above and other features and advantages of this invention and the manner of realizing them will become more apparent, and the invention itself will best be understood, from a study of the following description and appended claims, with reference had to the attached drawings showing the closest prior art and a preferred embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the prior art adaptive digital filter system;

FIG. 2 is a block diagram of the known Hopfield neural network model;

FIG. 3 is a block diagram of the adaptive digital filter system in accordance with the invention;

FIG. 4 shows the FIG. 3 system in its most simplified form for the ease of understanding;

FIG. 5 is a schematic electrical diagram of a circuit for testing the convergence of the FIG. 3 system;

FIG. 6 is a graphic representation of the results of a test conducted by use of the FIG. 5 circuit;

FIG. 7 is a similar representation of the results of another test conducted by use of the FIG. 5 circuit;

FIG. 8 is a similar representation of the results of testing a prior art system by use of the FIG. 5 circuit;

FIG. 9 is a block diagram showing the coefficient renewal circuit of the FIG. 3 system in detail; and

FIG. 10 shows the FIG. 9 circuit in simplified form for the ease of understanding.

DETAILED DESCRIPTION

The present invention will now be described in detail as embodied in the adaptive digital filter system shown in FIG. 3 and therein generally designated 20. The representative filter system 20 is shown as a combination of a transversal filter circuit 22 and a difference detector circuit 24, although in practice part or whole of the illustrated system may be computerized or constituted of an integral digital data processor.

The filter system 20 has a data input 26 for inputting data samples x(k) sampled at predetermined constant intervals. As in the prior art device of FIG. 1, the data input 26 is connected to a series of L delay elements M.sub.1, M.sub.2, . . . M.sub.L which successively impart a unit delay of one predetermined sampling interval to the input data samples x(k). Accordingly, (L+1) input data samples x(k), x(k-1), x(k-2), . . . x(k-L) of different sampling intervals are obtained concurrently on (L+1) lines C.sub.0 -C.sub.L, respectively, connecting the input terminal 10 and the outputs of the delay elements M.sub.1 -M.sub.1 to respective multipliers A.sub.0, A.sub.1, . . . A.sub.L. These multipliers multiply the input data samples x(k)-x(k-L) by respective coefficients w.sub.0 (k), w.sub.1 (k), . . . w.sub.L (k), thereby producing outputs x(k)w.sub.0 (k), x(k-1)w.sub.1 (k), . . . x(k-L)w.sub.L (k). These outputs x(k)w.sub.0 (k)-x(k-L)w.sub.L (k) are all directed into an adder 28 thereby to be added together into an output y(k). This output y(k) is then applied to the difference detector circuit 24, which produces a difference signal e(k) representative of the difference between the adder output y(k) and a reference signal d(k) supplied from a reference signal input 30.

The filter system 20 relies on the input data x(k) and the reference signal d(k), instead of on the difference signal e(k) as in the FIG. 1 prior art system, for renewal of the coefficients w.sub.0 (k), w.sub.1 (k), . . . w.sub.L (k). Thus the data input 26 and the reference signal input 30 are both connected to a coefficient renewal circuit 32, which has outputs connected respectively to the multipliers A.sub.0 -A.sub.L. The coefficient renewal circuit 32 computes and renews the coefficients w.sub.0 (k)-w.sub.L (k) n times during each predetermined sampling period and delivers the last set of renewed coefficients to the multipliers A.sub.0 -A.sub.L. More will be said presently about the details of the coefficient renewal circuit 32.

The coefficient renewal circuit 32 renews the coefficients by use of T.sub.ij (k) and I.sub.i (k) defined in Equations (13). Since both i and j denote digits from 0 to L, T.sub.ij (k) has (L+1).sup.2 values including equivalent values. Namely, T.sub.ij has the following values: ##EQU11##

T.sub.01 and T.sub.10, T.sub.02 and T.sub.20, etc., represent essentially the same value. I.sub.i has the following (L+1) values:

I.sub.0, I.sub.1, I.sub.2, I.sub.3, . . . I.sub.L.

The coefficients are renewed on the bases of T.sub.ij (k), I.sub.i (k) and initial or unrenewed coefficients w.sub.i n-1(k) and w.sub.j n-1(k), according to the equation: ##EQU12## where w.sub.i n(k) represents the coefficients after being renewed at each of the n renewals. Since n represents the number of times the coefficients are renewed, it may be any number from one to ten if the coefficients are to be renewed ten times. The suffixes i and j in Equation (14) have the same meanings as defined above. Thus, in Equation (14), w.sub.i n(k) represent (L+1) values: ##EQU13##

It is the tenth renewed set of coefficients that are supplied from the coefficient renewal circuit 32 to the respective multipliers A.sub.0 -A.sub.L and used as the coefficients w.sub.0 (k)-w.sub.L (k) in the FIG. 3 system.

The first term, w.sub.i n-1(k), of the right side of Equation (14) represents the coefficients at the end of the first renewal. Therefore, for the first renewal at the time k, the coefficients at the end of the tenth renewal of the time (k-1) of the preceding sampling period are used as the w.sub.i n-1(k). Initial or unrenewed coefficients w.sub.i n-1(k) at each renewal are as follows: ##EQU14##

Also, in Equation (14), w.sub.j n-1(k) is essentially equivalent to w.sub.i n-1(k) since j is equivalent to i. However, in this equation, w.sub.j n-1(k) represents all of the (L+1) coefficients whereas w.sub.i n-1(k) represents each specified coefficient. Equation (14) indicates that the computation of a coefficient on the arbitrary ith of the lines C.sub.0 -C.sub.L requires not only the initial coefficient w.sub.i n-1(k) on the ith line but also the initial coefficients w.sub.j n-1(k) on the other lines. The initial coefficient on the ith line is included in w.sub.j n-1(k).

Actual computations according to Equation (14) are as follows: ##EQU15##

It is thus seen that the set of coefficients renewed at each of the ten renewals are used as initial values at the next renewal. For instance, w.sub.10 (k) used for computing the coefficient on 0'th line C.sub.0 at the second renewal is the coefficient w.sub.01 (k) renewed at the first renewal. Further, w.sub.j1 (k) included in Equations (16) for the second renewal represents w.sub.01 (k), w.sub.11 (k), w.sub.21 (k), w.sub.31 (k), . . . w.sub.L1 (k) and thus agrees with the coefficients renewed at the first renewal.

The reader's attention is now invited to FIG. 4 for a better understanding of how the coefficients are renewed according to the invention, with the coefficients w.sub.0 (k) and w.sub.1 (k) taken for example. It has been stated that as one data sample x(k) is received at the data input 26 at any discrete time k, the first delay element M.sub.1 puts out a data sample x(k-1) of the preceding sampling time, so that the two data samples x(k) and x(k-1) are obtained concurrently on the lines C.sub.0 and C.sub.1. At the multipliers A.sub.0 and A.sub.1 the data samples x(k) and x(k-1) are multiplied by the respective coefficients w.sub.0 (k) and w.sub.1 (k). The resulting outputs x(k)w.sub.0 (k) and x(k-1)w.sub.1 (k) are added into y(k) by the adder 28.

Let us assume for the convenience of disclosure that the coefficients are renewed twice, rather than ten times as set forth above, during each sampling period. First of all, T.sub.ij (k) and I.sub.i (k) are obtained according to Equations (13) from the two input samples x(k) and x(k-1) and reference signal d(k) at the time k. T.sub.ij (k) is:

-2x(k)x(k) [let this be T.sub.00 (k)], -2x(k-1)x(k) [T.sub.01 (k)], -2x(k)x(k-1) [T.sub.10 (k)], and -2x(k-1)x(k-1) [T.sub.11 (k)].

I.sub.i (k) is:

2d(k)x(k) [I.sub.0 (k)] and 2d(k)x(k-1) [I.sub.1 (k)].

Then the first and second initial coefficients w.sub.00 (k+1) and w.sub.10 (k+1), for use at the next sampling time (k+1), are determined from the above determined T.sub.00 (k), T.sub.01 (k), T.sub.10 (k), T.sub.11 (k), I.sub.0 (k) and I.sub.1 (k), the first and second unrenewed coefficients w.sub.00 (k) and w.sub.10 (k) and the stepsize .mu.. The first coefficient renewed for the first time, w.sub.01 (k), is obtained as follows according to Equation (14):

w.sub.01 (k)=w.sub.00 (k)+.mu.[T.sub.00 (k)w.sub.00 (k)+T.sub.01 (k)w.sub.10 (k)+I.sub.0 (k)] (19).

For renewal of the coefficient on the line C.sub.0, i in Equation (14) is fixed at 0, so that w.sub.i, T.sub.ij and I.sub.i are w.sub.00, T.sub.00, T.sub.01 and I.sub.0. The second coefficient renewed for the first time, w.sub.11 (k), is likewise determined according to Equation (14):

w.sub.11 (k)=w.sub.10 (k)+.mu.[T.sub.10 (k)w.sub.00 (k)+T.sub.11 (k)w.sub.10 (k)I.sub.i (k)] (20).

For renewal of the coefficient on the line C.sub.1, i in Equation (14) is fixed at 1, so that w.sub.i, T.sub.ij and I.sub.i are w.sub.10, T.sub.10, T.sub.11 and I.sub.1.

Then the first coefficient renewed for the second time, w.sub.02 (k), is obtained as follows according to Equation (14):

w.sub.02 (k)=w.sub.01 (k)+.mu.[T.sub.00 (k)w.sub.01 (k)+T.sub.01 (k)w.sub.11 (k)+I.sub.0 (k)] (21).

The second coefficient renewed for the second time, w.sub.12 (k), is likewise obtained as follows according to Equation (14):

w.sub.12 (k)=w.sub.11 (k)+.mu.[T.sub.10 (k)w.sub.01 (k)+T.sub.11 (k)w.sub.11 (k)+I.sub.1 (k)] (22).

Then the two coefficients renewed for the second time as above, w.sub.02 (k) and w.sub.12 (k), are directed into the respective multipliers A.sub.0 and A.sub.1. The input data samples x(k+1) and x(k) of the next sampling time (k+1) are multiplied by the respective coefficients w.sub.02 (k) and w.sub.12 (k).

With the coefficients renewed twice, as set forth in the foregoing with reference to FIG. 4, the time constant will become half that of the conventional method. However, for still higher convergence, the coefficients may be renewed a greater number of times in a like manner.

The convergence of the adaptive digital filter 20 according to the invention was tested by the circuitry shown in FIG. 5. The test circuitry had two input terminals 34 and 36 connected to an adder 38 on the preceding stage of the data input 26. A sinusoidal wave of sin (2.pi.k/N), where N represents an arbitrary number, was supplied to the first input terminal 34, and white noise r(k) with an average of 0 and a variance of 0.01 to the second input terminal 36. The two inputs were combined into the input signal x(k) supplied to the data input 26. The reference signal d(k) received at the reference signal input 30 was 2 cos (2.pi.k/N).

FIGS. 6 and 7 are graphic analog representations of the variations of the coefficients w.sub.0 and w.sub.1 according to the FIG. 5 test circuitry. FIG. 8 is a similar representation of the variations of the coefficients according to the prior art method wherein the coefficients are renewed only once during each sampling period on the basis of the difference signal e(k). The sample numbers on the horizontal axes of FIGS. 6-8 start from Sample No. 0 at the time k, so that the horizontal axes represent time. The stepsize constant .mu. was 0.01, and the number n of renewals was 10, in FIG. 6; .mu. was 0.10, and n was 10, in FIG. 7; and .mu. was 0.10 in FIG. 8.

A comparison of FIGS. 6 and 7 indicates that the adaptive filter system according to the invention is just as favorable in convergence if the stepsize is made of one tenth of that of the prior art. A comparison of FIGS. 7 and 8, on the other hand, proves that convergence greatly improves according to the invention if the stepsize is the same as in the prior art. This is evident from the fact that convergence occurs at Sample No. 50 in FIG. 7 according to the invention, and at Sample No. 500 in FIG. 8 according to the prior art.

Admittedly, the variations of the coefficients are more pronounced in FIG. 7 than in FIG. 8. The present invention may therefore be employed advantageously in applications where convergence is of greater significance than such variations. Of course, as desired or required, the number n of coefficient renewals may be varied according to the degree of convergence; that is, the number n may be made high during a period of adaptation and decreased after convergence.

FIG. 9 is a detailed illustration of an example of coefficient renewal circuit 32 in the adaptive filter system 20 FIG. 3. The exemplified coefficient renewal circuit 32 has (L+1) arithmetic circuits S.sub.0, S.sub.1, . . . S.sub.L each for performing arithmetic operations necessary for renewing one of the (L+1) coefficients. Each arithmetic circuit comprises a multiplier 40, an adder 42 and a delay circuit 44. The multiplier 40 has its inputs connected to two circuit inputs 46 and 48, respectively. The adder 42 has two inputs connected respectively to the multiplier 40 and to the delay circuit 44 which may take the form of a memory in practice. The output of the adder 42 is connected to both the delay circuit 44 and a circuit output 50.

The inputs 46 of all the arithmetic circuits S.sub.0 -S.sub.L are connected to a data supply circuit 52 which puts out data representative of both unrenewed or initial coefficients w.sub.j n-1(k) and the digit 1. As has been stated, w.sub.j n-1(k) represents the (L+1) coefficients W.sub.0 n-1(k), w.sub.1 n-1(k), . . . w.sub.L n-1(k) on the respective lines C.sub.0, C.sub.1, . . . C.sub.L of FIG. 3. The data supply circuit 52 has therefore inputs connected to the outputs 50 of all the arithmetic circuits S.sub.0 -S.sub.L, which outputs are also connected to the respective multipliers A.sub.0 -A.sub.L of FIG. 3

The other inputs 48 of the arithmetic circuits S.sub.0 -S.sub.L are connected respectively to (L+1) data supply circuits B.sub.0 -B.sub.L. These data supply circuits compute the product of the value T.sub.ij (k) and the stepsize .mu., and the product of the value I.sub.i (k) and the stepsize .mu., according to Equations (13) and put out data representative of the products .mu.T.sub.ij (k) and .mu.I.sub.i (k). For computing these products the data supply circuits B.sub.0 -B.sub.L have their inputs connected to both the data input 26 and the reference signal input 30.

Despite the showing of FIG. 9, however, the products T.sub.ij (k) and I.sub.i (k) needed for renewal of the (L+1) coefficients differ for all the data supply circuits B.sub.0 -B.sub.L. For example, the 0'th data supply circuit B.sub.0 puts out .mu.T.sub.00 (k), .mu.T.sub.01 (k), .mu.T.sub.02 (k), . . . .mu.T.sub.0L (k) as .mu.T.sub.ij (k), and .mu.I.sub.1 (k) as .mu.I.sub.i (k). The L'th data supply circuit B.sub.L puts out .mu.T.sub.L0 (k), .mu.T.sub.L1 (k), .mu.T.sub.L2 (k), . . . .mu.T.sub.LL (k) as .mu.T.sub.ij (k), and .mu.I.sub.L (k) as .mu.I.sub.i (k).

In the operation of the coefficient renewal circuit 32, the data supply circuit 52 periodically and successively delivers the (L+1) initial values, labeled w.sub.j n-1(k) in Equation (14), to the multipliers 40 of the arithmetic circuits S.sub.0 -S.sub.L. However, when the system is turned on, w.sub.j n-1(k) is zero or, alternatively, may be one or any other constant.

Simultaneously, the data supply circuits B.sub.0 -B.sub.L delivers .mu.T.sub.ij (k) to the multipliers 40 of the arithmetic circuits S.sub.0 -S.sub.L, respectively. .mu.T.sub.ij (k) represents as aforesaid .mu.T.sub.0j (k), .mu.T.sub.1j (k), .mu.T.sub.2j (k), . . . .mu.T.sub.Lj (k). Since the suffix j stands for (L+1) values from 0 to L, the 0'th data supply circuit B.sub.0 successively puts out .mu.T.sub.00 (k), .mu.T.sub.01 (k), .mu.T.sub.02 (k), . . . .mu.T.sub.0L (k) as .mu.T.sub.ij (k). Similarly, the first data supply circuit B.sub.1 successively puts out .mu.T.sub.10 (k), .mu.T.sub.11 (k), .mu.T.sub.12 (k), . . . .mu.T.sub.1L (k) as .mu.T.sub.ij (k). Also, the L'th data supply circuit B.sub.L successively puts out .mu.T.sub.L0 (k), .mu.T.sub.L1 (k), .mu.T.sub.L2 (k), . . . .mu.T.sub.LL (k) as .mu.T.sub.ij (k).

Receiving the inputs as above, the arithmetic circuits S.sub.0 -S.sub.L performs arithmetic operations according to Equation (14). Initially, the delay circuits 44 has no data stored therein. However, repeating computations according to Equation (18) in response to the .mu.I.sub.i (k) and .mu.T.sub.ij (k) data from the data supply circuits B.sub.0 -B.sub.L, the arithmetic circuits S.sub.0 -S.sub.L will start producing coefficient outputs.

Let us assume for the ease of explanation that the data supply circuit 52 already received the initial values w.sub.j n-1(k) from the arithmetic circuits S.sub.0 -S.sub.L at the previous sampling time (k-1), and that the delay circuits 44 has the initial values w.sub.i n-1(k) stored therein. Then the data supply circuit 52 will successively produce the (L+1) initial coefficients w.sub.j n-1(k) in order to enable the arithmetic circuits S.sub.0 -S.sub.L to perform the computations of Equations (15) for the first coefficient renewal at the time k. w.sub.j n-1(k) represents as aforesaid w.sub.00 (k), w.sub.10 (k), w.sub.20 (k), . . . w.sub.L0 (k) when n-1=0.

Thus, as the data supply circuit first puts out w.sub.00 (k), all the arithmetic circuits S.sub.0 -S.sub.L will concurrently start computing w.sub.01 (k), w.sub.11 (k), . . . w.sub.L1 (k) in Equations (15). All Equations (15) contain w.sub.j0 (k), so that the data supply circuit 52 can simultaneously deliver w.sub.j0 (k) to all the arithmetic circuits S.sub.0 -S.sub.L. Since w.sub.j0 (k), which corresponds to w.sub.j n-1(k), represents (L+1) values w.sub.00 (k), w.sub.10 (k), w.sub.20 (k), . . . w.sub.L0 (k), the data supply circuit 52 will first put out w.sub.00 (k) as w.sub.j n-1(k).

At the arithmetic circuits S.sub.0 -S.sub.L, the multipliers 40 will compute .mu.T.sub.01 (k)w.sub.10 (k) as .mu.T.sub.0j (k)w.sub.j0 (k) which corresponds to .mu.T.sub.ij w.sub.j n-1(k). .mu.T.sub.01 (k) is supplied from B.sub.0. Then the adders 42 will add the multiplier outputs .mu.T.sub.01 (k)w.sub.10 (k) and the delay circuit outputs w.sub.00 (k)+.mu.T.sub.00 (k)w.sub.00 (k) to each other into W.sub.00 (k)+.mu.T.sub.00 (k)w.sub.00 (k)+.mu.T.sub.10 (k)w.sub.10 (k). The adder outputs are held in the delay circuits 44. Then the multipliers 40 will successively multiply the other values w.sub.20 (k)-w.sub.L0 (k) of w.sub.j0 (k) by .mu.T.sub.0j (k). There can thus be obtained the values for ##EQU16## in Equations (15) which corresponds to ##EQU17## in Equation (14).

Then, in order to add I.sub.0 (k) in Equations (15) which corresponds to I.sub.i (k) in Equation (14), the data supply circuit 52 will deliver the digit "1", and the data supply circuit B.sub.0 -B.sub.L will deliver .mu.I.sub.0 (k), to the multiplier 40. Consequently, .mu.I.sub.0 (k) will pass unchanged through the multiplier 40. Then, at the adder 42, .mu.I.sub.0 (k) will be added to the delay circuit output ##EQU18## The first renewal of the first coefficient, as well as of all the other coefficients, has now been completed according to Equations (15). All the coefficients, concurrently renewed for the first time as above, will be held in the delay circuits 44 and also delivered to the data supply circuit 52.

Then the coefficients will be renewed for the second time according to Equations (16) and then for the third time according to Equations (17). The same procedure will be repeated thereafter until the coefficients are renewed for the tenth time according to Equations (18). The ten renewals will be performed far more quickly than heretofore because all the coefficients are renewed simultaneously at each time.

The tenth renewed coefficients w.sub.010 (k)-w.sub.L10 (k) will be supplied to the respective multipliers A.sub.0 -A.sub.L as the renewed coefficients for use at the time (k+1). Also, the tenth renewed coefficients will be held in the delay circuits 44 and further directed into the data supply circuit 52, for use as the initial coefficients to be renewed during the next sampling period from time (k+1) to time (k+2).

The foregoing description of FIG. 9 will be better understood by referring to FIG. 10, in which the coefficient renewal circuit 32 of FIG. 9 is shown simplified, having but two arithmetic circuits S.sub.0 and S.sub.1 and two associated data supply circuits B.sub.0 and B.sub.1. Let it also be assumed for simplicity that the two coefficients are renewed only twice during each sampling interval.

Thus the data supply circuit 52 stores the initial coefficients w.sub.00 (k) and w.sub.10 (k), corresponding to w.sub.j n-1(k) in FIG. 9, for use at the first renewal, as well as the digit "1". The data supply circuit B.sub.0 stores .mu.T.sub.0 (k), corresponding to .mu.I.sub.i (k) in FIG. 9, and .mu.T.sub.00 (k) and .mu.T.sub.01 (k), corresponding to .mu.T.sub.ij (k) in FIG. 9. The data supply circuit B.sub.1 similarly stores .mu.I.sub.i (k), .mu.T.sub.10 (k) and .mu.T.sub.11 (k).

Equations for the first renewal of the two coefficients are, according to Equations (19) and (20):

w.sub.01 (k)=w.sub.00 (k)+.mu.[T.sub.00 (k) w.sub.00 (k)+T.sub.01 (k) w.sub.10 (k)+I.sub.0 (k)] w.sub.11 (k)=w.sub.10 (k)+.mu.[T.sub.10 (k) w.sub.00 (k)+T.sub.11 (k) w.sub.10 (k)+I.sub.i (k)].

The first renewal of the coefficients starts as the data supply circuit 52 delivers the first coefficient w.sub.00 (k), which has been determined at the previous sampling time (k-1), to the multipliers 40 of the two arithmetic circuits S.sub.0 and S.sub.1. Simultaneously, the data supply circuits B.sub.0 and B.sub.1 supply .mu.T.sub.00 (k) and .mu.T.sub.10 (k) to the respective multipliers 40. Thus the multipliers 40 will put out .mu.T.sub.00 (k)w.sub.00 (k) and .mu.T.sub.10 (k)w.sub.00 (k), respectively.

Then, at the adders 42, the unrenewed coefficients w.sub.00 (k) and w.sub.10 (k) which have been held in the delay circuits 44 will be added to the multiplier outputs:

w.sub.00 (k)+.mu.T.sub.00 (k) w.sub.00 (k) w.sub.10 (k)+.mu.T.sub.10 (k) w.sub.00 (k).

The delay circuits 44 will hold the respective sums thus obtained. Then the data supply circuit 52 will deliver w.sub.10 (k) to the multipliers 40 of both arithmetic circuits S.sub.0 and S.sub.1, and the data supply circuits B.sub.0 and B.sub.1 will also deliver .mu.T.sub.01 (k) and .mu.T.sub.11 (k) to the respective multipliers 40, with the consequent production of .mu.T.sub.01 (k)w.sub.10 (k) and .mu.T.sub.11 (k)w.sub.10 (k) from the multipliers. Then the adders 42 will add the delay circuit outputs to the multiplier outputs:

w.sub.00 (k)+.mu.T.sub.00 (k) w.sub.00 (k)+.mu.T.sub.01 (k) w.sub.10 (k) w.sub.10 (k)+.mu.T.sub.10 (k) w.sub.00 (k)+.mu.T.sub.11 (k) w.sub.10 (k).

The delay circuits 44 will hold the respective sums thus obtained. Then the data supply circuit 52 will deliver the digit "1" to both multipliers 40, and the data supply circuits B.sub.0 and B.sub.1 will deliver .mu.I.sub.0 (k) and .mu.I.sub.1 (k) to the respective multipliers 40. The resulting outputs from the multipliers 40, .mu.I.sub.0 (k) and .mu.I.sub.1 (k) will be added to the delay circuit outputs by the adders 42:

w.sub.00 (k)+.mu.T.sub.00 (k) w.sub.00 (k)+.mu.T.sub.01 (k) w.sub.10 (k)+.mu.I.sub.0 (k). w.sub.10 (k)+.mu.T.sub.10 (k) w.sub.00 (k)+.mu.T.sub.11 (k) w.sub.10 (k)+.mu.I.sub.1 (k)

These computations are in accordance with Equations (19) and (20). The thus renewed coefficients satisfy Equation (14). The first renewal of the two coefficients has now been completed. The renewed coefficients w.sub.01 (k) and w.sub.11 (k) are stored in the respective delay circuits 44 and in the data supply circuit 52.

Then the second renewal of the coefficients is conducted according to Equations (21) and (22):

w.sub.02 (k)=w.sub.01 (k)+.mu.[T.sub.00 (k) w.sub.01 (k)+T.sub.01 (k) w.sub.11 (k)+I.sub.0 (k)] w.sub.12 (k)=w.sub.11 (k)+.mu.[T.sub.10 (k) w.sub.01 (k)+T.sub.11 (k) w.sub.11 (k)+I.sub.1 (k)].

For these computations the data supply circuit 52 will supply w.sub.11 (k) to the multipliers 40 of both arithmetic circuits S.sub.0 and S.sub.1, and the data supply circuits B.sub.0 and B.sub.1 will supply .mu.T.sub.00 (k) and .mu.T.sub.10 (k) to the respective multipliers 40. Then the adders 42 will add the resulting multiplier outputs, .mu.T.sub.00 (k) w.sub.01 (k) and .mu.T.sub.10 (k) w.sub.01 (k), to w.sub.01 (k) and w.sub.11 (K) that have been held in the respective delay circuits 44:

w.sub.01 (k)+.mu.T.sub.00 (k) w.sub.01 (k) w.sub.11 (k)+.mu.T.sub.10 (k) w.sub.01 (k).

The resulting outputs from the adders 42 will be held in the delay circuits 44. Then the data supply circuit will supply w.sub.11 (k) to both multipliers 40, and the data supply circuits B.sub.0 and B.sub.1 will supply .mu.T.sub.01 (k) and .mu.T.sub.11 (k) to the respective multipliers 40. Then the adders 42 will add the resulting multiplier outputs, .mu.T.sub.01 (k) w.sub.11 (k) and .mu.T.sub.11 (k) w.sub.11 (k), to the above values that have been held in the delay circuits 44:

w.sub.01 (k)+.mu.T.sub.00 (k) w.sub.01 (k)+.mu.T.sub.01 (k) w.sub.11 (k) w.sub.11 (k)+.mu.T.sub.10 (k) w.sub.01 (k)+.mu.T.sub.11 (k) w.sub.11 (k).

The resulting outputs from the adders 42 will be held in the delay circuits 44. Then the data supply circuit will supply the digit "1" to both multipliers 40, and the data supply circuits B.sub.0 and B.sub.1 will supply .mu.I.sub.0 (k) and .mu.I.sub.1 (k) to the respective multipliers 40. Then the adders 42 will add the resulting multiplier outputs, .mu.I.sub.0 (k) and .mu.I.sub.1 (k), to the delay circuit outputs:

w.sub.01 (k)+.mu.T.sub.00 (k) w.sub.01 (k)+.mu.T.sub.01 (k) w.sub.11 (k)+.mu.I.sub.0 (k) W.sub.11 (k)+.mu.T.sub.10 (k) w.sub.01 (k)+.mu.T.sub.11 (k) w.sub.11 (k)+.mu.I.sub.1 (k).

Now the second renewed coefficients w.sub.02 (K) and w.sub.12 (k) have been obtained in accordance with Equations (21) and (22). These renewed coefficients will be supplied to the respective multipliers A.sub.0 and A.sub.1 for use at the sampling time (k+1). Also, the second renewed coefficients will be held in the delay circuits 44 and further directed into the data supply circuit 52, for use as the initial coefficients to be renewed during the next sampling period from time (k+1) to time (k+2).

Despite the foregoing detailed disclosure, it is not desired that the present invention be limited by the exact details of such disclosure. For example, each arithmetic circuit could take a variety of forms other than that shown in FIGS. 9 and 10. Also, the data supply circuits B.sub.0 -B.sub.L associated with the respective arithmetic circuits S.sub.0 -S.sub.L could be combined into a single circuit. These and other modifications, alterations and adaptations of the invention may be resorted to without departure from the scope of the invention as expressed in the following claims.

Claims

1. An adaptive digital filter system of the type having first input means for inputting samples of a reference signal at predetermined sampling times, second input means for inputting at the predetermined sampling times samples of data which is associated with the reference signal, and a filter circuit for imparting a unit delay of one interval between the predetermined sampling times to the successive input data samples in order to concurrently obtain a set of (L+1) data samples of different sampling times, from 0'th to L'th, where L is an integer greater than one, for multiplying the set of data samples by respective coefficients W.sub.0 (k), W.sub.1 (k), . . . W.sub.L (k), and for adding together the set of multiplied data samples into a sum y(k), the filter circuit including a coefficient renewal circuit for renewing the coefficients for each set of input data samples by computing the following equations from a reference signal d(k) and set of (L+1) data samples at any one sample time K;

T.sub.ij (k)=-2x(k-i)x(k-j)

I.sub.i (k)=2d(k)x(k-i)

where

i and j=variables denoting the numbers from 0 to L

T.sub.ij (k)=(L+1).sup.2 values, including like values, used for the renewal of the coefficients

I.sub.j (k)=(L+1) values used for the renewal of the coefficients

x(k-i)=(L+1) data samples chosen successively from the set of data samples

x(k-j)=(L+1) data samples chosen successively from the set of data samples,

by renewing the set of (L+1) data samples n times, where n is an integer not less than two, during a time interval from the sampling time k to the next sample time (k+1) according to the equation: ##EQU19## where w.sub.i n-1(k)=(L+1) unrenewed coefficients to be renewed at each of the n renewals

w.sub.i n(k)=(L+1) renewed coefficients at each of the n renewals .mu.=stepsize constant

w.sub.j n-1(k)=(L+1) unrenewed coefficients to be renewed at each of then n renewals,

and by using the coefficients renewed at the last of the n renewals as coefficients by which a set of data samples obtained at the next sampling time (k+1) are to be multiplied, the adaptive digital filter system being characterized in that the coefficient renewal circuit comprises:

(a)first data supply means for supplying the (L+1) unrenewed coefficients w.sub.i n-1(k) to be renewed at each of the n renewals and an unit value;

(b) second data supply means connected to the first and the second input means for supplying the products .mu.T.sub.ij (k) of T.sub.ij (k) and .mu., and the products .mu.I.sub.i (k) of I.sub.i (k) and .mu.; and

(c) (L+1) arithmetic circuits each having inputs connected to the first and the second data supply means and an output connected to the first data supply means, the arithmetic circuits simultaneously conducting the n renewals of the set of (L+1) data samples and putting out the coefficients renewed at the last of the n renewals;

wherein each arithmetic circuit comprises:

(a) a multiplier having a first input connected to the first data supply means and a second input connected to the second data supply means;

(b) an adder connected between the multiplier and the output of the arithmetic circuit; and

(c) a delay circuit connected to the adder for delaying an output from the adder by one interval between the predetermined sampling times for application to the adder.