Patent Application
20090207955
The present invention relates to an adaptive digital filter, and more particularly, to an adaptive digital filter, an FM receiver, a signal processing method, and a program that is executed on a computer, and that are suitable for a multipath equalizer of an FM (Frequency Modulation) receiver.
FM modulated waves used in FM radio broadcasting and television broadcasting are signals in which a sine wave carrier signal is subjected to phase modulation by a music signal. FM modulated waves have high resistance against noise and can transmit music signals having a wide band of 15 kHz with a low distortion factor. However, in multipath propagation paths, which include paths other than the path by which a radio waves arrive directly and in which radio waves are reflected by obstructions such as buildings and thus arrive with a delay, the phase information required for demodulation is disturbed by the influence of strong reflected waves that are received together with direct waves, and distortion therefore occurs in the demodulated signal. This distortion that is produced as a result of multipath propagation paths is referred to as “multipath distortion.” An equalizer for reducing multipath distortion by compensating for the characteristics of multipath propagation paths is referred to as a “multipath equalizer” or a “multipath distortion canceller.”
A multipath equalizer compensates for the effect of multipaths in a received signal by passing the received signal through a filter having the inverse characteristics of the multipath propagation paths, i.e., an inverse filter. The characteristics of the multipath propagation paths change according to the environment, and the characteristics of the inverse filter therefore must also be optimized according to the conditions over time. As a result, adaptive digital filters are typically used as inverse filters.
An adaptive digital filter is a filter having the capability for automatically updating the filter coefficient according to changes in the environment. An algorithm for calculating filter coefficients at each point in time is referred to as an “adaptive algorithm,” an LMS (Least Mean Square) algorithm being a representative example. In a broad sense, an LMS algorithm is a method of minimizing the mean-square error based on a steepest-descent method and offers the advantages of stability and a small amount of operations. Adaptive algorithms known as “complex LMS algorithms” are also known. A complex LMS algorithm is an extension of the LMS algorithm in which each of the input signal, output signal, target signal, and filter coefficients are complex amounts, and is used, for example, by separating the in-phase component and quadrature component and realizing adaptation when the input is a narrow-band high-frequency signal.
On the other hand, a conventional equalizer that is realized using an adaptive digital filter requires a reference signal (training signal) for this adaptation, and this requirement tends to cause a reduction of communication efficiency due to interruptions in communication and redundant reference signals. In contrast, a recently developed equalizer known as the “blind equalizer” performs restorative equalization of signals based only on the received signals without requiring a reference signal for adaptation. An algorithm for application in this type of blind equalization is called a “blind algorithm,” a CMA (Constant Modulus Algorithm) being a representative example. One example of a CMA is disclosed in C. Richard Johnson, Jr., Philip Schniter, Thomas J. Endres, James D. Behm, Donald R. Brown, and Raul A. Casas, “Blind Equalization Using the Constant Modulus Criterion: A Review” (Proceedings of IEEE, Vol. 86, No. 10, October 1998) (hereinbelow referred to as “Non-Patent Document 1”).
As shown in Non-Patent Document 1, CMA typically refers to an algorithm that takes as an index a statistic relating to the output signal such as the envelope of the filter output or a higher-order statistic and that updates filter coefficients such that this index approaches a target value. An example of using a constant-amplitude modulated wave in which the amplitude of the modulated wave is fixed, as in FM modulation, is disclosed in: J. R. Treichler and B. G. Agee, “A New Approach to Multipath Correction of Constant Modulus Signals” (IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 31, No. 2, pp. 459-472, April 1983) (Hereinbelow referred to as “Non-Patent Document 2”). As shown in Non-Patent Document 2, when using a constant-amplitude modulated wave, the envelope of the filter output, i.e., the amplitude, is used as the index, and the filter coefficient is updated to minimize the error between a target value and the value of the envelope of the signal following passage through the filter. In this way, distortion of phase is corrected together with the distortion of the envelope, and the influence of the reflected waves of multipath propagation paths is eliminated. Here, CMA is a different concept than an adaptive algorithm. In CMA, an adaptive algorithm such as the previously mentioned LMS algorithm is used as an adaptive algorithm for calculating filter coefficients at each time point.
In order to control the value of the envelope of the output signal of a filter to a uniform value as described above, the value of the envelope must be extracted instantaneously, and complex signal processing is a representative method of this type of extraction. In complex signal processing, a real signal f2 having phase that is delayed 90° (π/2) with respect to a particular real signal f1 is generated by, for example, a Hilbert transformer, whereby a complex signal (typically referred to as an “analytic signal”) having f1 as a real part and f2 as an imaginary part is generated. In this way, the value of the envelope of this real signal can be found instantaneously by calculating the square sum of the real part and imaginary part of the complex signal. However, when the output signal of the filter is subjected to complex signal processing, delay caused by the complex signal processing enters into the coefficient update loop and gives rise to instability of the loop. As a result, the complex signal processing is carried out upon the input signal. In this case, the input signal becomes a complex signal, and an algorithm that can handle complex quantities such as a complex LMS algorithm is therefore used as the adaptive algorithm. This method is referred to as the “first technique of the related art.”
W(k+1)=W(k)−μ(|y(k)|p−yref0)qy(k)XH(k) (1)
y(k)=WT(k)X(k) (2)
W(k)=[w0(k),w1(k), . . . , wN-1(k)]T (3)
X(k)=[x(k),x(k−1), . . . , x(k−N+1)]T (4)
where W(k) represents a filter coefficient vector, X(k) represents a complex signal vector, k represents a sample index, and N represents the number of filter taps. Further, y(k) represents the output signal, yref0 represents the envelope target value, and μ represents a parameter for determining the amount of updating of the filter coefficients. In addition, H represents a complex conjugate transposition, and T represents a transposition. The values p and q are constants for determining an evaluation function of error for the envelope target value, and for example, may be p=1 and q=1.
In the first technique of the related art, two signals having phases shifted 90° (π/2) with respect to each other are generated by applying complex signal processing. However, as can be seen from the document JP-A-2005-064618 (Hereinbelow referred to as “Patent Document 1”) and Itami Makoto, Hatori Mitsutoshi, Tsukamoto Norio, “Hardware Implementation of FM Multipath Distortion Canceller” (National Convention Record of the Institute of Television Engineers of Japan, pp. 355-356, 1986) (hereinbelow referred to as “Non-Patent Document 3”), if sampling is carried out at a frequency of (4/odd number) times the carrier frequency when sampling the input signal, the phases of adjacent sample points will be shifted 90°. By taking this approach, an adaptive algorithm for handling real numbers can be used as is, whereby the square sum of adjacent sample points can be calculated when seeking the value of the envelope of the output signal. This method is referred to as the “second technique of the related art.”
Wr(k+1)=Wr(k)−μ(Env[yr(k)]−yref0)yr(k)Xr(k) (5)
yr(k)=WrT(k)Xr(k) (6)
Env[yr(k)]=(yr2(k−1)+yr2(k))1/2 (7)
Wr(k)=Re[W(k)] (8)
Xr(k)=Re[X(k)] (9)
where Wr(k) represents a real coefficient vector, Xr(k) represents a real signal vector, Env[ ] represents an operation for obtaining an approximate value of an envelope, Re[ ] represents an operation for taking the real part of the complex number, and yr(k) represents a real-number output signal.
Drawbacks of a conventional adaptive digital filter include the large amount of operations and the necessity for large-scale hardware, the reasons for these requirements being as follows:
The first reason for these requirements is the large number of bits of filter coefficients. An adaptive digital filter requires both memory units (delay units) for saving the current value of each filter coefficient and multipliers that take each of the filter coefficients as multiplicands equal in number to the number of filter coefficients (the tap number), resulting in a large amount of hardware overall even when the number of bits for one filter coefficient is small. Operations for numbers having many bits result in further increases in the amount of operations.
The second reason for the need for a large amount of hardware is the complex signal processing. Essentially, nearly all signal processing for input signal X(k), filter coefficient W(k), and output signal y(k) in the adaptive digital filter shown in
In the adaptive digital filter shown in
The present invention was proposed in view of these circumstances and therefore has as its object the provision of an adaptive digital filter, an FM receiver, a signal processing method, and a program that can be executed on a computer that are capable of reducing the amount of operations and the amount of hardware.
The adaptive digital filter of the present invention for achieving the above-described object is of a configuration that includes:
a filter unit that includes a plurality of multipliers divided into groups of at least one multiplier and other multipliers based on expected values of filter coefficients, for generating first signals by means of convolution operations of an input signal and filter coefficients; an adder for adding the input signal that is applied as input to at least one multiplier and the first signals to supply second signals as output; and a coefficient control unit for controlling the filter coefficients based on error between a target signal and an index value derived from the second signals.
According to the present invention, the division into groups causes a difference in filter coefficients between at least one multiplier and the other multipliers. The input signal applied as input to this one multiplier, if left unchanged, is equivalent to the value obtained by multiplying at the multiplier of filter coefficient 1, and implementing control to extract this input signal to add to the first signal that is the output of the filter unit to generate a second signal and implementing control to decrease the filter coefficient of the above-described multiplier based on error between a target signal and an index value such that the amount of the above-described input signal is not included in the multiplication result in the above-described multiplier suppresses variation of filter coefficients in the filter unit to a smaller value than in the related art. As a result, the number of bits required for multipliers for the convolution operations and delay units for holding filter coefficients can be reduced, the amount of operations can be decreased, and the amount of hardware can be cut.
In addition, the adaptive digital filter of the present invention is of a configuration that includes: a filter unit that includes a plurality of multipliers for carrying out convolution operations of an input signal and filter coefficients and that enlarges by a prescribed magnification the output of at least one multiplier of the plurality of multipliers and generating the results of the convolution operations as first signals; and a coefficient control unit for controlling the filter coefficients used in the plurality of multipliers based on error between a target signal and an index value derived from the first signals and for reducing, by the prescribed magnification, a signal that depends on error that is the basis for generation of filter coefficients that are used in the multipliers in which output is enlarged at a prescribed magnification.
According to the present invention, the output signal of at least one multiplier among multipliers for the convolution operations is enlarged, and the signal that accords with the error that serves as the basis for generation of filter coefficients used in the multipliers is reduced by a proportion that matches that of the enlargement, whereby the filter coefficients required by multipliers for the convolution operations can be values that are substantially smaller than in the related art. As a result, the number of bits required for multipliers for the convolution operations and delay units for holding filter coefficients can be decreased, the amount of operations can be reduced, and the amount of hardware can be cut.
Still further, the FM receiver of the present invention for achieving the above-described object is of a configuration that includes: an adaptive digital filter according to the present invention as described above; and a Hilbert transformer for applying as input to the adaptive digital filter a complex signal generated by subjecting an FM modulated signal that has been converted to an intermediate frequency and digitized to a Hilbert transformation.
As described in the foregoing explanation, the amount of signal processing operations for realizing an adaptive digital filter can be reduced in the present invention. This reduction can be achieved because the filter coefficients used in the multipliers for the convolution operations can be values that are substantially smaller than in the related art.
105 Hilbert transformer
303 step-size generation circuit
305 envelope-target-value generation circuit
307 subtractor
308 absolute-value circuit
309 real-part extraction circuit
310, 311 multipliers
318 common unit
319
0-319N-1 separate units
330
1-330N-1 delay units
331
0-331N-1 multipliers
341
0-341N-1 multipliers
333
0-333N-1 adders
343
0-343N-1 adders
334
0-334N-1 delay units
344
0-344N-1 delay units
335
0-335N-1 real-part extraction circuits
336
0-336N-1 multipliers
337
1-337N-1 adders
338 adder
349 branch line
339
1-339N-1 delay units
340
0-340N-1 complex conjugate unit
Explanation next regards the configuration of an adaptive digital filter of an exemplary embodiment of the present invention.
Referring to
The filter unit is provided with: an FIR (Finite Impulse Response) filter for which the tap number, i.e., the number of filter coefficients, is N and that includes a tapped delay line composed of N−1 delay units 3301-330N-1 that each give a delay of one sampling cycle, N multipliers 3360-336N-1 for multiplying the complex input signal and the output signal of each of delay units 3301-330N-1 by a filter coefficient, and N−1 adders 3371-337N-1 for successively adding the multiplication results of these N multipliers 3360-336N-1; branch line 349 for extracting the output signal of delay unit 330M-1; and adder 338 for adding the output signal of the FIR filter, i.e., the output signal of adder 337N-1, and the signal extracted at branch line 349 and transmitting this result to output terminal 302.
A configuration that includes delay unit 330S (where S is any positive integer of at least 1 but no greater than (N−1)), multiplier 336S, and adder 337S is a basic element of a filter and is referred to as a “tap.” In addition, the tap that includes delay unit 330M-1, multiplier 336M-1, and adder 337M-1 is referred to as the “center tap.” Here, M is a positive integer equal to or greater than 1.
The case next described is one example of a method of determining the initial value of each filter coefficient. In the case of multipath propagation, the filter coefficients of the filter unit are all set to the same value before activation of the adaptive digital filter, and each filter coefficient changes when the adaptive digital filter is activated. After convergence, the expected values of the filter coefficients in each tap are found. The initial value of each filter coefficient is then set in accordance with the expected values that have been found. In particular, when not a case of multipath propagation, i.e., when there are only directly propagated waves, the expected values of filter coefficients are obtained without bringing about convergence, the taps are classified as one tap in which the expected value of the filter coefficient is “1” and the other taps in which the expected values are “0,” and these expected values then set as the initial values.
In the present exemplary embodiment, the initial value of the filter coefficient of the center tap is set to a higher value than the other taps.
Taps can be classified into a plurality of groups depending on whether the filter coefficient is at least a reference value or less than the reference value based on the expected values of filter coefficients. According to the method of classification, the filter coefficient of the center tap is greater than that of the other taps, and the taps are thus grouped into the center tap and the other taps. The reference value may be set to, for example, “1.0.”
The signal extracted by branch line 349 is a signal obtained by subjecting the input signal of input terminal 301 to (M−1) sampling delays, and this signal is the signal supplied as output from delay unit 330M-1 of the center tap. In other words, this signal corresponds to the output signal of the delay unit of the tap for which the initial value of the filter coefficient is greater than in other taps. Accordingly, the signal of the center tap is directly extracted and separately added in adder 338 in the present exemplary embodiment.
In addition, the coefficient control unit is of a configuration that uses LMS as an adaptive algorithm and that includes common unit 318 that is common to the control of all filter coefficients and separate units 3190-319N-1 for the separate control of each individual filter coefficient.
Common unit 318 is of a configuration that includes: absolute-value circuit 308 for, upon the input of the complex output signal that is the output of the filter unit, calculating the value of the envelope of the complex output signal by the square sum of the real part and imaginary part to supply as output; envelope-target-value generation circuit 305 for generating the value with which the envelope is to converge, i.e., the envelope target value; subtractor 307 for supplying as output a value obtained by subtracting the envelope target value from the value of the envelope that was found in absolute-value circuit 308; real-part extraction circuit 309 for, upon input of the complex output signal, extracting only the real part of this signal to supply as output; multiplier 310 for supplying as output the result of multiplying the output of subtractor 307 and the output of real-part extraction circuit 309; step-size generation circuit 303 for generating a step size that is a parameter for determining the update amount of a filter coefficient; and multiplier 311 for supplying as output to each of separate units 3190-319N-1 the result of multiplying the output of multiplier 310 and the step size.
In the case of the present exemplary embodiment, the filter coefficients are real numbers and not complex numbers, and the step size generated at step-size generation circuit 303 is therefore set to approximately four times the step size when using complex filter coefficients, whereby the speed of convergence can be made equivalent to a case of using complex filter coefficients.
Separate units 3190-319N-1 are each of a configuration that includes: real-part extraction circuits 3350-335N-1 for, upon input of the complex input signal or the output signal of corresponding delay units 3301-331N-1 on the tapped delay line, extracting only the real part of the complex signal and supplying this real part as output; multipliers 3310-331N-1 for supplying as output the results of multiplying a signal received as input from common unit 318 and the real parts extracted at real-part extraction circuits 3350-335N-1; adders 3330-333N-1 for adding the filter coefficients that have been given to multipliers 3360-336N-1 and the outputs of multipliers 3310-331N-1 and supplying as output the filter coefficients that are to be used in the next sampling cycle; and delay units 3340-334N-1 for delaying the outputs of these adders 3330-333N-1 by exactly one sampling cycle and supplying as output to multipliers 3360-336N-1.
The algorithm of the adaptive digital filter of the present exemplary embodiment is represented as shown below:
Wr(k+1)=Wr(k)−μ(|y(k)|p−yref0)qRe[y(k)]Re[X(k)] (10)
y(k)=WrT(k)X(k)+X(M−1) (11)
where Wr(k) represents a real coefficient vector, X(k) represents a complex signal vector, and Re[ ] represents the operation of extracting the real part of a complex number. In addition, y(k) is the complex output signal, k represents the sampling index, N represents the number of filter taps, yref0 is the envelope target value, μ is a parameter for determining the update amount of a filter coefficient, and X(M−1) is a signal extracted by branch line 349. The values p and q are constants for determining the evaluation function of the error for the envelope target value, and may be set to, for example, p=1 and q=1.
Explanation next regards the operation of the adaptive digital filter of the present exemplary embodiment.
First, regarding adaptive equalizing process S2, the complex input signal that is received as input at input terminal 301 is supplied to multiplier 3360 and real-part extraction circuit 3350, and at the same time, supplied to the tapped delay line that is composed of delay units 3301-330N-1 that generate delays of one sampling cycle. The complex signal supplied to delay units 3301-330N-1 is transmitted to an adjacent delay unit with each clock, and the output signals of each of delay units 3301-330N-1 are supplied to corresponding multipliers 3361-336N-1 and corresponding real-part extraction circuits 3351-335N-1. In addition, the output signal of delay unit 330M-1 is extracted by branch line 349 and supplied to adder 338.
In multiplier 3360, the real-number filter coefficient supplied from delay unit 3340 is multiplied by the complex signal received as input from input terminal 301 and the result is supplied to adder 3371. In multipliers 3361-336N-1, the real-number filter coefficients supplied from corresponding delay units 3341-334N-1 are multiplied by the complex signals supplied from delay unit 3301-330N-1 and the results are supplied to adders 3371-337N-1. Adders 3371-337N-1 add all complex signals received from multipliers 3360-336N-1 and supply the result to adder 338.
In adder 338, the signal supplied from adder 337N-1 and the signal extracted by branch line 349 are added, the result is supplied to output terminal 302, and at the same time, supplied to absolute-value circuit 308 and real-part extraction circuit 309. In this way, a complex signal is generated and supplied that is obtained by adding the complex signal extracted from the center tap and the complex signal that is generated by the convolution operation of the complex input signal and a filter coefficient that is a real signal.
Next, regarding parameter update process S4, absolute-value circuit 308 receives the complex output signal, calculates the absolute value of this signal and transmits this result as the value of the envelope to subtractor 307. Envelope-target-value generation circuit 305 generates an envelope target value and transmits this value to subtractor 307. Subtractor 307 subtracts the envelope target value received from envelope-target-value generation circuit 305 from the signal received from absolute-value circuit 308 and transmits the result to multiplier 310. Real-part extraction circuit 309 receives the complex output signal, extracts only the real part from this signal, and transmits this result to multiplier 310. Multiplier 310 multiplies the signal received from real-part extraction circuit 309 by the signal received from subtractor 307 and transmits the result to multiplier 311. Step-size generation circuit 303 generates a step size, which is a parameter for determining the amount of updating of filter coefficients in the filter unit and supplies the step size to multiplier 311. Multiplier 311 multiplies the step size supplied from step-size generation circuit 303 by the signal received from multiplier 310 and supplies the result to each of separate units 3190-319N-1.
In each of separate units 3190-319N-1, the signal supplied from multiplier 311 is transmitted to multipliers 3310-331N-1. Real-part extraction circuits 3350-335N-1 each extract the real part of the complex signal supplied from input terminal 301 or corresponding delay units 3301-330N-1 and transmit the extracted real part to corresponding multipliers 3310-331N-1. Multipliers 3310-331N-1 multiply the real-number signal supplied from common unit 318 by the real-number signal supplied from corresponding real-part extraction units 3350-335N-1, respectively, and transmit the results to corresponding adders 3330-333N-1. Adders 3330-333N-1 add the real-number filter coefficients supplied from corresponding delay units 3340-334N-1 to the real-number signals received from corresponding multipliers 3310-331N-1, respectively, and transmit the results as the filter coefficients to be used in the next sample to corresponding delay units 3340-334N-1. Delay units 3340-334N-1 delay the real-number filter coefficients received from corresponding adders 3330-333N-1 by one sample and both supply the results to corresponding multipliers 3360-336N-1 and transmit the results to corresponding adders 3330-333N-1, respectively.
Explanation next regards the effects of the present exemplary embodiment.
Assuming the multipath propagation path H(z) as:
H(z)=1+a·z−10 (12)
where a=0.675, a simulation is now considered in which multipath distortion is eliminated using G0(z)=z−25 as the initial value of equalizing filter G(z). In this multipath propagation path, reflected waves arrive with a 10-sample delay compared to direct waves, and filter G(z) for equalizing H(z) therefore is ideally as follows:
In other words, a filter coefficient that is not 0 appears with each tenth filter coefficient, with the 25th filter coefficient (tap coefficient) being “1,” the 35th filter coefficient being “−a,” the 45th filter coefficient being “+a2,” and so on, and all other filter coefficients being “0.” In actuality, however, the ideal pattern is not realized, and simulation results such as shown in
Referring to
Here, in a configuration in which branch line 349 and adder 338 are removed from the configuration of
X(M−1)·(1+Δh)=X(M−1)+X(M−1)·Δh (14)
On the other hand, if Δh is a value obtained by subtracting “1” from the filter coefficient saved in delay unit 334M-1 of the center tap in the configuration of
In the adaptive digital filter of the present exemplary embodiment, if multipliers 3360-336N-1 are grouped based on filter coefficients, multiplier 336M-1 can be said to have a filter coefficient that differs from other multipliers. The input signal that is applied as input to this multiplier 336M-1, if unchanged, is equivalent to a value obtained by multiplying filter coefficient 1 by a multiplier, and if this input signal is extracted by the branch line and added to the output signal of the filter unit to generate a complex output signal, and further, if control is implemented to decrease the filter coefficient of multiplier 336M-1 based on the error between the index value and the target signal such that the above-described input signal portion is not included in the multiplication result in multiplier 336M-1, the variation of filter coefficients within the filter unit can be suppressed to a smaller value than in the related art.
In the present exemplary embodiment, the filter coefficient of multiplier 336M-1 is larger than in other multipliers. The input signal applied as input to multiplier 336M-1, if unchanged, is equivalent to a value obtained by multiplying filter coefficient 1 in a multiplier, and this input signal is extracted by branch line 349 and added to the output signal of the filter unit in adder 338 to generate a complex output signal. Control is then implemented to decrease the filter coefficient of multiplier 336M-1 based on the error between the index value and target signal such that the above-described input signal portion is not included in the multiplication results in multiplier 336M-1. As a result, the filter coefficient of multiplier 336M-1 is a substantially smaller value than the initial value. Accordingly, the number of bits required for multipliers for convolution operations and delay units for holding filter coefficients can be reduced, and the amount of operations and hardware can be decreased.
Further, as can be seen by referring to
Accordingly, replacing points at which multiplication is carried out between complex numbers in the first technique of the related art with multipliers 3360-336N-1 that carry out multiplication between complex numbers and real numbers realizes a decrease equivalent to N multiplications between real numbers. Replacing points at which multiplication is carried out between complex numbers in the first technique of the related art with multipliers 3310-331N-1 that carry out multiplication between real numbers further realizes a decrease equivalent to 3N multiplications between real numbers and 2N additions of real numbers. Still further, the portion of real-part extraction circuits 3350-335N-1 required a complex conjugation unit in the first technique of the related art, and the amount of operations is reduced to the degree that code of imaginary parts is not transmitted.
As described in the foregoing explanation, the amount of operations in the present exemplary embodiment can be cut to approximately 40% of the first technique of the related art.
Still further, the output signal of the filter unit is obtained as a complex number in the present exemplary embodiment, and as a result, the value of the envelope of the output signal, i.e., the amplitude, is obtained both instantaneously and accurately as the output signal of absolute-value circuit 308 of
Explanation next regards the adaptive digital filter according to the second exemplary embodiment of the present invention using the block diagram of
Referring to
In the present exemplary embodiment, M−1 delay units 3391-339M-1 are newly required, but the signal transmitted by branch line 349 to adder 338 is the same as in the first exemplary embodiment and the same effect can therefore be obtained as in the first exemplary embodiment.
Explanation next regards the adaptive digital filter according to the third exemplary embodiment of the present invention using the block diagram of
Referring to
The filter unit is provided with: an FIR filter in which the number of taps, i.e., the number of filter coefficients, is N and that includes a tapped delay line composed of N−1 delay units 3301-330N-1 that each give delay of one sampling cycle, N multipliers 3460-346N-1 for multiplying filter coefficients by each of the complex input signal and the output signals of each of delay units 3301-330N-1, and N−1 adders 3371-337N-1 for successively adding the multiplication results of these N multipliers 3460-346N-1; branch line 349 for extracting the output signal of delay unit 330M-1; and adder 338 for adding the output signal of the FIR filter, i.e., the output signal of adder 337N-1 and the signal extracted by branch line 349 and transmitting the result to output terminal 302.
Here, the signal extracted by branch line 349 is a signal in which the input signal of input terminal 301 is delayed by (M−1) samples, this signal being the signal supplied from delay unit 330M-1 that is the center tap. In other words, this signal corresponds to the output signal of the delay unit in the tap in which the initial value of the filter coefficient is larger than that of other taps. Thus, in the present exemplary embodiment, the signal of the center tap is directly extracted and separately added at adder 338.
The coefficient control unit uses a complex LMS that is extended to handle complex numbers as its adaptive algorithm, and is of a configuration that includes common unit 318 that is common to control of all filter coefficient and separate units 3190-319N-1 for the control of each individual filter coefficient.
Common unit 318 is of a configuration that includes: envelope-target-value generation circuit 305 for generating an envelope target value; absolute-value circuit 308 for, upon input of a complex output signal that is the output of the filter unit, calculating the value of the envelope of the complex output signal by means of the square sum of the real part and the imaginary part; subtractor 307 for supplying as output a value obtained by subtracting the envelope target value from the value of the envelope found in absolute-value circuit 308; multiplier 181 for supplying as output the result of multiplying the output of subtractor 307 and the complex output signal; step-size generation circuit 303 for generating a step size, which is a parameter for determining the amount of update of filter coefficients; and multiplier 182 for supplying as output to each of separate units 3190-319N-1 the result of multiplying the output of multiplier 181 and the step size.
Separate units 3190-319N-1 are each of a configuration that includes: complex conjugate units 3400-340N-1 for, upon input of the complex input signal or the output signal of corresponding delay units 3301-330N-1 on a tapped delay line, subjecting the complex signal to a complex conjugate conversion and supplying the result as output; multipliers 3410-341N-1 for supplying the result of multiplication of the signal received as input from common unit 318 and the complex signal supplied from complex conjugation units 3400-340N-1; adders 3430-343N-1 for adding the filter coefficients given to multipliers 3460-346N-1 and the outputs of multipliers 3410-341N-1 and supplying the results as the filter coefficients to be used in the next sampling cycle; and delay units 3440-344N-1 for delaying the outputs of these adders 3430-343N-1 by exactly one sampling cycle and supplying the result to multipliers 3460-346N-1.
The algorithm of the adaptive digital filter of the present exemplary embodiment is represented as follows:
W(k+1)=W(k)−μ(|y(k)|p−yref(k))qy(k)XH(k) (15)
y(k)=WT(k)X(k)+X(M−1) (16)
W(k)=[w0(k),w1(k), . . . , wN-1(k)]T (17)
X(k)=[x(k),x(k−1), . . . , x(k−N+1)]T (18)
yref(k)=Av[|x(k)|] (19)
Av[|x(k)|]=(1−β)Av[|x(k−1)|]+β|x(k)| (20)
where W(k) represents a filter coefficient vector, X(k) represents a complex signal vector, k represents a sampling index, and N represents the filter tap number. In addition, y(k) is an output signal, yref is the time-variant envelope target value, μ is a parameter for determining the amount of update of a filter coefficient, X(M−1) is a signal extracted by branch line 349, Av[ ] represents the operation of averaging, and β is a weighting coefficient that is a positive constant satisfying the relation 0<β<1. In addition, H represents a complex conjugate transposition, and T represents a transposition. The values p and q are constants for determining an evaluation function of the error with respect to the envelope target value, these values being, for example, p=1 and q=1.
Explanation next regards the operation of the adaptive digital filter of the present exemplary embodiment.
The adaptive digital filter of the present exemplary embodiment repeats the processes from adaptive equalizing process S2 to parameter updating process S4 shown in
First, regarding adaptive equalizing process S2, the complex input signal applied as input to input terminal 301 is supplied to multiplier 3460 and complex conjugation unit 3400, and at the same time, is supplied to the tapped delay line composed of delay units 3301-330N-1 for generating delays of one sampling cycle. The complex signal supplied to delay units 3301-330N-1 is transmitted to an adjacent delay unit with each clock, and the output signals of each of delay units 3301-330N-1 are supplied to corresponding multipliers 3461-346N-1 and corresponding complex conjugation units 3401-340N-1. In addition, the output signal of delay unit 330M-1 is extracted by branch line 349 and supplied to adder 338.
In multiplier 3460, a complex filter coefficient supplied from delay unit 3440 is multiplied by the complex signal received as input from input terminal 301 and the result is supplied to adder 3371. In multipliers 3461-346N-1, the complex filter coefficients supplied from corresponding delay units 3441-344N-1 are multiplied by the complex signals supplied from corresponding delay units 3301-330N-1 and the results are supplied to adders 3371-337N-1. Adders 3371-337N-1 add all complex signals received from multipliers 3460-346N-1 and supply the results to adder 338.
In adder 338, the signal supplied from adder 337N-1 is added to the signal extracted by branch line 349, the result is supplied to output terminal 302, and at the same time, supplied to absolute-value circuit 308 and multiplier 181. In this way, the complex signal that is generated by the convolution operation of the complex input signal and a complex filter coefficient and the complex signal extracted from the center tap are added to generate and supply a complex signal.
Next, regarding parameter updating process S4, envelope-target-value generation circuit 305 generates an envelope target value and supplies the value to subtractor 307. On the other hand, absolute-value circuit 308 receives the complex output signal, calculates the absolute value of this value, and transmits the result as the value of the envelope to subtractor 307. Subtractor 307 subtracts the envelope target value received from envelope target value generation unit 305 from the signal received from absolute-value circuit 308 and transmits the result to multiplier 181. multiplier 181 multiplies the complex output signal by the signal received from subtractor 307 and transmits the result to multiplier 182. Step-size generation circuit 303 generates a step size, which is a parameter for determining the amount of filter coefficient updating in the filter unit and supplies this step size to multiplier 182. Multiplier 182 multiplies the step size received from step-size generation circuit 303 by the signal received from multiplier 181 and transmits the result to each of separate units 3190-319N-1.
In each of separate units 3190-319N-1, the signal supplied from multiplier 182 is transmitted to multipliers 3410-341N-1. Complex conjugation units 3400-340N-1 each subject the complex signal supplied from corresponding delay units 3301-330N-1 or from input terminal 301 to a complex conjugation conversion and transmit the results to corresponding multipliers 3410-341N-1. Multipliers 3410-341N-1 each multiply the complex signals supplied from common unit 318 with the real-number signals supplied from corresponding complex conjugation units 3400-340N-1 and transmit the results to corresponding adders 3430-343N-1. Adders 3430-343N-1 each add the complex filter coefficients supplied from corresponding delay units 3440-344N-1 to complex signals received from corresponding multipliers 3410-341N-1 and transmit the results to corresponding delay units 3440-344N-1 as the filter coefficients for the next sample. Delay units 3440-344N-1 each delay by one sample the complex filter coefficients received from corresponding adders 3430-343N-1 and both supply to corresponding multipliers 3460-346N-1 and transmit to corresponding adders 3430-343N-1.
Explanation next regards the effect of the present exemplary embodiment.
In the present exemplary embodiment as well, all filter coefficients including the center tap can be limited to a small value, whereby the amount of hardware and the amount of operations of delay units 3440-344N-1, adders 3430-343N-1, and multipliers 3460-346N-1 can be reduced.
In the present exemplary embodiment, the output signal of the filter unit is obtained as a complex number, and the value of the envelope of the output signal, i.e., the amplitude, is therefore obtained instantaneously and accurately as the output signal of absolute-value circuit 308 of
Explanation next regards the adaptive digital filter according to the fourth exemplary embodiment of the present invention using the block diagram of
Referring to
The present exemplary embodiment requires an additional M−1 delay units 3391-339M-1, but the signal that is transmitted to adder 338 by branch line 349 is the same as in the third exemplary embodiment and the same effect as the third exemplary embodiment is therefore obtained.
Explanation next regards the adaptive digital filter according to the fifth exemplary embodiment of the present invention using the block diagram of
Referring to
The operation of the present exemplary embodiment is next described briefly.
As shown in by the simulation results of
Thus, according to the present exemplary embodiment, the equivalent operation is carried out even when the filter coefficient applied to multiplier 336M-1 of the center tap is made small. As seen in the simulation results of
In the adaptive digital filter of the present exemplary embodiment, the output signal of at least one multiplier of the multipliers for the convolution operations is enlarged, and the signal that depends on the error that serves as the basis for generating the filter coefficient used in this multiplier is reduced to a degree that corresponds to the enlargement, whereby the filter coefficients required in the multipliers for the convolution operations can be made substantially smaller than the related art. As a result, the number of bits required for multipliers for the convolution operation and the delay units for holding the filter coefficients can be decreased, and the amount of operations and amount of hardware can be cut back.
Explanation next regards the adaptive digital filter according to the sixth exemplary embodiment of the present invention using the block diagram of
Referring to
The present exemplary embodiment is a form in which a modification similar to that of the fifth exemplary embodiment is added to the third exemplary embodiment that handles complex filter coefficients and therefore has the effect of enabling a reduction of the amount of operations and the amount of hardware compared to the adaptive digital filter according to the first technique of the related art.
In the above-described first to sixth exemplary embodiments, exemplary embodiments were described that are suitable for cases in which there is one tap in which the filter coefficient becomes greater following convergence, but in cases in which two or more taps are known to exist in which the filter coefficients become greater following convergence, a configuration similar to each of the above-described exemplary embodiments may be added for each of these taps.
For example, when, in addition to the tap that corresponds to the output point of delay unit 330M-1, the filter coefficient of the tap corresponding to the output point of delay unit 330J-1 is greater than “1,” the output signal of delay unit 330J-1 in the exemplary embodiments of
In the exemplary embodiments of
Still further, in the exemplary embodiments of
In addition, filter coefficient groups can be classified in groups according to the expected values of filter coefficients and then processed in group units as in the seventh exemplary embodiment described hereinbelow.
Explanation next regards the adaptive digital filter according to the seventh exemplary embodiment of the present invention using the block diagram of
Referring to
Common unit 318 is the same as the component in the adaptive digital filter according to the first exemplary embodiment shown in
Explanation next regards the configuration of group processors 33100-3310L-1.
Referring to
Explanation next regards the configuration of separate processors 33120-3312M-1.
Referring to
Multiplier 336i multiplies the complex input signal or the output signals of corresponding delay units 3301-330N-1 on the tapped delay line with the filter coefficient from delay unit 334i and supplies the result to adder 3314 shown in
Explanation next regards the operation of the present exemplary embodiment. An example is here described in which L=2, i.e., in which filter coefficients are divided into two groups. It is now assumed that the distribution of the values of the filter coefficients of each tap after convergence is divided into the two groups: Group 0 in which filter coefficients belong to the range of at least “1” but less than “1.5” and Group 1 in which filter coefficients belong to the range of less than “0.5.” Tapped delay line and group processors 33100 and 33101 are connected in advance such that, of the tap signals, tap signals that belong to Group 0 are applied as input to group processor 33100, and tap signals that belong to Group 1 are applied as input to group processor 33101.
In group processor 33100, constant C that is multiplied by multiplier 3311 of
In group processor 33101, on the other hand, the value of the filter coefficients after convergence are 0.5 or less, and constant C can therefore be set to “1” and handled as in the sixth exemplary embodiment. However, if, for example, the values of filter coefficients after convergence are small, the values of the multiplication results of multiplier 331i or multiplier 336i are consequently also small, and fixed-decimal-point operations result in the elimination of the lower-ranked digits and a consequent degradation of the operational accuracy, then multiplication by a constant C that produces larger filter coefficients is also possible. For example, the calculation “0.1·0.2” results in “0.02,” but this result will be “0” if values can be expressed only as far as the first decimal-point digit in a separate processor. If multiplication is here carried out with C=10, the calculation “0.1·10=1.0” and the multiplication of this result with “0.2” produces “0.2,” which can be expressed. The result is here increased by a multiple of 10, but multiplication by the reciprocal of C in multiplier 3313 allows the result to be treated as “0.02” following multiplier 3313.
Although the foregoing explanation regards an example in which filter coefficients are divided into two groups, a case in which the filter coefficients are divided into three or more groups is similar.
The present exemplary embodiment is premised on the exemplary embodiment described in
Using
Referring to
FM modulated waves received at antenna 101 are converted to a signal of an intermediate frequency band in radio frequency/intermediate frequency converter 102 and transmitted to analog/digital converter 103. Analog/digital converter 103 samples the analog signal transmitted from radio frequency/intermediate frequency converter 102 at an appropriate sampling frequency to convert to a digital signal and transmits the digital signal to automatic gain controller 104. Automatic gain controller 104 multiplies gain such that the amplitude of the output signal falls within a fixed range within a range that does not adversely affect a CMA algorithm that takes the value of the envelope as an index and transmits the result to Hilbert transformer 105.
In Hilbert transformer 105, the signal that has been transmitted from automatic gain controller 104 undergoes conversion to an analytic signal, i.e., a complex signal in which one of two signals having phase shifted 90° with respect to each other is a real part and the other signal is an imaginary part, and the analytic signal is then transmitted to multipath canceller 106. Multipath canceller 106 receives the complex input signal that has been transmitted from Hilbert transformer 105, converts to a signal in which the influence of multiple reflections has been reduced, and transmits the result to demodulator 107. Demodulator 107 subjects the signal transmitted from multipath canceller 106 to FM demodulation and supplies a signal in the speech frequency band. Although a complex output signal is supplied from output terminal 302 of the adaptive digital filter according to each of the above-described exemplary embodiments, only the real part of this complex signal is extracted and supplied to demodulator 107, or only the imaginary part of this complex signal is extracted, the code inverted, and then supplied to demodulator 107.
Although the foregoing explanation regards an exemplary embodiment of the present invention, the present invention is not limited to only the above-described exemplary embodiments and is open to various additions and modifications as described hereinbelow.
In the above-described exemplary embodiments, the envelope target value was taken as a fixed value, but a time-variable envelope target value can also be used that changes based on at least one of the input signal and output signal of the adaptive digital filter.
In exemplary embodiments that employ a branch line, the tap signal that is extracted by means of the branch line is transmitted without change to adder 338, but the tap signal may also be supplied to adder 338 by way of a multiplier that multiplies by a particular coefficient, or the tap signal may be passed through a particular type of filter and supplied to adder 338.
Exemplary embodiments that use real-number filter coefficients employ real-part extraction circuits 3350-335N-1 and real-part extraction circuit 309, but all or a portion of these components may be replaced by imaginary-part extraction/inversion circuits. An imaginary-part extraction/inversion circuit is a circuit that extracts only the imaginary part of a complex signal that is received as input and then supplies a value obtained by inverting the code of the imaginary part. A complex input signal that is applied to input terminal 301 of an adaptive digital filter is a complex signal in which one signal of two signals that are generated from one real signal and that have phases shifted 90° with respect to each other is a real part and the other signal is an imaginary part, and using an imaginary-part extraction/inversion circuit therefore obtains the same effect as in the above-described exemplary embodiments.
In exemplary embodiments that employ real-number filter coefficients, all of the filter coefficients are real numbers, i.e., scalar values, but a portion of the filter coefficients can also be made complex numbers, although this approach weakens the effect of reducing the amount of operations. In addition, real-part extraction circuit 309 can be moved to the output side of multiplier 310 or moved to the output side of multiplier 311 and operations carried out by means of complex numbers in multipliers 310 and 311.
Although an FIR filter is used as the filter unit in the above-described exemplary embodiments, an IIR (Infinite Impulse Response) filter can also be used.
Although an LMS algorithm was used as the adaptive algorithm in the above-described exemplary embodiments, various other adaptive algorithms can also be used such as a Recursive Least Squares Algorithm, a Least Squares Algorithm, an Affine Projection Algorithm, and a Gradient Algorithm. If the number of multiplications when updating filter coefficients by means of these adaptive algorithms is more than with the LMS algorithm, the effect of reducing the amount of operations by converting filter coefficients to real numbers is further increased.
Although FM modulation was an object in the above-described exemplary embodiments, the configuration of the present invention can obviously also be applied in other constant-amplitude modulation such as PSK (Phase Shift Keying). If multilevel CMA is used, the present invention can obviously also be applied in modulation modes such as QAM (Quadrature Amplitude Modulation). Still further, among constant modulus algorithms shown in Non-Patent Document 1, the present invention can clearly also be applied in cases in which the output signal is a complex signal.
Although explanation regarded CMA that takes the envelope as index in the above-described exemplary embodiments, the present invention can obviously also be applied in cases in which other statistics that are derived from the output signal are taken as index, as shown in Non-Patent Document 1.
The functions of the adaptive digital filter of the present invention can also be realized by hardware using separate components, ASIC (Application-Specific Integrated Circuits), or FPGA (Field-Programmable Gate Arrays). In addition, the present invention can also be applied to a program for causing the arithmetic processor of a DSP (Digital Signal Processor) that is a computer to execute the signal processing method of the adaptive digital filter of the present invention. This program can be written to a recording medium that can be read by a computer and installed on another computer. The program is provided recorded on a computer-readable recording medium such as a magnetic disk or semiconductor memory, is read by the computer at a time such as the time of start-up of the computer, and by controlling the operations of the computer, causes the computer to function as the adaptive digital filter in each of the above-described exemplary embodiments.
In addition, the present invention is not limited to any of the above-described working examples and is open to various modifications within the scope of the invention, these modifications of course being included within the scope of the present invention.
As described in the foregoing explanation, the adaptive digital filter according to the present invention is useful as an adaptive digital filter that uses a CMA algorithm, and is particularly suitable for use in the multipath equalizer of an FM receiver.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-206722 | Jul 2005 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2006/314153 | 7/18/2006 | WO | 00 | 1/10/2008 |
