Patent Application
20160087602
1. Technical Field
Apparatuses and methods consistent with the present inventive concept relate to power distribution networks, and more particularly to reducing noise due to an impedance barrier between the power distribution network and a semiconductor integrated circuit (IC).
2. Related Art
An impedance barrier exists between any switching load on an IC such as CMOS logic on a System-on-Chip (SoC) die and the Power Distribution Network (PDN) for the SoC that includes a Voltage Regulator Module (VRM). The impedance barrier is a result of semiconductor package inductance that forms a parasitic parallel resonant circuit with the on-die capacitance of the IC. When the spectral content of the switching current for the switching load is near the resonant frequency of the parallel resonant circuit, excessive switching noise will be generated that can affect operation of the CMOS logic or other circuits sharing the same PDN.
This problem is conventionally addressed by reducing the inductance, increasing the capacitance, or adding damping resistance to the resonant circuit. Another conventional approach adds a canceling current to reduce the total switching current. These methods, however, add significant cost to a product.
Aspects and features of the present inventive concept will be more apparent by describing example embodiments with reference to the accompanying drawings, in which:
While certain embodiments are described, these embodiments are presented by way of example only, and are not intended to limit the scope of protection. The methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the example methods and systems described herein may be made without departing from the scope of protection.
The parasitic capacitance on a semiconductor IC and its corresponding impedance varies with workload. As more transistors, for example in logic circuits and/or other circuits in which transistors are switched on and off, are inactive (i.e., not switching), the capacitance and available charge to supply active (i.e., switching) transistors in the circuits increases. The parasitic capacitance of the IC is the capacitance of transistor gates in the circuits that are not switching. At the same time, the total resistance and inductance for the inactive transistors in the circuits decreases. The resulting parallel resonance between semiconductor package inductance and IC parasitic capacitance will vary causing the impedance barrier between the PDN and the IC to vary. A semiconductor package pin inductance of 200 pico-henries may create the impedance barrier between the PDN and the IC.
Some embodiments related to the present inventive concept may suppress noise resulting from the impedance barrier by adding an adaptive feedback loop to control a voltage across a capacitance that may serve as a decoupling capacitance. As a result, less capacitance may be needed to achieve an acceptable PDN impedance target to suppress noise.
The impedance of the semiconductor package inductance to switching currents in switching circuitry, e.g., CMOS circuits, may contribute to the cause of the impedance barrier. IC or semiconductor package capacitance may be made more effective by sensing the high-frequency components of the voltage supplied to the IC or semiconductor package and controlling voltage across a local capacitance, for example, a bypass capacitor, to reduce noise variations by controlling the voltage on the capacitance. An amplifier may make the IC or semiconductor package capacitance more effective based on gain of the amplifier. The amplifier gain may be less than, greater than, or equal to one.
The resistive element 340 and second capacitive element 330 may be electrically connected in series between the first power supply line 112 and the second power supply line 114 and may form a filter 350. The filter 350 may be configured as a high-pass filter. High-frequency components of the power supply voltage applied between the first power supply line 112 and the second power supply line 114 through the PDN 150 caused by variations in the switching current 140 due to changes in switching load may be filtered by the filter 350 and sensed across the first resistive element 340 as a high-frequency alternating current (AC) signal 360. The high-frequency alternating current (AC) signal 360 may be a voltage signal or a current signal and may be a control signal for the controlled source 320. One of ordinary skill in the art will appreciate that other methods of sensing the high-frequency components of the power supply voltage known to those of skill in the art may be used without departing from the scope of the inventive concept.
The high-frequency AC control signal 360 may control an output voltage signal of the controlled source 320. The first capacitive element 310 may have a first terminal electrically connected to the first power supply line 112 and a second terminal connected to the output of the controlled source 320. The output of the controlled source 320 may control the voltage across the first capacitive element 310 based on the high-frequency AC control signal 360. By controlling the voltage across the first capacitive element 310, current may be supplied to the first power supply line 112 by the first capacitive element 310 to compensate for the variations in power supply voltage between the first power supply line 112 and the second power supply line 114 caused by the variations in the switching current 140, thereby reducing the noise due to the impedance barrier.
For convenience, throughout the disclosure, the first capacitive element 310 will be referred to as a first capacitor 310, the second capacitive element 330 will be referred to as a second capacitor 330, the resistive element 340 will be referred to as a resistor 340, and the controlled source 320 will be referred to as an amplifier 320. One of ordinary skill in the art will appreciate that various elements and/or devices having the appropriate resistive, capacitive, and controlled source characteristics may be used without departing from the scope of the present inventive concept.
The amplifier 320 may be, for example, but not limited to, a voltage feedback amplifier. The amplifier 320 may include one or more feedback resistors 522. The one or more feedback resistors may be configured to adjust a gain of the amplifier 320. One of ordinary skill in the art will appreciate that other amplifier configurations known to those of skill in the art may be implemented without departing from the scope of the inventive concept.
The filter 350 may include one or more capacitors 330 electrically connected in series to one or more resistors 340. The filter 350 may be configured as a high-pass filter. The filter 350 may be configured to extract high-frequency components of the power supply voltage applied between the first power supply line 112 and the second power supply line 114 through the PDN 150. For example, the high-frequency components of the power supply voltage may be sensed as a high-frequency AC signal 360 developed across the one or more resistors 340. One of ordinary skill in the art will appreciate that other filter configurations known to those of skill in the art may be implemented without departing from the scope of the inventive concept.
An input of the amplifier 320 may be electrically connected to a common connection point 524 between the one or more capacitors 330 and the one or more first resistors 340 and may be configured to input the high-frequency AC signal 360 developed across the one or more resistors 340. The amplifier 320 may apply gain to the high-frequency AC signal 360 to generate an amplified high-frequency AC signal 365 at an output 526 of the amplifier 320. The amplified high-frequency AC signal 365 may be a voltage signal or a current signal. The gain of the amplifier 320 may be set, for example, based on a value of the feedback resistor 522.
The output of the amplifier 320 may be electrically connected to a second terminal 312 of the first capacitor 310 and may be configured to apply the amplified high-frequency AC signal 365 to the second terminal 312 of the first capacitor 310 to control a voltage across the first capacitor 310. The amplified high-frequency AC signal 365 generated by the amplifier may control the voltage applied between the first terminal 311 and the second terminal 312 of the first capacitor 310 proportional to the high-frequency signal output by the filter. By controlling the voltage across the first capacitive element 310, current may be supplied to the first power supply line 112 by the first capacitive element 310 to compensate for the variations in power supply voltage between the first power supply line 112 and the second power supply line 114 caused by the variations in the switching current 140, thereby reducing the noise due to the impedance barrier.
The one or more adaptive feedback circuits 510 may control the voltage across the first capacitive element 310, current may be supplied to the first power supply line 112 by the first capacitive element 310 to compensate for the variations in power supply voltage between the first power supply line 112 and the second power supply line 114 caused by the variations in switching current, thereby reducing the noise due to the impedance barrier between the IC 610 and the PDN 150.
The SoC 710 may be mechanically enclosed in a package 720 mounted on a printed circuit board (PCB) 730. The package 720 may include one or more electrical leads 711 configured to connect the SoC to the printed circuit board 730. Two or more of the electrical leads 711 may be connected to a third power supply line 712 and a fourth power supply line 714 from the power supply 160. The PDN 150 may receive power from the power supply 160 and supply power to the one or more ICs 610 through the first power supply line 112 and the second power supply line 114. One or more of the ICs 610 may include an adaptive feedback circuit 510.
In some embodiments, one or more adaptive feedback circuits 510 may be provided to the SoC 710 external to the one or more ICs 610. The one or more adaptive feedback circuits 510 may control the voltage across the first capacitive element 310, current may be supplied to the first power supply line 112 by the first capacitive element 310 to compensate for the variations in power supply voltage between the first power supply line 112 and the second power supply line 114 caused by the variations in switching current, thereby reducing the noise due to the impedance barrier between the IC 610 and the PDN 150. The first capacitor 310 one or more adaptive feedback circuits 510 may be coupled proximately to a connection of the first power supply line 112 or the second power supply line 114 with a power supply external to the one or more ICs 610 and/or may be configured as a bypass capacitor.
The amplified high-frequency AC signal 365 may be applied to a capacitor (e.g., the capacitor 310) having a terminal connected to one of a positive power supply line and a negative power supply line (830). The amplified high-frequency AC signal 365 may control the voltage across the capacitor proportional to the high-frequency AC signal 360 output by the filter (840). By controlling the voltage across the capacitor, current may be supplied to one of the positive and negative power supply lines by the capacitor based on the amplified high-frequency AC signal 360 (850). The supplied current may compensate for the variations in power supply voltage between the positive and negative power supply lines caused by the variations in switching current, thereby reducing the noise due to the impedance barrier.
Implementation of the inventive concept may vary according to application and technology using known circuit designs, for example amplifier and/or filter designs, and methods. In some embodiments, the adaptive feedback circuit may be included on a CMOS SoC die. In some embodiments, the control circuitry (e.g., the filter 350 and amplifier 320) may be on-die and the decoupling capacitance (e.g., the first capacitor 310) may be in-package to keep the die size to a minimum while keeping inductance low.
In some embodiments, a power supply/power management device, for example, but not limited to a power large scale integrated circuit (PLSI) and/or a power management integrated circuit (PMIC), may include one or more high efficiency switching regulators. In this case the adaptive feedback circuit may be integrated on-die, as a discrete external circuit, or some hybrid integrated-external circuit combination. In some embodiments, the adaptive feedback circuit may include circuits to limit in-rush currents when power is applied to the capacitor.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the protection. The methods and systems described herein may be embodied in a variety of other forms. Various omissions, substitutions, and/or changes in the form of the example methods and systems described herein may be made without departing from the spirit of the protection.
The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the protection. For example, the example systems and methods disclosed herein can be applied to any electronic devices, including data storage devices such as hard disk drives, hybrid hard drives, solid state drives and the like, and/or any electronic devices having switching loads. In addition, other forms of storage, for example, but not limited to, DRAM or SRAM, battery backed-up volatile DRAM or SRAM devices, EPROM, EEPROM memory, etc., may additionally or alternatively be used. As another example, the various components illustrated in the figures may be implemented as software and/or firmware on a processor, ASIC/FPGA, or dedicated hardware. Also, the features and attributes of the specific example embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure.
Although the present disclosure provides certain example embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. Accordingly, the scope of the present disclosure is intended to be defined only by reference to the appended claims.
