Patent Application
20130100099
This disclosure relates to methods and systems for write waveform timing in writing data to an electromechanical display.
Electromechanical systems include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (e.g., mirrors) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of electromechanical systems device is called an interferometric modulator (IMOD). As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an interferometric modulator may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. In an implementation, one plate may include a stationary layer deposited on a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Interferometric modulator devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
Interferometric modulators can be driven by array driver circuits which write data to lines of display elements. Generally, a refresh rate of a display, for example a passive matrix display, is related to the write waveform line time for writing data to each line of the display. An increase in write waveform line time reduces the speed at which images may be updated. Thus, reduction in the line time required to write data to the display is desirable.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus for driving a display including a plurality of common lines and a plurality of segment lines connected to an array of display elements. The apparatus includes a controller configured to receive, as part of a frame of image data to be written to the array of display elements, image data for one or more common lines of the array, wherein the controller is configured to determine a line time for writing at least some of the image data to display elements along at least a first one of the one or more common lines of the array, wherein the determining is based at least in part on one or both of the write actuation state to be produced in the display elements along the at least a first one of the one or more common lines as defined by the at least some of the image data, and characteristics of at least some of the segment line transitions that will occur to place the segment lines in a series of states operable to write the image data to the one or more common lines. The apparatus also includes a common driver and a segment driver configured to drive the array of display elements to write the at least some of the image data to display elements along the at least one of the one or more common lines with the determined line time.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a method for driving a display including a plurality of common lines and a plurality of segment lines connected to an array of display elements. The method includes receiving image data, including image data for one or more common lines, determining a line time for writing the image data to one or more common lines based at least in part on one or both of a write actuation state of display elements along one or more common lines, and characteristics of at least some segment line transitions in writing the image data to the display elements along the one or more common lines. The method also includes writing the image data to display elements along one or more common lines with the determined line time.
Another innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus for driving a display including a plurality of common lines and a plurality of segment lines connected to an array of display elements. The apparatus includes means for receiving image data, including image data for one or more common lines, means for determining a line time for writing the image data to one or more common lines based at least in part on one or both of a write actuation state of display elements along one or more common lines, and characteristics of at least some segment line transitions in writing the image data to the display elements along the one or more common lines. The apparatus also includes means for writing the image data to display elements along one or more common lines with the determined line time.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a computer program product for processing data for a program configured to drive a display including a plurality of common lines and a plurality of segment lines connected to an array of display elements. The computer program product includes a non-transitory computer-readable medium having stored thereon code for causing processing circuitry to receive image data including image data for one or more common lines, determine a line time for the one or more common lines based at least in part on one or both of a write actuation state of display elements along one or more common lines and characteristics of at least some segment line transitions in writing the image data to the display elements along the one or more common lines, and write the image data to display elements along one or more common lines with the determined line time.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following detailed description is directed to certain implementations for the purposes of describing the innovative aspects. However, the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the implementations may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (e.g., e-readers), computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (e.g., MEMS and non-MEMS), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of electromechanical systems devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes, and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to a person having ordinary skill in the art.
Particular implementations of the subject matter described herein include a variable write waveform line time for different lines of display elements in a display. In some aspects, the line time is variable based on the image data that is to be written the display elements. For example, the line time of a particular line of display element may be a function of the number of display elements that will transition from an un-actuated state to an actuated state and the number of segment line transitions for writing the image data to the display.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. The time required to write display data may be reduced when compared to drivers known in the art. This may increase the frame rate at which images are displayed, and reduce artifacts associated with lower frame rate. Further, the performance of display elements may be improved with the same overall update rate for the display. For a given target update rate, it can be useful to allocate line time duration differently for different lines of the display based on particular image data to be written to the display and the particular structure of the display elements along the line. This can provide more margin for suitable operation for the display elements, and as a result, the yield of the display panels can be improved without reducing frame rate or sacrificing image quality.
An example of a suitable MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the interferometric modulator. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity, i.e., by changing the position of the reflector.
The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when actuated, reflecting light outside of the visible range (e.g., infrared light). In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.
The depicted portion of the pixel array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, e.g., chromium (Cr), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and conductor, while different, more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or a conductive/absorptive layer.
In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be approximately 1-1000 um, while the gap 19 may be less than 10,000 Angstroms (Å).
In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the pixel 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, e.g., a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD
In some implementations, hold voltages, address voltages, and segment voltages may be used which always produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.
During the first line time 60a: a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example,
As illustrated in
In implementations such as those shown in
The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (e.g., at block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting interferometric modulators 12 illustrated in
The process 80 continues at block 86 with the formation of a support structure e.g., a post 18 as illustrated in
The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in
The process 80 continues at block 90 with the formation of a cavity, e.g., cavity 19 as illustrated in
As discussed above with reference to
As illustrated in
A line time 60 includes a front porch 1020, a write pulse 1024, and a back porch 1022. A front porch 1020 may be defined as a delay time following initiation of segment line transitions and before the write pulse 1024 in order to avoid error in writing data to a display element along the common line. During a write pulse 1024, a voltage level corresponding to an address voltage, for example a high address voltage 74, is applied as illustrated in
As described above with reference to
In the example illustrated in
Table 1 below shows examples of a front porch 1020 duration, a write pulse 1024 duration, and a back porch 1022 duration corresponding to different frame rates in one implementation for driving a display having 1,152 common lines.
As shown in Table 1, for a frame rate of 15 Hz, a front porch 1020 may be set to 8 μs, a write pulse 1024 may be set to 40 and a back porch 1022 may be set to 8 μs for a total line time 60 of 56 μs. Alternatively, for a frame rate of 6.7 Hz, a front porch 1020 may be set to 12 μs, a write pulse 1024 may be set to 70 μs and a back porch 1022 may be set to 47 μs for a total line time 60 of 129 μs.
A front porch 1020 may be set to provide sufficient time for all segment lines to settle to their new state following a segment line transition and prior to the application of the write pulse 1024. Similarly, a back porch 1022 may be provided such that a write pulse 1024 may settle to a hold state prior to a subsequent segment line transition. The duration of the write pulse 1024 provides sufficient time to enable actuation of the display element on segment lines which are to be actuated by the write pulse 1024.
For example, in driving an array of display elements having a plurality of common lines and a plurality of intersecting segment lines connected to the display elements, the segment line transitions along a common line in the array may be staggered to reduce cross-talk in writing data to the display. Cross-talk may occur when a large number of segment lines are transitioned in phase at the start of a new line time. When segments are switching from −Vs to +Vs (or from +Vs to −Vs) due to the fact that the segment lines are being switched to write data to a new line, which in general is different data than that written to the previous line, a sudden change in the amount of charge on the segment lines is produced. This may cause a voltage transient on the common lines, leading to a potentially undesirable voltage levels along one or more common electrodes. As a result, display elements that were previously actuated may be released in error due to the cross talk of the transitioning segment lines.
In some implementations, to reduce crosstalk, a pre-discharge segment waveform may be used.
The duration of the write pulse 1024 may be set to provide adequate charge to write all display elements connected to the common line. A display element in an actuated position exhibits higher capacitance than a display element in an un-actuated state. As discussed above with reference to
The duration of the back porch may be selected to reduce or prevent accidental release of actuated display elements in a previously written line when the segments transition to the new data for the next line. This accidental release can occur if there is insufficient delay between the end of the write pulse for the previous line and the segment transitions that occur to write the immediately subsequent line. For example, with reference to
It may be further noted that the back porch is more important to proper display element operation for some common lines than for others in the display. In an array of display elements having a plurality of common lines intersecting a plurality of segment lines, different common lines are situated at different distances from the segment driver connected to the plurality of segment lines. As a result of the difference in distance from the segment driver, when the segment driver changes the state of a segment line, the transition is steepest at the common lines nearest the segment driver. Due to impedance along the segment line length, the rise time of the voltage is longer at the far end of the display away from the segment driver. As a result, the segment lines exhibit sharper and steeper transitions for display elements that are closer to the segment driver than for display elements that are farther from the segment driver. Due to the sharper transitions close to the segment driver, the segment line transitions produce larger transients on the common lines and may cause more accidental release of display elements that are closer to the segment driver that have transitioned to an actuated state relative to display elements that are farther from the segment driver. Therefore, a long back porch 1022 is more important for common lines that are closer to the segment driver, relative to common lines that are farther from the segment driver.
Conventionally, the same front porch 1020 duration, back porch 1022 duration, and write pulse duration 1024 are used for every common line across the array. In such implementations, the front porch 1020 used for every common line is the overall maximum front porch 1020 duration. Furthermore, the back porch 1022 duration used for every common line is the overall maximum back porch 1022 duration. In addition, the write pulse 1024 duration used is the overall maximum write pulse 1024 duration. The line time used for every common line in these conventional implementations is therefore max(FP)+max(WP)+max(BP).
As discussed above, the frame rate of the display is inversely proportional to the line time, such that as the line time increases, the frame rate decreases. Since the line time includes the combined time of a front porch 1020, back porch 1022, and write pulse 1024, a reduction in the front porch 1020, the back porch 1022, and/or the write pulse 1024 would result in a faster frame rate for the display.
According to some implementations, a line time duration (for example, sum of front porch 1020, back porch 1022, and/or write pulse 1024) may be adjusted based on data to be written to an array of display elements. Using this technique, display elements connected to common lines that can be written faster without errors due to the nature of the data being written are written faster, thus reducing the total time required to write a frame of data.
For the front porch setting, the number of stagger groups can be reduced based at least in part on the characteristics of the segment line transitions that will occur when the segments are switched from being set for writing the previous line to being set for writing the current line. For example, if a relatively small number of segment transitions are occurring, the number of stagger groups can be reduced. For example, if the implementation described above with reference to
To set the back porch, the number of segment transitions that will occur when preparing the segment lines to write the next line are considered. If there are few transitions that will occur for the next line, or if the transitions are relatively evenly distributed between the two transition directions, the back porch can be shortened. If no segments will switch to write the next line (for example, if the same data is written to display elements along a common line and display elements along an immediately subsequent common line), the back porch can be eliminated entirely. The data corresponding to an image to be written to the display may be processed to determine the number of segment transitions that will occur in writing the data to the array.
Further, the number of display elements that will be transitioned from an un-actuated state to an actuated state may be determined based on the data to be written to the line of display elements. For example, as discussed above, display elements along a particular common line may first be transitioned to an un-actuated state using a clearing pulse 70. The data corresponding to the particular common line may be analyzed to determine the number of display elements that will be transitioned to an actuated position when the data is written to the line of display elements. The fewer display elements that are going to be actuated during the write cycle, the shorter the write pulse 1024 can be. If all the display elements are going to remain un-actuated, then no write pulse at all is required, since the clear cycle has already set the display elements in the desired state for that line.
At block 1106, the image data is written to the display elements using the determined line time along one or more common lines. In some implementations, a line time may be determined for display elements along a particular common line, and the data may be written to the display elements along the particular common line using the determined line time. In some implementations, a line time may be determined for display elements along a first common line and the determined line time may be used to write data to display elements along a second common line. For example, a line time having the longest duration among a group of common lines may be used to write data to each common line in the group of common lines. In some implementations, an average value of determined line times for a group of common lines may be used to write data to the display elements along the common lines of the same group.
At block 1205, the characteristics of segment line transitions are determined for writing image data to display elements along an immediately subsequent common line based on image data for the subsequent common line and image data for the current common line. For example, the number of segment line transitions for a subsequent line of display elements may impact display elements which have been transitioned to an actuated state in a current line of display elements. Therefore, according to some implementations, the back porch 1022 may be determined based at least in part on the number of segment lines that will be transitioned for writing image data to the subsequent common line in order to provide sufficient time for the display elements along the current line to mechanically stabilize prior to the transitions of the segment lines for writing data to the subsequent line. At block 1206, the number of display elements along the current common line that are to be transitioned to an actuated state is determined. According to an example, the write pulse 1024 duration may be set based at least in part on the number of display elements that will transition from an un-actuated to an actuated state based on display data to be written to the current common line. As discussed above, the write pulse 1024 duration may be set based on the number of transitioning display elements, and the resulting capacitance change and charge leakage along the common line.
At block 1208, the waveform parameters, including one or more of the front porch 1020 duration, the back porch 1022 duration, and the write pulse 1024 duration for writing the image data to the current common line are calculated based at least in part on the determinations of one or more of blocks 1204, 1205, and 1206. At block 1210, the data is written to the display elements along the current common line based on the computed waveform parameters.
As discussed above, a line time for writing image data to a common line connected to a line of display elements may be determined based on the image data to be written to the display elements. In some implementations, the image data is analyzed to determine the number of display elements that will be transitioned from an un-actuated to an actuated state, and the number of segment line transitions that will occur. In some implementations, other factors, such as the color of display elements, and the location of a common line in the array may also be used to determine the line times.
For example, since display elements which exhibit different colors have different characteristics, they may have different response times to the application of write pulse 1024 and require different minimum write pulse 1024 durations. Similarly, a suitable front porch 1020 and back porch 1022 for different color display elements may be dependent on the color of the display element. In some implementations, different color display element rows are driven with driving signals corresponding to different write waveform line times. The line times of each color display element row may be configured based on the characteristics of the specific color, and the corresponding physical structure and response time of the particular color display element.
For example, a line time for lines having only blue display elements in the array may be less than a line time for green display elements in the array. A row including green display elements may be configured with a longer line time than a row with red display elements. Similarly, the row of red display elements may be configured to have a longer line time than the row of blue display elements.
Further, in some implementations the line times may also be determined based on a position of the line of display elements relative to a segment driver. For example, since the segment transitions occur sooner for common lines closer to the segment driver, in some implementations, the back porch 1022 duration may be set to be relatively longer for common lines closer to the segment driver.
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48, and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber, and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an interferometric modulator display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, e.g., data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g or n. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1xEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation, and gray-scale level. The frame buffer 28 may be configured to store the processed image data corresponding to a previous write operation (for example, image data corresponding to one or more previous lines of display elements), for access by the processor 21. The processor 21 may be configured to retrieve the previous image data to determine a line time for writing current image data to a line of display elements.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Further, the drive controller 29 may be configured to determine the line time for writing the image data to a line of display elements as discussed above with reference to
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (e.g., an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (e.g., an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (e.g., a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation is common in highly integrated systems such as cellular phones, watches and other small-area displays.
In some implementations, the input device 48 can be configured to allow, e.g., a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices as are well known in the art. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The steps of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of the IMOD as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
This disclosure claims priority to U.S. Provisional Patent Application No. 61/550,223, filed Oct. 21, 2011, entitled “SYSTEMS AND METHODS FOR CHOOSING DISPLAY MODES,” and assigned to the assignee hereof. The disclosure of the prior application is considered part of, and is incorporated by reference in, this disclosure.
| Number | Date | Country | |
|---|---|---|---|
| 61550223 | Oct 2011 | US |
