Patent Application
20080068236
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
The following notation is used throughout this document.
The present invention is an apparatus for and method of improving the quantization noise resolution of a time to digital converter (TDC) in a digital PLL or all-digital PLL (ADPLL) using noise shaping. In particular, the invention is intended for use in a digital radio transmitter and receiver but can be used in other applications as well, such as clock synchronization and timing recovery control loops including but not limited to a general communication channel or a control system for mitigation of feedback quantization noise. The TDC quantization noise shaping scheme of the present invention is effective to reduce TDC quantization noise levels to acceptable levels especially in the case of integer-N channel operation, where the performance impact may be most severe.
To aid in understanding the principles of the present invention, the description is provided in the context of a digital RF processor (DRP) transmitter and receiver that may be adapted to comply with a particular wireless communications standard such as GSM, EDGE, Bluetooth, WLAN, WiMax, WCDMA, LTE, etc. It is appreciated, however, that the invention is not limited to use with any particular communication standard or circuit and may be used in optical, wired, wireless and control system applications. Further, the use of the invention in PLLs is not limited to use with a specific modulation scheme but is applicable to any modulation scheme including both digital and analog modulation. The invention is applicable in situations where it is desirable to reduce the quantization noise generated by a time to digital converter circuit in a digital PLL or feedback control system.
Although the TDC quantization noise shaping mechanism in a PLL is applicable to numerous wireless communication standards and can be incorporated in numerous types of wireless or wired communication devices such a multimedia player, mobile station, cellular phone, PDA, DSL modem, WPAN device, etc., it is described in the context of a digital RF processor (DRP) based transmitter that may be adapted to comply with a particular wireless communications standard such as GSM, Bluetooth, EDGE, WLAN, WiMax, WCDMA, LTE, etc. It is appreciated, however, that the invention is not limited to use with any particular communication standard and may be used in optical, wired and wireless applications. Further, the invention is not limited to use with a specific modulation scheme but is applicable to any modulation scheme including both digital and analog modulation schemes. This functionality is often also employed in feedback control systems that may be used for clock synchronization as well as timing recovery loops. Furthermore, the proposed scheme can be expanded to aid in mitigation of interference affects due to the possible coupling of the transmit RF output signal back into the frequency reference input often found in integrated radio solutions.
Note that throughout this document, the term communications device is defined as any apparatus or mechanism adapted to transmit, receive or transmit and receive data through a medium. The term communications transceiver or communications device is defined as any apparatus or mechanism adapted to transmit and receive data through a medium. The communications device or communications transceiver may be adapted to communicate over any suitable medium, including wireless or wired media. Examples of wireless media include RF, infrared, optical, microwave, UWB, Bluetooth, GSM, EDGE, WiMAX, WiMedia, WiFi, 3G/4G or any other broadband medium, etc. Examples of wired media include twisted pair, coaxial, optical fiber, any wired interface (e.g., USB, Firewire, Ethernet, etc.). The term Ethernet network is defined as a network compatible with any of the IEEE 802.3 Ethernet standards, including but not limited to 10Base-T, 100Base-T or 1000Base-T over shielded or unshielded twisted pair wiring. The terms communications channel, link and cable are used interchangeably. The notation DRP is intended to denote either a Digital RF Processor or Digital Radio Processor. References to a Digital RF Processor infer a reference to a Digital Radio Processor and vice versa. The term data frequency command word (FCW) is defined as the demanded frequency normalized by the reference frequency (FREF).
The term multimedia player or device is defined as any apparatus having a display screen and user input means that is capable of playing audio (e.g., MP3, WMA, etc.), video (AVI, MPG, WMV, etc.) and/or pictures (JPG, BMP, etc.) and/or other content widely identified as multimedia. The user input means is typically formed of one or more manually operated switches, buttons, wheels or other user input means. Examples of multimedia devices include pocket sized personal digital assistants (PDAs), personal media player/recorders, cellular telephones, handheld devices, and the like.
Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, steps, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is generally conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, bytes, words, values, elements, symbols, characters, terms, numbers, or the like.
It should be born in mind that all of the above and similar terms are to be associated with the appropriate physical quantities they represent and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as ‘processing,’ ‘computing,’ ‘calculating,’ ‘determining,’ ‘displaying’ or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing a combination of hardware and software elements. In one embodiment, a portion of the mechanism of the invention is implemented in software, which includes but is not limited to firmware, resident software, object code, assembly code, microcode, etc.
Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium is any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device, e.g., floppy disks, removable hard drives, computer files comprising source code or object code, flash semiconductor memory (USB flash drives, etc.), ROM, EPROM, or other semiconductor memory devices.
A simplified block diagram illustrating an example ADPLL based DRP polar transmitter is shown in
In operation, the modulating data frequency command word (FCW) and the channel FCW, both digital values, are input to the frequency synthesizer which is adapted to generate a digital tuning word to the DCO. The DCO produces a digital clock CKV in the RF frequency band. The CKV clock is amplified by the PA and terminated with an antenna. In the feedback path, the CKV clock is used to retime the FREF clock. The FREF clock is the stable reference frequency clock. The FREF clock is input to the D input of a retiming element (not shown) (e.g., retimer, flip flop, register, etc.) and is clocked by the CKV clock. The output generated is the retimed frequency reference clock CKR. The operation of the flip flop/register serves to strip FREF of its critical timing information and generate a retimed CKR clock. It is this CKR clock that is subsequently distributed and used throughout the system. As a result of the retiming operation, the edges of the CKR clock are now synchronous with the RF oscillator clock CKV. This results in the time separation between the closest CKR and CKV edges to be time invariant.
Thus, the entire radio, including a digital RF processor, the digital baseband circuitry and the application processor, is operated in a clock synchronous mode wherein every clock in the system is either derived from or synchronized to the RF oscillator clock. Thus, the frequency reference clock is made synchronous to the oscillator clock and this retimed frequency reference clock is used to drive the entire digital logic circuitry of the SoC chip. This ensures that the different clock edges throughout the system will not exhibit mutual drift.
The CKR clock can be used to drive the digital logic since the digital logic is not sensitive to the accuracy of the edges, as long as the edges are compliant with the relevant timing specifications. In order to eliminate injection pulling effect in the entire chip, all the digital logic including DSP or other processors is adapted to operate on the CKR clock or clocks that are derived from or synchronous to the CKV clock.
A block diagram illustrating an ADPLL-based polar transmitter for wireless applications is shown in
For illustration purposes only, the transmitter, as shown, is adapted for the GSM/EDGE/WCDMA cellular standards. It is appreciated, however, that one skilled in the communication arts can adapt the transmitter illustrated herein to other modulations and communication standards as well without departing from the spirit and scope of the present invention.
The transmitter, generally referenced 10, is well-suited for a deep-submicron CMOS implementation. The transmitter comprises a complex pulse shaping filter 12, amplitude modulation (AM) block 14 and ADPLL 11. The circuit is operative to perform complex modulation in the polar domain in addition to the generation of the local oscillator (LO) signal for the receiver. All clocks internal to the system are derived directly from this source. Note that the transmitter is constructed using digital techniques that exploit the high speed and high density of the advanced CMOS, while avoiding problems related to voltage headroom. The ADPLL circuit replaces a conventional RF synthesizer architecture (based on a voltage-controlled oscillator (VCO) and a phase/frequency detector and charge-pump combination), with a digitally controlled oscillator (DCO) 28 and a time-to-digital converter (TDC) 42. All inputs and outputs are digital and some even at multi-GHz frequency.
The core of the ADPLL is a digitally controlled oscillator (DCO) 28 adapted to generate the RF oscillator clock CKV. The oscillator core (not shown) operates at least twice the 1.6-2.0 GHz high band frequency or at least four times the 0.8-1.0 GHz low band frequency. The output of the DCO is then divided for precise generation of RX quadrature signals, and for use as the transmitter's carrier frequency. The single DCO is shared between transmitter and receiver and is used for both the high frequency bands (HB) and the low frequency bands (LB). In additional to the integer control of the DCO, at least 3-bits of the minimal varactor size used are dedicated for ΣΔ dithering in order to improve frequency resolution. The DCO comprises a plurality of varactor banks, which may be realized as n-poly/n-well inversion type MOS capacitor (MOSCAP) devices or Metal Insulator Metal (MIM) devices that operate in the flat regions of their C-V curves to assist digital control. The output of the DCO is input to the RF high band pre-power amplifier (PPA) 34. It is also input to the RF low band pre-power amplifier 32 after divide by two via divider 30.
The expected variable frequency fV is related to the reference frequency fR by the frequency command word (FCW).
The FCW is time variant and is allowed to change with every cycle TR=1/fR of the frequency reference clock. With WF=24 the word length of the fractional part of FCW, the ADPLL provides fine frequency control with 1.5 Hz accuracy, according to:
The ADPLL operates in a digitally-synchronous fixed-point phase domain as follows: The variable phase accumulator 36 determines the variable phase RV[i] by counting the number of rising clock transitions of the DCO oscillator clock CKV as expressed below.
The index i indicates the DCO edge activity. The variable phase RV[i] is sampled via sampler 38 to yield sampled FREF variable phase RV[k], where k is the index of the FREF edge activity. The sampled FREF variable phase RV[k] is fixed-point concatenated with the normalized time-to-digital converter (TDC) 42 output ε[k]. The TDC measures and quantizes the time differences between the frequency reference FREF and the DCO clock edges. The sampled differentiated (via block 40) variable phase is subtracted from the frequency command word (FCW) by the digital frequency detector 18. The frequency error fE[k] samples
f
E
[k]=FCW−[(RV[k]−ε[k])−(RV[k−1]−ε[k−1])] (4)
are accumulated via the frequency error accumulator 40 to create the phase error φE[k] samples
which are then filtered by a fourth order IIR loop filter 22 and scaled by a proportional loop attenuator α. A parallel feed with coefficient ρ adds an integrated term to create type-II loop characteristics which suppress the DCO flicker noise.
The IIR filter is a cascade of four single stage filters, each satisfying the following equation:
y[k]=(1−λ)·y[k−1]+λ·x[k] (6)
wherein
x[k] is the current input;
y[k] is the current output;
k is the time index;
λ is the configurable coefficient;
The 4-pole IIR loop filter attenuates the reference and TDC quantization noise with an 80 dB/dec slope, primarily to meet the GSM/EDGE spectral mask requirements at 400 kHz offset. The filtered and scaled phase error samples are then multiplied by the DCO gain KDCO normalization factor fR/{circumflex over (K)}DCO via multiplier 26, where fR is the reference frequency and {circumflex over (K)}DCO is the DCO gain estimate, to make the loop characteristics and modulation independent from KDCO. The modulating data is injected into two points of the ADPLL for direct frequency modulation, via adders 16 and 24. A hitless gear-shifting mechanism for the dynamic loop bandwidth control serves to reduce the settling time. It changes the loop attenuator α several times during the frequency locking while adding the (α1/α2−1)φ1 DC offset to the phase error, where indices 1 and 2 denote before and after the event, respectively. Note that φ1=φ2, since the phase is to be continuous.
The FREF input is resampled by the RF oscillator clock CKV via retimer block 46 which may comprise a flip flop or register clocked by the reference frequency FREF. The resulting retimed clock (CKR) is distributed and used throughout the system. This ensures that the massive digital logic is clocked after the quiet interval of the phase error detection by the TDC. Note that in the example embodiment described herein, the ADPLL is a discrete-time sampled system implemented with all digital components connected with all digital signals.
A block diagram illustrating a discrete time domain model of the ADPLL is shown in
The TDC block 66 in this feedback system quantizes the phase of the output CKV clock denoted by φv[n]. The TDC quantization is a nonlinear operation within the loop that may introduce oscillations (referred to as limit cycles in control system analysis) within its quantization interval, especially for integer-N channel frequencies. This oscillation frequency varies depending on the initial state of ADPLL. When the oscillation frequency of the quantization noise is low, the loop filter is unable to filter the idle tones and the overall system performance (i.e. RMS phase error) suffers. The RMS phase errors in these cases can be worse than the theoretical performance of TDC quantization which assumes the quantization noise to be white and uniformly distributed over a quantization interval. In real systems, however, noise contributions from other sources will reduce this effect by adding randomization to the quantization process.
If the quantization noise from the TDC is high-pass frequency shaped, however, the contribution of the TDC quantization noise can be further reduced. The low pass filter in the ADPLL loop is operative to remove the high frequency content of the noise. Thus, the present invention provides a signal processing algorithm, method and system that performs noise shaping on this quantization noise so as to push the quantization noise outside loop bandwidth, thereby allowing the ADPLL low pass loop filter to remove it.
A block diagram illustrating a single chip radio incorporating an all-digital local oscillator based polar transmitter and digitally-intensive receiver, as well as the TDC quantization noise shaping mechanism of the present invention is shown in
The radio circuit, generally referenced 130, comprises a radio integrated circuit 136 coupled to a crystal 152, front end module 176 and battery management circuit 132. The radio chip 136 comprises a script processor 146, digital baseband (DBB) processor 144, memory 142 (e.g., static RAM), TX block 148, RX block 150, digitally controlled crystal oscillator (DCXO) 154, slicer 156, RF front-end module 176 and antenna 180, power management unit 138, RF built-in self test (BIST) 140, battery 134 and battery management circuit 132. The TX block comprises high speed and low speed digital logic block 158 including ΣΔ modulators 160, 162, digitally controlled oscillator (DCO) 164, digitally controlled power amplifier (DPA) 174 or pre power amplifier (PPA), time to digital converter (TDC) circuit 170 and TDC quantization noise shaping block 166. The ADPLL and transmitter generate various radio frequency signals. The RX block comprises a low noise transconductance amplifier 182, current sampler 184, discrete time processing block 186, analog to digital converter (ADC) 188 and digital logic block 190.
In accordance with the invention, the radio also comprises TDC quantization noise shaping block 166 operative to reduce the quantization noise contribution of the TDC. It is noted that the TDC quantization noise shaping mechanism is especially applicable in an ADPLL circuit.
The principles presented herein have been used to develop three generations of a Digital RF Processor (DRP): single-chip Bluetooth, GSM and GSM/EDGE radios realized in 130 nm, 90 nm and 65 nm digital CMOS process technologies, respectively. The common architecture is highlighted in
A key component is the digitally controlled oscillator (DCO) 164, which avoids any analog tuning controls. A digitally-controlled crystal oscillator (DCXO) generates a high-quality base station-synchronized frequency reference such that the transmitted carrier frequencies and the received symbol rates are accurate to within 0.1 ppm. Fine frequency resolution is achieved through high-speed ΣΔ dithering of its varactors. Digital logic built around the DCO realizes an all-digital PLL (ADPLL) that is used as a local oscillator for both the transmitter and receiver. The polar transmitter architecture utilizes the wideband direct frequency modulation capability of the ADPLL and a digitally controlled power amplifier (DPA) 174 for the amplitude modulation. The DPA operates in near-class-E mode and uses an array of nMOS transistor switches to regulate the RF amplitude and acts as a digital-to-RF amplitude converter (DRAC). It is followed by a matching network and an external front-end module 176, which comprises a power amplifier (PA), a transmit/receive switch for the common antenna 180 and RX surface acoustic wave (SAW) filters. Fine amplitude resolution is achieved through high-speed ΣΔ dithering of the DPA nMOS transistors.
The receiver 150 employs a discrete-time architecture in which the RF signal is directly sampled at the Nyquist rate of the RF carrier and processed using analog and digital signal processing techniques. The transceiver is integrated with a script processor 146, dedicated digital base band processor 144 (i.e. ARM family processor or DSP) and SRAM memory 142. The script processor handles various TX and RX calibration, compensation, sequencing and lower-rate data path tasks and encapsulates the transceiver complexity in order to present a much simpler software programming model.
The frequency reference (FREF) is generated on-chip by a 26 MHz (could be 38.4 MHz or other) digitally controlled crystal oscillator (DCXO) 154 coupled to slicer 156. An integrated power management (PM) system is connected to an external battery management circuit 132 that conditions and stabilizes the supply voltage. The PM comprises multiple low drop out (LDO) regulators that provide internal supply voltages and also isolate supply noise between circuits, especially protecting the DCO. The RF built-in self-test (RFBIST) 140 performs autonomous phase noise and modulation distortion testing, various loopback configurations for bit-error rate measurements and implements various DPA calibration and BIST procedures. The transceiver is integrated with the digital baseband, SRAM memory in a complete system-on-chip (SoC) solution. Almost all the clocks on this SoC are derived from and are synchronous to the RF oscillator clock. This helps to reduce susceptibility to the noise generated through clocking of the massive digital logic.
The transmitter comprises a polar architecture in which the amplitude and phase/frequency modulations are implemented in separate paths. Transmitted symbols generated in the digital baseband (DBB) processor are first pulse-shape filtered in the Cartesian coordinate system. The filtered in-phase (I) and quadrature (Q) samples are then converted through a CORDIC algorithm into amplitude and phase samples of the polar coordinate system. The phase is then differentiated to obtain frequency deviation. The polar signals are subsequently conditioned through signal processing to sufficiently increase the sampling rate in order to reduce the quantization noise density and lessen the effects of the modulating spectrum replicas.
A more detailed description of the operation of the ADPLL can be found in U.S. Patent Publication No. 2006/0033582A1, published Feb. 16, 2006, to Staszewski et al., entitled “Gain Calibration of a Digital Controlled Oscillator,” U.S. Patent Publication No. 2006/0038710A1, published Feb. 23, 2006, Staszewski et al., entitled “Hybrid Polar/Cartesian Digital Modulator” and U.S. Pat. No. 6,809,598, to Staszewski et al., entitled “Hybrid Of Predictive And Closed-Loop Phase-Domain Digital PLL Architecture,” all of which are incorporated herein by reference in their entirety.
A simplified block diagram illustrating an example communication device incorporating the TDC quantization noise shaping mechanism of the present invention is shown in
The cellular phone, generally referenced 70, comprises a baseband processor or CPU 71 having analog and digital portions. The basic cellular link is provided by the RF transceiver 94 and related one or more antennas 96, 98. A plurality of antennas is used to provide antenna diversity which yields improved radio performance. The cell phone also comprises internal RAM and ROM memory 110, Flash memory 112 and external memory 114.
In accordance with the invention, the RF transceiver comprises a TDC quantization noise shaping block 128 operative to reduce effect of the quantization noise generated by the TDC in the ADPLL circuit, as described in more detail infra. The benefits include: lower modulation distortion and better modulation mask in during transmission, as well as lower close-in phase noise and better sensitivity and selectivity during reception. In operation, the TDC quantization noise shaping mechanism may be implemented as hardware, as software executed as a task on the baseband processor 71 or a combination of hardware and software. Implemented as a software task, the program code operative to implement the TDC quantization noise shaping mechanism of the present invention is stored in one or more memories 110, 112 or 114.
Several user interface devices include microphone 84, speaker 82 and associated audio codec 80, a keypad for entering dialing digits 86, vibrator 88 for alerting a user, camera and related circuitry 100, a TV tuner 102 and associated antenna 104, display 106 and associated display controller 108 and GPS receiver 90 and associated antenna 92.
A USB interface connection 78 provides a serial link to a user's PC or other device. An FM receiver 72 and antenna 74 provide the user the ability to listen to FM broadcasts. WLAN radio and interface 76 and antenna 77 provide wireless connectivity when in a hot spot or within the range of an ad hoc, infrastructure or mesh based wireless LAN network. A Bluetooth EDR radio and interface 73 and antenna 75 provide Bluetooth wireless connectivity when within the range of a Bluetooth wireless network. Further, the communication device 70 may also comprise a WiMAX radio and interface 123 and antenna 125. SIM card 116 provides the interface to a user's SIM card for storing user data such as address book entries, etc. The communication device 70 also comprises an Ultra Wideband (UWB) radio and interface 83 and antenna 81. The UWB radio typically comprises an MBOA-UWB based radio.
Portable power is provided by the battery 124 coupled to battery management circuitry 122. External power is provided via USB power 118 or an AC/DC adapter 120 connected to the battery management circuitry which is operative to manage the charging and discharging of the battery 124.
A block diagram illustrating a time to digital converter (TDC) circuit in more detail is shown in
In the example presented in
The combination of the arithmetic phase detector and the TDC can be considered a replacement of a conventional phase/frequency detector. Since all the circuitry in the ADPLL system uses the delayed, retimed version CKR of the FREF clock except for the TDC and the clock retiming circuitry, which uses the original FREF clock, there will be a quiet time period during the TDC sampling period. The ADPLL thus exploits a time-causal relationship between the FREF and CKR clocks. The critical continuous-domain time-difference conversion to a digital word by the TDC is performed at the FREF edge event. The FREF clock is then resampled (i.e. retimed) by the CKV clock edges to generate the CKR clock. The digital processing of almost the entire chip, including the ADPLL, is performed at the following CKR edge event or synchronously with the other CKV events.
Thus, the digital logic circuitry on the chip is forced to be quiet at the time the FREF edge event arrives. Once the time difference has been measured by the TDC, the tens or hundreds of thousands of gates of digital circuitry can operate with the consequent noise generation from ringing, etc.
The FREF retiming quantization error is determined by the time to digital converter (TDC). As shown in
The TDC operates by passing the oscillator clock (CKV) through the chain of inverters wherein the delayed clock is then sampled by the FREF clock using an array of registers whose outputs form a pseudo-thermometer code. The TDC output is normalized by the oscillator clock period TV before being input to the phase locked loop.
In principle, the TDC operation results in quantizing the phase (or time) difference between FREF and the nearest causal CKV clock edge at specific time instances. This specific time instance is the rising edge of FREF clock in the case of an ADPLL.
The TDC quantization operation, however, has an effect on the phase noise at the output of the ADPLL. Considering the phase noise spectrum contributors at the RF output of the ADPLL reveals that the TDC phase noise contribution can be minimized by improving the TDC timing resolution and increasing the sampling rate.
There are two potential internal sources of noise: the first is the oscillator itself and the second is the TDC operation of calculating ε (epsilon), i.e. the normalized timing delay difference. It is noted that other than these two sources of internal phase noise, the system, due to its digital nature, is relatively immune from any time-domain or amplitude-domain perturbations and does not contribute to the phase noise.
The phase noise generated by the operation of the TDC is due to the fact that even though the TDC is a digital circuit, the FREF and CKV clock edge information is continuous in the time domain. The TDC error comprises several components including quantization errors, non-linearity errors and random errors due to thermal effects. The TDC quantization noise, however, is the predominant of the three components. The TDC phase error is particularly worse (i.e. spikes) when are caused by ill-conditioned TDC behavior at integer-N values of the channel number.
A solution to this problem is to randomize the instantaneous value of the timing difference using well-known sigma-delta modulation techniques such that the reference clock FREF is dithered before being input to the TDC. A block diagram illustrating an example FREF dither circuit is shown in
Note that the sigma-delta modulator may be any order depending on the requirements of the particular application. In the example presented herein, the modulator is a 5th order sigma-delta MASH modulator. A constant input code to the sigma-delta modulator results in a high-speed unit weighted 32-bit output whose time-averaged value equals that of the input. The power spectral density of the output is noise shaped with the quantization energy rising at higher frequencies.
A block diagram illustrating one realization of the FREF delay circuit portion of the dither circuit of
For a better understanding of the effect of TDC quantization, consider quantizing a linear phase signal with a uniform quantizer in an open-loop system. A diagram illustrating the quantization of a linear phase signal is shown in
As mentioned earlier, the nonlinear effect of the quantizer in a feedback system introduces limit cycles. The following examples demonstrate this effect in an example ADPLL system. The RMS phase error (or the phase error trajectory) for an integer channel depends on the initial state and the noise in the digital PLL system. A graph illustrating the phase error trajectory for an initial state resulting in a poor RMS phase error is shown in
At the same time, for a different state the phase error trajectory may look much better as shown in
The variation of the RMS phase error measurement as the initial CKV clock phase is varied is shown in
The time-to-digital converter in the broad sense defines a mechanism by which the difference (e.g., timing difference) between two analog quantities (e.g., the difference between the respective edge timestamps of reference and DCO clocks) is quantized. The term feedback control system refers to any such loop that inherently introduces such analog-to-digital quantization in the feedback or sensory paths of the loop. Such arrangements are often employed in control systems where synchronization is achieved between a reference and a control signal. Examples of such feedback control systems include symbol timing recovery loops, clock synchronization between, for example, base station and a mobile device, baseband and the transceiver, etc.
A block diagram illustrating an example digital controller circuit incorporating the quantization noise shaping mechanism of the present invention and utilizing analog noise shaping is shown in
In this first generalized embodiment, digital noise shaping is applied after the quantization step. The quantization noise shaping block uses the reference input with noise added and data from the digital controller to generate the digital noise shaping. In the particular example of the ADPLL, the reference signal is the frequency command word (FCW). The quantizer functions to quantize the error between the desired FCW and the instantaneous frequency deviation of the PLL output normalized with respect to the reference frequency. The sampling rate of the quantizer in this case is the reference clock rate. The quantization noise shaping block generates the quantization correction signal utilizing the reference input (i.e. the desired frequency command word) and observable signals from the controller (e.g., example DCO correction signal, actual quantized output, etc.)
A second generalized block diagram illustrating the TDC resolution improvement mechanism of the present invention is shown in
In this second generalized embodiment, the noise shaping provided by the quantiziation noise shaping block is analog (rather than digital as was in the first generalized embodiment of
As stated supra, the objective of the present invention is to improve TDC quantization noise for both integer and non-integer channels thereby improving the overall RMS phase error. A generalized block diagram illustrating the TDC resolution improvement mechanism of the present invention is shown in
In one embodiment, an implementation of the quantizer correction block is operative to estimate the CKV clock edges at each FREF cycle and control the spectral shape of the quantization noise. The TDC quantization noise can be shaped by observing the TDC output and applying appropriate delay control signals (e.g., dither) to delay the reference clock (FREF of 26 MHz) such that the TDC quantization noise is shaped.
The noise shaping applied can take many forms. Several examples of preferred noise shaping are listed below:
The motivation behind the proposed mechanism is derived from the observation that the relative phase (or time delay) of the CKV clock with respect to TDC reference clock (i.e. the delay controlled FREF clock) can affect the quantization noise from the TDC quantizer.
To illustrate this, consider an open loop simulation of the TDC. The input to the TDC quantizer is a 5th order ΣΔ generated pseudo-random delay with varying delay offsets. The unit delay of ΣΔ output is also varied as a fraction of the TDC quantization resolution (i.e. inverter delay Tinv). To measure the sensitivity of the TDC quantizer, the TDC output is correlated with the input delay sequences. This yields a good indication of the accuracy of the TDC output.
A block diagram illustrating an example implementation of the TDC quantization noise shaping mechanism of the present invention in an ADPLL loop is shown in
It is noted that in case of ADPLL, the present invention does not require any significant additional hardware to implement the quantization noise shaping mechanism. In the example embodiment presented herein, the mechanism uses the dithering NAND gates (or other possible ADPLL dithering implementations) and existing structure of the TDC circuit to implement the TDC resolution enhancement mechanism. The only additional cost being the computation of the adaptive dither correction that may be either realized as dedicated hardware or more conveniently as firmware operating on the internal script processor 146 (
In accordance with the mechanism, the frequency reference clock FREF is delayed utilizing NAND gates as shown in
A graph illustrating the sensitivity of the TDC for different delay offsets at the input to the TDC is shown in
A block diagram illustrating the TDC quantization noise shaping mechanism of
Note that for illustration purposes only, the invention depicts a realization of the TDC circuit as shown in
In accordance with the invention, the reference clock is delayed with NAND gates as shown in
The circuit 300 is operative to shape the quantization noise as follows. The mechanism attempts to place the CKV clock (output of the ADPLL) at the boundary of the delayed (i.e. dithered) reference clock, thereby operating the TDC circuit 316 at its most sensitive delay point. The CKV clock edge can be estimated from the previous estimate of the CKV clock and the current Frequency Command Word (FCW) including channel and modulation. When there is no activity in the TDC, it means there are no changes in edge timing and the TDC is not operating in its sensitive point, i.e. the TDC is not tracking the CKV (RF oscillator) clock edge. The mechanism moves the FREF edge (earlier or later) to place the TDC as close as possible to its sensitive operating point. The slope of the normalized tuning word (NTW) is used to determine whether to speed up or retard the FREF clock.
The dithering applied to the reference clock edge is generated as follows. The fraction of estimated CKV clock edge is determined in terms of NAND gate delay or it could be realized through some other means. Further, if the TDC output is low frequency in nature (i.e. the TDC quantization noise is of low frequency) then high frequency TDC noise is induced by adding dithering in a direction opposite that of the DCO drift. The slope of the DCO drift is estimated from the slope of the normalized tuning word (NTW) NTW_PLL signal of the ADPLL.
An example block diagram illustrating the low frequency activity detect mechanism of the present invention is shown in
ABS(φq′[n]−φq[n−1])>ρ (7)
where
ρ is the threshold (e g., TINV/TV/4);
TINV is the inverter delay (i.e. raw TDC resolution);
TV is the ADPLL frequency period;
In operation, the low frequency activity detector examines the differences between sample output of the TDC circuit, i.e. it differentiates the output). It detects whether or not the TDC output contains high frequency content. This is an indication that the TDC quantization noise is high frequency noise shaped. The output of the circuit 330 is an enable signal ‘1’ or a disable signal ‘0’ to indicate whether the TDC is active enough or not. The dither is applied only if the enable signal is active. A high rate of change indicates the TDC is active. Conversely, a low rate of change indicates the TDC is inactive. In the latter case, this means that some amount of delay needs to be added to the reference clock.
An example block diagram illustrating the DCO slope estimation mechanism of the present invention is shown in
SIGN(NTW_PLL[n]-NTW_PLL[n−1]) (8)
In operation, the block 342 estimates the negative slope of the DCO drift. It is thus determined whether the DCO drift is increasing or decreasing. The output from this block is an indication of either positive or negative slope (i.e. +1/−1) or no change. The output value represents the direction the reference delay is to be applied. The high frequency content is contributed by the instantaneous phase errors due to quantization, the digital nature of the loop, phase/frequency modulation of the ADPLL clock, etc.
A block diagram illustrating the fractional phase offset estimation mechanism of the present invention is shown in
The circuit 336 is operative to estimate the CKV clock edge for the next reference clock edge (i.e. cycle) in terms of NAND gate delays or, in general, fractional delay of an inverter. The output of the circuit is in terms of NAND gate resolution. The clock edge can be estimated with fairly good accuracy as the DCO drifts only by a very small amount (<2 ps) within a reference clock interval. The drift from one reference clock to another and the resulting error is thus very small.
The value (phase offset) output of this block 336 is typically much smaller than the resolution of the TDC (<20 ps). The phase offset is added with the negative slope of the DCO drift multiplied by the NAND delay (5 ps in this example embodiment). The sum is then added to the input of the TDC circuit along with the FREF noise after a delay 332 via time-domain adder 314 (
The TDC quantization noise shaping mechanism can be verified by implementing the discrete time domain model of ADPLL as described in
A graph illustrating the improvement of the ADPLL output phase error using the mechanism of the invention in the case of an integer channel is shown in
A graph illustrating the spectrum of the TDC quantization noise for the integer channel case is shown in
A graph illustrating the improvement of the ADPLL output phase error using the mechanism of the invention in the case of a non-integer channel is shown in
A graph illustrating the spectrum of the TDC quantization noise for the non-integer channel case is shown in
It is intended that the appended claims cover all such features and advantages of the invention that fall within the spirit and scope of the present invention. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention.
This application claims priority to U.S. Provisional Application No. 60/825,838, filed Sep. 15, 2006, entitled “Software Reconfigurable All Digital Phase Lock Loop”, incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60825838 | Sep 2006 | US |
