Patent Application
20200313567
The present disclosure relates generally to power conversion. In particular, but not by way of limitation, the present disclosure relates to systems, methods and apparatuses for arbitrary waveform power generation.
Switching power converters, or switchmode power converters, using pairs of switches (e.g., metal-oxide semiconductor field-effect transistors (MOSFETS)) rose in popularity in the 1980s due to their efficiency in both up and down conversion of power. Switching power converters employ pulse-width modulated (PWM) control of switches along with LC filtering of a PWM output from the switches to generate an up or downconverted waveform that roughly mimics a setpoint, though with some “ripple” that typically requires filtering. When a switch in a switchmode power converter is “on” it has low resistance, and when “off” it has a low leakage current. Consequently, the switches in a switchmode power converter are close to ideal and power dissipation is minimized.
This example shows that ripple voltage has long-been considered an inevitable byproduct of switchmode power conversion, which more or less, digitizes an analog setpoint, and then attempts to convert that digital signal (the PWM voltage at output node 103) back to an analogue signal via the filter. To better recreate the setpoint waveform, larger filter components can be used, thereby further and further reducing ripple.
However, larger LC filter components are also slower to react to setpoint changes (i.e., they cause an increased response time of the converter). Thus, as one reduces ripple with larger LC components, one also adds delay between the setpoint and switchmode power converter's tracking of the setpoint. Higher voltages and currents also suggest the need for larger switches and larger LC components, thus further adding delay between the setpoint and the output's ability to rapidly track the setpoint.
Another way to reduce ripple is to increase switching frequency, which allows for a smaller LC filter to be used. Yet, power converters are limited to a maximum practical switching frequency due to switching losses, and thus the LC filter can only be reduced so far. The problem is further exaggerated in high power applications since larger switches are needed, thus further limiting the maximum switching frequency and leading to larger LC filters.
These and other methods are known by those skilled in the art to reduce ripple and decrease response time, yet practical limits on switching frequency, switch size, LC component size, and ripple lead to practical limits for various use cases.
The following presents a simplified summary relating to one or more aspects and/or embodiments disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or embodiments, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or embodiments or to delineate the scope associated with any particular aspect and/or embodiment. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or embodiments relating to the mechanisms disclosed herein in a simplified form to precede the detailed description presented below.
One aspect of the present disclosure involves a power supply including a switch module comprising a first buck converter portion and a second buck converter portion, the first buck converter portion with a first output current magnetically coupled with a second output current of the second buck converter portion. The switch module may be an AWPG block as shown in
Another aspect of the present disclosure involves a power system, which may be for a plasma system, comprising a dynamic setpoint waveform generator comprising a controller providing a first sequence of pulses to a first switch pair and a second sequence of pulses to a second switch pair offset from the first sequence of pulses, the first sequence of pulses and the second sequence of pulses each based on a controllable set point (e.g., AC or modulating DC). The first switch pair may be coupled with a rail voltage, and comprise a first switch and a second switch interconnected at a common output operably connected with an input of a primary winding of a first transformer. An output of a secondary winding of the first transformer can be operably coupled with an output node. The second switch pair may be coupled with the same rail voltage, and the second switch pair can include a first switch and a second switch interconnected at a common output operably connected with an input of a primary winding of a second transformer. An input of a secondary winding of the second transformer can be coupled with an output of the primary winding of the first transformer, where an output of the secondary winding is operably coupled with the output node. Finally, the system may include a capacitor, or a filter, coupled with the common output, the capacitor or filter sized to allow a voltage at the common output to vary rapidly (e.g., fast enough to manage an arc response, e.g., <0.5 μs).
In yet another aspect, a power supply module may include a plurality of (N) buck converters each generating an output current magnetically coupled with an output of another one of the (N) buck converters, each buck converter switching at a fundamental frequency (f), wherein the magnetically coupled output of the (N) buck converters is responsive to an input set point at a frequency of N times the fundamental frequency to define an output waveform.
In another aspect, a power supply circuit is disclosed including a plurality of N, additive, interleaved, switchmode, power conversion stages, each having an output voltage and an output current. The circuit also includes a dynamic setpoint input to said power supply circuit. The circuit further includes an interconnect topology which connects said output voltage or output current from said interleaved, switchmode, power conversion stages into a summarized output responsive to the dynamic setpoint input. The summarized output responds instantaneously or approaches instantaneous response to changes in said dynamic setpoint input.
The interconnect topology for summarizing said interleaved, switchmode, power conversion stages may be accomplished with series connectivity by: powering each of the said interleaved, switchmode, power conversion stages from separate isolated input power supply rails; and connecting the outputs from each of said interleaved, switchmode, power conversion stage in series such that said output current from each stage is equal. The summarized output can be the sum of said output voltages of each of the said interleaved, switchmode, power conversion stages.
The process of summarizing said interleaved, switchmode, power conversion stages is accomplished in a parallel connectivity by: powering all of said N, additive, interleaved, switchmode, power conversion stages from a common input power supply rail, and, connecting the outputs from said interleaved, switchmode, power conversion stages to transformers configured to force the ac current from each of said interleaved, switchmode, power conversion stages to have the same ac current at all times, wherein said transformers are connected to provide a summarized output current which is the sum of the currents from each of said interleaved, switchmode, power conversion stages.
In another aspect of the disclosure, a power supply circuit is disclosed wherein each of a plurality of additive switchmode power conversion stages includes two switches, one coupled to a high voltage rail, and one coupled to a low voltage rail, and having a single pulse-width modulation output taken from between the two switches, the low voltage rails of all but one of the plurality of additive switchmode power conversion stages coupled to outputs of others of the plurality of additive switchmode power conversion stages, and a remaining low voltage rail providing the summarized output.
In yet another aspect of the disclosure, a power supply circuit is disclosed wherein each of a plurality of additive switchmode power conversion stages includes two switches, one coupled to a high voltage rail, and one coupled to a low voltage rail, and having a single pulse-width modulation output taken from between the two switches, the single pulse-width modulation outputs added together via a system of interlinked transformers providing the summarized output. The interlinked transformers can force the AC current from each of said interleaved, switchmode, power conversion stages to have the same AC current at all times.
Yet another aspect of the disclosure can be described as a switchmode power converter having an input and an output, wherein, the output tracks the input instantaneously after only inherent component delays.
Some embodiments of the disclosure may be characterized as a method of providing varying DC power to a plasma load to carry out a plasm processing recipe, the method comprising: providing a plurality of N, additive PWM power conversion stages, each having an inherent delay and each having a pulse width modulated output; providing a reference waveform, VR, to the power supply circuit; providing a dynamic setpoint input to the power supply circuit, wherein a ratio of a dynamic setpoint voltage, VS, at the dynamic setpoint input, over a reference waveform, VR, equals an input voltage ratio, VS/VR; providing an interconnect topology between the plurality of additive PWM power conversion stages, the topology summarizing output voltages or currents from the plurality of additive PWM power conversion stages into a summarized output, providing the summarized output to a load; and adjusting the dynamic setpoint voltage and causing the summarized output to track the dynamic setpoint voltage instantaneously within VRI of the input voltage ratio VS/VR. This method can further include providing a filter between the summarized voltage output and the plasma load, the filter having a capacitance <40 nF.
Some embodiments of the disclosure may be characterized as a flash power converter with an arbitrary output. The power supply circuit can include a plurality of N, additive, interleaved pulse-width modulated (PWM) power conversion stages, a setpoint input, and an interconnect topology between the plurality of additive interleaved PWM power conversion stages. The plurality of N, additive, interleaved pulse-width modulated (PWM) power conversion stages can each having an output and a switch within each stage. These switches can have a fundamental switching frequency, f. The setpoint input can be configured to receive a dynamic setpoint waveform. The interconnect topology can connect the outputs of the plurality of additive interleaved PWM power conversion stages into a summarized output. In this embodiment, the current output of each of the plurality of additive PWM power conversion stages is the same. The voltage at the summarized output is a sum of an output voltage from each of the plurality of additive interleaved PWM power conversion stages. The summarized output can be configured to respond to the dynamic setpoint waveform at a frequency greater than the fundamental switching frequency f to define an output waveform.
Other embodiments of the disclosure may also be characterized as a flash power converter with an arbitrary output. The flash power converter can include a plurality of N, additive pulse-width modulated (PWM) power conversion stages, a reference input to the flash power converter, a dynamic setpoint input to the flash power converter, an interconnect topology, and a summarized output. The plurality of N, additive (PWM) power conversion stages can have inherent component delays and can each have a pulse width modulated output. A ratio of the dynamic setpoint waveform, VS, at the dynamic setpoint input divided by a peak-to-peak voltage of the reference waveform, VR, equals an input voltage ratio, VS/VR. The interconnect topology can be arranged between the plurality of additive PWM power conversion stages. The interconnect topology can summarize output voltages or currents from the plurality of additive PWM power conversion stages into a summarized output voltage, VOUT. The summarized output can have a ripple voltage, VRI, where the ripple voltage, VRI, is a full peak-to-peak output voltage range, VT, divided by N. The summarized output voltage, VOUT, can track the dynamic setpoint waveform, VS, where the summarized output voltage, VOUT, responds to said dynamic setpoint waveform, VS, such that after the inherent component delays, the summarized output voltage, VOUT, is instantaneously within the ripple voltage, VRI, of the input voltage ratio, VS/VR, times the full output peak-to-peak voltage range, VT, of the summarized output voltage, VOUT.
In one aspect of the disclosure, a power converter is disclosed including a phase shifted pulse-width modulation driver system and two or more switching converter modules. The phase shifted pulse-width-modulation driver system can be configured to receive a signal to be synthesized. The two or more switching converter modules can be arranged in series and can be configured to receive switching control signals from the phase shifted pulse-width-modulation driver system and provide a summarized output to a load. Each of the two or more switching converter modules can include an input, an output, an isolated DC power supply, and a unipolar or bipolar switching circuit. The unipolar switching circuit can include N pairs of switches, and a capacitor arranged between every two pairs of the N pairs of switches. The bipolar switching circuit can include 2N pairs of switches with 2(N−1) capacitors arranged between the 2N pairs of switches. The switching control signals can provide offset pulse trains to each of the N or 2N pairs of switches.
In another aspect of the disclosure, a power converter is disclosed including two or more switching converter modules each including an input, an output, two or more switch pairs, and an isolated DC power supply. The two or more switching converter modules can be coupled in series and provide a summarized output for the power converter. The summarized output can include a summation of voltage or power from the two or more switching converter modules. Each two adjacent switch pairs can be separated by and coupled to a capacitor. The isolated DC power supply can be arranged between a first pair of the two or more switch pairs in a unipolar topology, or between two adjacent pairs of the two or more switch pairs in a bipolar topology. Each switch pair is configured to be driven by a pulse train that is offset from pulse trains for other switch pairs.
In another aspect of the disclosure, a power converter is disclosed having a controller and two or more switching converter modules. The controller can be configured to receive an input signal for conversion to an output signal to be provided to a load. The controller can be further configured to provide a reference waveform and a signal to be synthesized. The two or more switching converter modules can be arranged in series such that one of the two or more switching converter modules provides a summed output of the two or more switching converter modules to the load. Each of the modules can include a module input, a module output, N pairs of switches, a capacitor coupled between every two pairs of the N pairs of switches, and an isolated DC power supply. The module output can be configured to provide N+1 levels of voltage or power to a next switching converter module or to the load. The number of switch pairs, N, is two or more, and the N pairs of switches can be arranged between the module input and the module output. The two or more pairs of switches can be driven by a switching pattern generated, for instance, by a phase shifted pulse-width-modulation driver system arranged between the controller and the two or more switching converter modules. The capacitors can each be coupled between a first switch pair and a next switch pair (i.e., between two pairs of switches or between four switches). The number of capacitors can be one less than the number of switch pairs, or N−1. The isolated DC power supply can be arranged between a first of the pairs of switches in a given module such that states of the two or more pairs of switches determines an amount of the DC power supply voltage or power reaching the output.
Various objects and advantages and a more complete understanding of the present disclosure are apparent and more readily appreciated by referring to the following detailed description and to the appended claims when taken in conjunction with the accompanying drawings:
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
Preliminary note: the flowcharts and block diagrams in the following Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, some blocks in these flowcharts or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Aspects of the present disclosure are directed to an N-phase flash interleaved bi-directional summarized power converter (“flash power converter”) with a dynamic output, or the ability to track a dynamic setpoint with a faster response time than prior art converters (e.g., faster than a fundamental switching frequency, f, of the switches used to perform the switchmode power conversion, or faster than a limit set by the Nyquist criteria). The nature of the flash power converter rests on the inventors' recognition that a PWM output of each comparator in such a multi-phase power converter has a duty cycle that is ideally instantaneously responsive to a dynamic setpoint waveform. In one embodiment, the flash power converter can convert (increase or decrease) an amplitude of a dynamic setpoint waveform without delay (i.e., without delay beyond inherent device delays such as switching delays). In this sense, the present disclosure presents a flash power converter that “instantaneously” tracks a dynamic setpoint waveform, and can do so even where very high voltages and currents are needed (e.g., >500 V and >500 A).
Each of the N phases can include a dynamic setpoint waveform and a recurring reference waveform (e.g., a ramp or triangle wave or a sine wave to name a few non-limiting examples) (herein referred to as a “reference waveform”). The setpoints for each of the N comparators can be the same (just the dynamic setpoint waveform), but the reference waveforms are offset by N/360 degrees for each of the N comparators. So, for a 100 phase flash power converter, this would mean a 3.6 degree phase delay between comparators. Each comparator produces a single PWM output that is used to drive a switchmode power conversion stage of each phase. A high PWM output can turn the upper of a pair of switches on and a lower of the pair off, and a low PWM output can turn the upper switch off and the lower switch on. The N outputs of the N comparators can then be summarized into a summarized PWM output via series connections between the phases (e.g., see
While
Typically, power converters passing high voltages and/or high currents use large output filters (i.e., large inductive and capacitive components) to smooth out ripple that is inherent in switchmode power converters. These large filters typically add significant delay to a conversion circuit's ability to quickly track a dynamic setpoint waveform (i.e., response time).
At the same time, high power switchmode power converters typically use large switches to handle high voltage and/or current, and these switches typically have a slower fundamental switching frequency (e.g., ˜50 kHz to 400 kHz in plasma processing applications) than switches used in low voltage applications (e.g., power converters for microprocessors). What is more, it has long been held that the maximum unity gain crossover frequency of switchmode power supplies is limited by the Nyquist criteria—one half the fundamental switching frequency, f, of switches in the switchmode power supply (Kester, Walt. What the Nyquist Criterion Means to Your Sampled Data System Design. Analog Devices, MT-002). However, in practice, the usable switching frequency is even lower, due to changes in the load impedance, temperature, component variation, etc., and is often closer to f/4 or f/5.
As such, high power switch mode power converters worsen a problem seen in all power converters, even low powered ones; the output power lags behind changes in the setpoint—or fails to track the setpoint without noticeable delay. This disclosure drastically reduces that delay and approaches what one could call an “instantaneous” output response to changes in the power converter setpoint (or near-instantaneous tracking of a dynamic setpoint waveform). In other words, the herein disclosed flash power converter provides greatly improved response time over the prior art.
Such a power converter can be useful in plasma processing, where arcing commonly depresses fabrication yield. Arcs, like lightning in nature, actually grow in intensity over a short period of time (e.g., ˜30 μs). Known plasma power supplies, for instance, the PINNACLE, AMS, DMS, and SMS AP, supplied by ADVANCED ENERGY of Fort Collins Colo., can reduce and even absorb power during an arcing event (e.g., see U.S. Pat. Nos. 8,217,299 and 8,552,665). However, these existing power supplies are limited in their ability to mitigate arcs due to the above-mentioned delays—the inability of a power converter's output to instantly react to changes to the setpoint, especially where high voltages and currents are used as is typical in plasma processing.
This disclosure's reduction, and near elimination, of delay between a change in the power supply circuit's setpoint and a resulting change in the output, greatly enhances the ability to reduce and even absorb power during an arcing event, as well as generate highly dynamic waveforms with near instantaneous response to setpoint. For instance, where prior art power converters imperfectly produce a square wave output (e.g., having beveled or ‘soft’ corners) or produce a slightly angled slope when there is a sharp voltage jump, the herein disclosed flash power converter produces much sharper square waves and nearly vertical jumps between voltages. This near instantaneous response to a dynamic setpoint waveform, even where high current and voltage are needed, have wide ranging applications in electric vehicle traction, powering an RF conversion stage, and reducing power supply size and stored energy, to name a few non-limiting examples.
Additionally, those in the plasma processing space have long sought to avoid or reduce the size of capacitors arranged between plasma power supplies and the plasma. Again, returning to the challenges of arcing, when an arc occurs, capacitors can dump their energy into the arc, thereby enhancing rather than reducing the arc. Thus, there has long been a desire to reduce the size of such capacitors—yet large ones have often been needed to smooth out ripple in a typical power converter output. The flash power converter herein disclosed achieves significant reduction in the ripple and thereby a significant if not complete elimination of the filtering capacitor. This in turn greatly reduces the need to design systems that mitigate the capacitor dumping power into arcs (e.g., in plasma processing applications).
On a similar note, power converters often also include feedback to help make small adjustments to the switching duty cycle to better achieve an output corresponding to the dynamic setpoint waveform. However, such feedback is also limited by the Nyquist criteria. Accordingly, feedback for power converters has an upper limit on the frequency of output sampling. This disclosure breaks this limitation and enables sampling frequencies above the Nyquist criteria, and even above the fundamental switching frequency, f, of the switches.
In this disclosure, a reference waveform generally refers to a repetitive waveform, often a triangle, sawtooth, or ramp waveform. Other waveforms could also be implemented with known adjustment to the transfer function, including non-repetitive waveforms. The reference waveform may be a voltage, current, or combination of the two.
In this disclosure, a dynamic setpoint waveform generally refers to a signal representing a desired output of a power conversion circuit. The dynamic setpoint waveform may be modified by feedback or other factors, and can be repeating or non-repeating. The dynamic setpoint waveform may be a voltage, current, or combination of the two. The dynamic setpoint waveform can be sinusoidal, stepped, triangle, combinations of waveforms, complex profile waveforms, or any imaginable waveform at any frequency. This disclosure often uses a sinusoidal dynamic setpoint waveform to illustrate the effects of the flash power converter, but this is illustrative only, and the dynamic setpoint waveform is in no way limited to sinusoidal functions.
In this disclosure, an input voltage ratio, VS/VR, generally refers to a ratio of an amplitude of the dynamic setpoint waveform, VS, over a peak-to-peak amplitude of the reference waveform, VR. It should be noted that the input voltage ratio, VS/VR, is an instantaneous relationship of these two values.
In this disclosure, the output ratio generally refers to the value of the summed PWM output voltage or current at a point in time compared to the peak-to-peak voltage or current of the summarized PWM output voltage.
In this disclosure, inherent delay generally refers to signal delay attributed to comparators, drivers, and power conversion devices, such as switches and interconnects. It can include delays in drivers and power switches, but not delays caused by energy storage devices such as inductors, capacitors or filters. A driver circuit for a power conversion stage may have a latency or delay between the time an input changes and the time that an output changes. This delay could exist over a broad range depending on the power range or voltage isolation, for example. Common inherent delays for a switchmode power converter are 1-30 ns. A switch in the switchmode power converter may have a delay between when it receives a switching signal and when it actually becomes primarily conducting or primarily open. These transition times between open and closed and vice versa could be on the order of nanoseconds or microseconds.
Specific structures and control methods for achieving the above-mentioned advances will be described below.
In some embodiments of the disclosure, a flash power converter 306 is disclosed having a dynamic setpoint input, a reference waveform input, a driving portion, a serial switching and summation portion, and a summarized PWM output. The flash power converter 306 can receive a dynamic setpoint waveform from a setpoint waveform generator 304, and a reference waveform (e.g., a sawtooth function) from a reference generator 302, and output a summarized PWM output. The reference generator 302 may provide a sawtooth reference waveform as shown, for instance, in
The reference generator 302 and the setpoint waveform generator 304 may form a part of an optional controller 301. The flash power converter 306 may also receive DC power from an optional DC power supply 312 or may include one or more internal DC supplies.
The flash power converter 306 can compare the reference waveform and dynamic setpoint waveform, for instance via a series of phase offset comparators, to drive one or more switching sections, and sum the outputs thereof to form a summed pulse-width modulated (PWM) output that roughly mimics the dynamic setpoint waveform, but at a different voltage and/or current. This summed PWM output can then be provided to a load 310, where the summed PWM output is optionally smoothed via signal conditioning circuitry 308 such as an LC filter. However, in some cases the ripple may be sufficiently small to avoid the need for the signal conditioning circuitry 308. The optional DC power supply 312 may have a negative output, a ground, or may be a floating ground depending on the implementation. There is a characteristic of this simple circuit which is generally not known in the power conversion world: if the dynamic setpoint waveform changes, the output duty cycle changes instantaneously in response to the setpoint change.
In an embodiment, the optional controller 301 can be arranged within or as part of the flash power converter 306. In this or other embodiments, the flash power converter 306 can include a phase shifted pulse-width-modulation driver system, such as the one shown in
A six-phase example of a “serial” variation of the flash power converter 306 is shown at least at
In both the series and parallel variations, the driving portion 412 translates the dynamic setpoint waveform, in association with the reference input, to a set of two or more pulse-width modulated (PWM) signals that are interleaved or phase offset from every other set. Each of the two or more PWM signals is provided to a different “phase” within either the serial switching and summation portion (e.g.,
Each phase can include a half-bridge (
The PWM output from each phase is summed with all other PWM outputs in either: (1) a serial fashion, where an output node between the switches in all but one phase is coupled to a low voltage side of a next DC power supply or a next low voltage rail and the remaining output node is the summarized PWM output; or (2) a parallel fashion, where an output node between the switches in all phases is passed to a separate but magnetically-coupled transformer of a parallel summation portion. In the latter case, each of these magnetically-coupled transformers includes (1) an input to a primary winding coupled to the PWM output of one of the phases, (2) an input of a secondary winding coupled to an output of a primary winding of another of the magnetically-coupled transformers, and (3) an output from the secondary winding coupled to all the other outputs of secondary windings to form the summarized PWM output.
In both variations, the summarized PWM output can be provided to a load and optionally passed through signal conditioning circuitry, such as a filter, before reaching the load.
The speed of the flash power converter's response to changes in the dynamic setpoint waveform may be a function of the number of phases, N. Specifically, the flash power converter's sampling frequency, or number of output voltages that can be achieved as a function of time, can be found as f*N, where f is the fundamental switching frequency of the switches used in each phase. So, for example, with 24 phases each running at f=200 kHz it is possible to adjust the summarized PWM output as fast as 24*200 kHz, or 4.8 MHz, where the prior art is limited to switching of 40 kHz. As seen, the improvement in response time to a dynamic setpoint waveform is profound.
While both the parallel and serial variations provide substantial advantages over the prior art, the parallel variation sees each phase output current being magnetically coupled to the current output of another phase. Each phase is connected to another such that output currents from all phases are the same. However, since a transformer is arranged between the switches and the load, only AC current is equalized between the phases. Any DC or low frequency AC current is blocked by the transformers, which can lead to DC or low frequency AC imbalances between the phases. Feedback may be needed to help balance the phases—added complexity and signal degradation that the serial version does not suffer from.
The dynamic setpoint input 401 and the reference waveform input 407 are each coupled to an N number of comparators 418 within the driving portion 412, where the comparators 418 are time-sequenced. In other words, a phase delay (e.g., 1/N) is applied to the reference waveform between each comparator 418, such that each comparator 418 sees a different phasing of the reference waveform (i.e., the PWM pulse trains reaching each set of switches is interleaved). So, for example, in a six phase implementation, as shown in
While a single PWM output of a comparator with these inputs has been known, the inventors recognized that hidden in the single PWM output is the fact that at any moment the PWM output has a duty cycle that is equal to the input ratio—not just an up or down—but a greyscale value between and including one and zero that is equal to a ratio of the dynamic setpoint waveform over the reference waveform. Said another way, even where the PWM output appears to be a high or a low, and a given pulse appears to have a given duty cycle once the whole pulse has been plotted, in reality, the duty cycle may be changing throughout that pulse.
This revolutionary discovery may be better understood with reference to
The single PWM outputs 405 from each comparator, are each passed to a respective driver 419. The drivers 419 can take a logic level signal from a respective comparator 418 and boost them to a high current signal at a voltage suitable for driving high power switches (e.g., 420). In
The switches 420 are shown in half-bridge configurations in
The first phase 430 includes a ground connection 424 to the lower of its two switches 420, and thus couples its output node 414 to ground 424 when the lower switch 420 of the first phase 430 is in the on-state. The topmost phase in the figure can be referred to as the sixth phase 440 (or output or last phase). The other phases can be referred to as the second 432, third 434, fourth 436, and fifth phases 438. The output phase 440 can include an output node 414 that provides the summarized PWM output 403—it is not coupled to any other phases, but is instead provided to the load 410, and optionally filtered via optional signal conditioning circuitry 408.
An example of the summarized PWM output 403 is shown in
Additionally, the frequency of the PWM signal within each step may be observed to be N times the fundamental switching frequency, f, of any one of the switches 420 (e.g., six times the fundamental frequency, f, of 200 kHz or 1.2 MHz). Described another way, for a flash power converter having six phases, and the switches switching at 200 kHz, the summarized PWM output tracks the dynamic setpoint waveform with only a delay inherent to devices in the power chain (i.e., otherwise an instantaneous tracking of the input setpoint). The summarized PWM output 403 tracks the dynamic setpoint waveform to within 1/N (e.g., ⅙) times the peak-to-peak voltage of the summarized PMW output 403, and has a ripple PWM instantaneously following the dynamic setpoint waveform at a frequency of 1.2 MHz. As such, in some embodiments, the switching speed of each of the plurality of additive PWM power conversion stages is 20-800 kHz. In some embodiments, greater than 150 kHz switching speeds can be achieved even where a filter is arranged between the flash power converter and the load.
Consider now a flash power converter having 24 interleaved power conversion phases. The output ripple in this case is reduced from ⅙ to 1/24. The ripple would have a PWM frequency of N*f or 24*200 kHz=4.8 MHz. Along these same lines, while prior art methods would need to apply filtering to smooth the ripple, where the filtering was limited by the switching frequency of a given switch (e.g., a large LC filter), the present disclosure enables a much higher “effective switching frequency” from the standpoint of filtering-here filtering would be limited to 4.8 MHz. Since higher frequencies can be filtered with smaller filter components, the disclosed summarized PWM output is more easily filtered than prior art power conversion outputs, despite using similar switching devices (though a radically different topology and driving circuitry). In some cases, to address the reduced size ripple and increased frequency ripple of the summarized PWM output over prior art power conversion outputs, the necessary filter can be reduced by a factor of N2.
It should be understood that for many applications it can be enough to simply increase the number of power conversion stages to the point that no filter is required.
Where an output filter is necessitated, a feedback loop may be used, in which case the feedback can be taken prior to the output filter. The feedback loop can be arranged between the summarized output and the dynamic setpoint input. In this way the unity gain crossover frequency of the feedback is not related to conventional limitations such as switching frequency, output filter or Nyquist criteria. In other words, the unity gain crossover frequency can be greater than ⅕th of the fundamental switching frequency or can be greater than ½ of the fundamental switching frequency or can be greater than the fundamental switching frequency.
Referring back to
Each phase 430-440 may include its own DC power supply 422 as shown. Each DC power supply 422 may be isolated and floating. Each DC power supply 422 may include a positive side and a negative side. The positive side of each DC power supply 422 can be coupled to a first switch of the switch pair 420 in each phase. The negative side of each DC power supply 422 can be coupled to a second switch of the switch pair 420 in each phase. Each switch can have an output coupled to the output 414 and an input, where the input for the first switch is coupled to the positive side of the corresponding DC power supply 422 and the input for the second switch is coupled to the negative side of the corresponding DC power supply 422. The input to the second switch of phase 430 is coupled to ground. The input to the second switch of the other phases is coupled to an output 414 of a previous phase (e.g., a lower phase in
Although each phase 430-440 is shown with a single pair of switches, and an isolated DC power supply, in other embodiments, each phase 430-440 may include two or more pairs of switches with a capacitor between every two pairs of switches and a single isolated DC power supply as shown in the exemplary switching converter modules shown in
The driving portion 412 is one example of the phase shifted pulse-width-modulated driver system 2506 shown in
Various components in the flash power converter 400 may have inherent delays. First, the comparators 418 may have a delay of a few nanoseconds. The drivers 419 may have a delay of 5-30 ns. The power conversion switches 420 may have a delay of 20 ns before beginning to transition. The transition time of the switches 420 may be 10 n to a few microseconds. All these inherent delays are related to power levels and types of devices. For one example, let us assume the switches 420 are SiC FETs capable of switching 40 A at 1200 V. The delay time of these switches 420 may be on the order of 15 ns. The switching time may be on the order of 50 ns. The driver 419 may have a delay of 20 ns. The total inherent delay for this example may be on the order of 100 ns.
The summarized PWM output 403 or 803 can have a ripple voltage, VRI. The ripple voltage, VRI, is the summarized PWM output voltage, VOUT(t), at a time t, divided by N (or
The summarized PWM output 403 or 803 can respond to the dynamic setpoint waveform at the dynamic setpoint input 401 such that after the inherent delays, the summarized PWM output voltage, VOUT(t), at time t, is instantaneously within the ripple voltage, VRI, of an input voltage ratio, VS/VR(t), at time t, times the full peak-to-peak output voltage range, VT (for either serial or parallel topologies). In equation form, the summarized PWM output voltage, VOUT(t), is instantaneously within the ripple voltage, VRI, of
The input voltage ratio, VS/VR(t) is a ratio of the dynamic setpoint waveform, VS, at time t, at the dynamic setpoint input 401, over a peak-to-peak voltage of the reference waveform, VR, at the reference waveform input 407. In equation form, the summarized PWM output voltage VOUT(t), at the time t is (after inherent component delays):
Where N is the number of phases and VIR is the input voltage ratio, VS/VR(t).
In some conventional designs for use with a DC output, output capacitance is relatively large to assist in maintaining a stable DC voltage at the output. The large output capacitance is also used to maintain a steady output in the presence of load changes such as associated with a rapid change in current draw (increase or decrease), as would be seen in power a microprocessor for instance. In the embodiment of
The capacitive component 704, in some implementations, may also not be necessary. For instance when driving a speaker, or when sufficient phases, N, are implemented to produce negligible ripple at the summarized PWM output, the capacitive component 704 may not be needed. As another example, where the flash power converter is used to power a subsequent power conversion stage having its own signal conditioning circuitry or filter, the capacitive component 704 may not be needed. For instance, if the flash power converter is used to provide the power for an RF power conversion stage, the low amplitude, high frequency ripple may be negligible and/or removed by the subsequent power stage's filter(s). Along these same lines, the frequency of output ripple is increased by a factor of N, and thus the frequency to be filtered is much higher than a conventional power converter. For instance, assume a switching frequency of the switching pairs to be 200 kHz and 24 phases—the output ripple will occur at 4.8 MHz and be 24 times smaller than a conventional switchmode power converter, and thus the filter may be exceedingly small.
In the specific case of a plasma power system, this disclosure's ability to utilize a relatively smaller capacitive element 704 is advantageous in providing less arc energy in an arc situation within the chamber. As noted earlier, the proposed flash power converter facilitates very fast arc response. Generally speaking, the power may be momentarily disabled or quickly switched to the opposite polarity when an arc is detected within the chamber. Such actions are meant to quickly extinguish the arc, and then allow the plasma to be reignited and returned to normal plasma operation. The dramatically smaller capacitive element 704 allows for much faster power shut down and stores dramatically less arc energy. In general, having complete control of the waveform being impressed on a plasma provides many advantages for ignition, stability and arc management as one skilled in the art will appreciate.
The control electronics, including the comparators and phase delay components, along with switches and drivers can be implemented in analogue or digital domains.
The single PWM outputs from each comparator, are each passed to a respective driver 819. The drivers 819 provide switching signals to switches 820 in the parallel switching portion 815. In particular, the drivers 819 translate the single PWM signals into two driving signals that are passed to the switches 820 (or switch pairs) of each phase (or four driving signals that are passed to the switches 820 of each phase in a full-bridge configuration—see
The switches 820 are shown in half-bridge configurations in
The transformers 816 form coupled inductors where the term “coupled inductor” refers generally to the output current of one phase being magnetically coupled with the output current of another phase. In one example, to achieve magnetic output current coupling, the primary winding of one phase is connected with the secondary winding of another phase. In the example of
In use, the gate drive pulses for each switch pair are delayed or offset relative to each other (e.g., by 1/N of the fundamental switching period). By action of the interconnected transformers, the currents from each phase are magnetically coupled so that an increase in current in the sixth phase 840 when the sixth switch pair is active, causes current to flow to and be induced in the fifth transformer of the fifth phase 838, even though its switch pair is not active (e.g., the upper switch connected to the high voltage rail is open), and so on to the subsequent transformers. The same sequence holds when each phase leg is active, current from the associated transformer cascades (flows to and is induced in) to the sixth interconnected transformer, and so on. The cascading current continues as various phases are active or inactive.
As an example, if each phase, of a six-phase flash power converter, provides about 17 A at a rail voltage of 750 V, the summarized PWM output 803 will swing between 0 and 750 V at about 100 A, and can provide 75 KW power.
An example of the summarized PWM output 803 is shown in
Additionally, the frequency of the PWM within each step in
Consider now a flash power converter having 24 interleaved power conversion phases. The output ripple in this case is reduced from ⅙ to 1/24. The ripple would have a PWM frequency of N*f or 24*200 kHz=4.8 MHz. Along these same lines, while prior art methods would need to apply filtering to smooth the ripple, where the filtering was limited by the switching frequency of a given switch (e.g., a large LC filter), the present disclosure enables a much higher “effective switching frequency” from the standpoint of filtering—here filtering would be limited to 4.8 MHz. Since higher frequencies can be filtered with smaller filter components, the disclosed summarized PWM output is more easily filtered than prior art power conversion outputs, despite using similar switching devices (though a radically different topology and driving circuitry). In some cases, to address the reduced size ripple and increased frequency ripple of the summarized PWM output over prior art power conversion outputs, the necessary filter can be reduced by a factor of N2.
It should be understood that for many applications it can be enough to simply increase the number of power conversion stages to the point that no filter is required.
Where an output filter is necessitated, a feedback loop may be used, in which case the feedback can be taken prior to the output filter. In this way the unity gain crossover frequency of the feedback is not related to conventional limitations such as switching frequency, output filter or Nyquist criteria.
Various components in the flash power converter 800 may have inherent delays as described relative to
Although
Output current of the first switch pair (first phase) 1804A is provided to a first transformer 1814A. Similarly, output current of the second switch pair (second phase) 1804B is provided to the first transformer 1814A. Like the interconnection of transformers shown in
The third transformer 1814C combines the currents from the first and second transformers 1814A and 1814B and provides a summarized PWM output to the load, which includes a summed current of all phases. Although not shown, conditioning circuitry or filtering may be arranged between the third transformer 1814C and the load. One advantage, among many, is a power supply conforming with aspects of the present disclosure may produce a complex output waveform suitable to driving various possible loads such as a plasma, one representative example of such a waveform being illustrated between the load and the third transformer 1814C. This example output waveform is based on the dynamic setpoint waveform within the controller.
With either the serial or parallel topology, half or full-wave switch configurations, or any other variation of the disclosed flash power converter, a wide variety of distinct power supply types may be replaced with the flash power converter operating under a control scheme for whatever power supply is being replaced. In the case of plasma systems, for example, the highly controllable and configurable nature of the flash power converter provides for an ability to alter process (how the plasma is ignited and controlled, particularly considering complicated power waveforms) without concern for the hardware of the power supply. For example, using a flash power converter, a process engineer may effectively “draw” a desired waveform as an input waveform or to modify a waveform for a plasma, and execute the process.
In the case of a MOSFET based switch pair used in the phases of
As the number of such summarized, interleaved switchmode power conversion stages/phases increases, the summarized PWM output has smaller and smaller steps (e.g.,
Besides the ability to produce highly controllable and arbitrarily shaped output waveforms that nearly instantly track a dynamic setpoint waveform, the disclosed flash power converter provides for such converters to be interconnected in various ways to produce various multiples of the output of any converter.
The serial and parallel designs described thus far improve upon the prior art, but still have their own shortcomings. For instance, the parallel version can suffer from current imbalance between the phases, leading to a need for circuits and algorithms to minimize differences between currents in each phase. And, some manufacturers may not desire to use a large number of isolated DC power supplies in the serial version. One alternative is to use a switching converter module having a plurality of pairs of switches, and capacitors between each two pairs of switches, powered by a single isolated DC power supply (e.g., see
The inventor realized that decreasing the number of switches and capacitors in a switching converter module would ease the burden of voltage balancing and that decreasing a number of phases in the serial variation would make that solution more practically appealing. To do this, a “hybrid” topology was developed that combined aspects of both the single switching converter module and the serial variation (described earlier). This hybrid includes multiple switching converter modules linked in series (see
The signal at the input 2524, or the signal to be synthesized, may also be referred to as a set point or controllable set point.
Each switching converter module 2508 can include an isolated DC power supply 2510 and N pairs of switches with N−1 capacitors arranged between those switches for a unipolar design or with 2(N−1) capacitors arranged between those switches for a bipolar design (allowing negative as well as positive output). The arrangement of switches and capacitors can be referred to as a switching circuit 2512. Exemplary switching circuits 2512 and respective isolated DC power supplies can be seen in
The power converter 2500 can include an input 2524 configured to receive a signal to be synthesized at an output 2526 and passed to a load 2516. The synthesized signal can optionally be passed through signal conditioning circuitry 2514 (e.g., a filter), and the optional signal conditioning circuitry 2514 can be arranged within, or as part of, the power converter 2500 (as shown), or can be arranged external to the power converter 2500. Two non-limiting examples of the signal conditioning circuitry 2514 can be seen in
The signal to be synthesized can include any signal (e.g., a voltage) that is to be converted to a higher or lower voltage or power before reaching the load 2516. To begin the conversion or signal synthesizing process, the signal to be synthesized can optionally be received at a controller 2501, and optionally at a setpoint waveform generator 2504 similar to the setpoint waveform generators 304 and 404. However, in many cases, the signal to be synthesized can pass into the power converter 2500 and straight to a phase shifted pulse-width-modulation driver system 2506. In other words, some embodiments do not include a controller 2501 and instead just a reference generator 2502, with an input signal to the power converter 2500 (or signal to be synthesized) passing straight to the phase shifted pulse-width-modulation driver system 2506.
The setpoint waveform generator 2504, if implemented, can modify the signal, e.g., increasing a voltage thereof, and pass the signal to be synthesized to the phase shifted pulse-width-modulation driver system 2506 (“driver system”) and the driver system 2506 can use this signal as a setpoint, and along with a reference signal from a reference generator 2502 of the controller 2501, can generate switching control signals for the switch pairs of the switching converter modules 2508 (e.g., interleaved sequences of pulses, where each switch pair receives one of these sequences of pulses). The switching control signals may include a plurality of pulse sequences, each one of which is provided to a switch pair and drives that switch pair in the switching converter modules 2508, and each sequence interleaved with sequences of pulses delivered to other switches both in the same switching converter module 2508 and in other modules 2508. The pulse sequences can be generated based on a target output waveform (i.e., on the input signal or signal to be synthesized). These switching control signals can be passed via digital links 2518 that may include signals for a plurality of switch pairs. The digital links 2518 may take many forms including a communication path for each switch, or fewer paths than the number of switches, but using a multiplexing algorithm. Other variations known to those of skill in the art for passing switching signals to the switch pairs can also be used.
The driver system 2506 can include a topology of delay components, comparators, and drivers as shown in
In
In these three examples, one can see that the more switch pairs and capacitors used in a switching converter module 2508, the smaller the contribution each switching pair makes to an output of the switching converter module 2600, and the greater the resolution of output voltage or power. Additionally, the greater the number of switches and capacitors, the more average voltage drops across each switch on the higher-voltage side of the converter module (e.g., S1, S2, S3 are on the higher voltage-side). Thus, where N=2, the switches can be selected to handle a smallest average voltage drop (i.e., a larger Vdc can be selected for given switches without damaging them than if larger numbers of switch pairs are used). Larger numbers of switch pairs and capacitors also lead to greater overhead for voltage balancing between the capacitors. Thus, in terms of voltage balancing needs,
The duty cycle of each switch pair may vary over time as the drive system 2506 controls these duty cycles to achieve a synthesized signal at the output 2526 that accurately synthesizes the input at 2524 with a minimum error. In other words, a ratio of the synthesized signal at the output 2526 over the signal to the synthesized at the input 2524 should be less than or equal to 1.
Referring back to
These illustrations show just a few of the many variations of a switching converter module 2508, and one of skill in the art should appreciate that any number of two or more switch pairs can be implemented in a given module 2508.
A more generalized view of the switching converter modules 2508 can be seen in
wherein i is an index running from 1 to n.
In the bipolar generalization, there are 2N switch pairs S1 through S2N, where N is a number of switch pairs on one half of the topology, or on a unipolar section of the topology. The variable, n, represents a number of switch pairs between S2 and SN−1 as well as between SN+2 and S2N−1. For instance, where the number of switch pairs is 20, n would be 6, since n is seen on both sides of the isolated DC power supply. Each added switch pair, n, also comes with a respective capacitor having an average voltage
wherein i is an index running from 1 to n.
Similarly, for the unipolar topology, and given a number of switch pairs N, the number of capacitors is N−1, and the number of output voltage or power levels is N+1. So, for a three-level topology (N+1=3), two switch pairs and one capacitor could be used (e.g.,
Typically, the voltage limit of the switches is not a design variable, while the number of switches, N, and the voltage or power of the isolated DC power supply are. Therefore, to find an optimum number of switch pairs, N, a designer can select a desired isolated DC power supply voltage (e.g., Vdc) or power, take the known switch power or voltage limit, and solve for a number of switches N. Alternatively, one can select a number of switches, N, and solve for the isolated DC power supply voltage or power. For instance, the greater the number of switches, the greater the effective switching frequency. The number of switching converter modules, M, may also factor in. Increasing the number of switching converter modules, M, and keeping a number of switches per module constant, the effective switching frequency of the power converter can be increased. Further, since a maximum voltage or power contribution that each switching converter module can make is Vdc, increasing the number of modules, M, increased the maximum power converter output. If this were attempted by using more powerful isolated DC power supplies, then heavier-duty switches would be needed. Hence, increasing the number of modules, M, is a less expensive means of increasing the converter's headroom.
For purposes of this disclosure, an “isolated” DC power supply is one that does not have a direct electrical connection to another DC power supply. Any intervening electrical device between one DC power supply and another causes those two supplies to be isolated.
The switches of
It should be noted that all waveform diagrams disclosed herein can be referenced to ground or a floating reference.
Turning to
In one implementation, the electronic device 1900 includes a display unit 1902 configured to display information, such as a graphical user interface, and a processing unit 1904 in communication with the display unit 1902 and an input unit 1906 configured to receive data from one or more input devices or systems. Various operations described herein may be implemented by the processing unit 1904 using data received by the input unit 1906 to output information for display using the display unit 1902. A controller my not include a display unit. Additionally, in one implementation, the electronic device 1900 includes units implementing the operations described with respect to the various figures.
Referring to
The computer system 2000 may be a computing system is capable of executing a computer program product to execute a computer process. Data and program files may be input to the computer system 2000, which reads the files and executes the programs therein. Some of the elements of the computer system 2000 are shown in
The processor 2002 may include, for example, a central processing unit (CPU), a microprocessor, a microcontroller, a digital signal processor (DSP), and/or one or more internal levels of cache. There may be one or more processors 2002, such that the processor 2002 comprises a single central-processing unit, or a plurality of processing units capable of executing instructions and performing operations in parallel with each other, commonly referred to as a parallel processing environment.
The computer system 2000 may be a conventional computer, a distributed computer, or any other type of computer, such as one or more external computers made available via a cloud computing architecture. The presently described technology is optionally implemented in software stored on the data stored device(s) 2004, stored on the memory device(s) 2006, and/or communicated via one or more of the ports 2008-710, thereby transforming the computer system 2000 in
The one or more data storage devices 2004 may include any non-volatile data storage device capable of storing data generated or employed within the computing system 2000, such as computer executable instructions for performing a computer process, which may include instructions of both application programs and an operating system (OS) that manages the various components of the computing system 2000. The data storage devices 2004 may include, without limitation, magnetic disk drives, optical disk drives, solid state drives (SSDs), flash drives, and the like. The data storage devices 2004 may include removable data storage media, non-removable data storage media, and/or external storage devices made available via a wired or wireless network architecture with such computer program products, including one or more database management products, web server products, application server products, and/or other additional software components. Examples of removable data storage media include Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc Read-Only Memory (DVD-ROM), magneto-optical disks, flash drives, and the like. Examples of non-removable data storage media include internal magnetic hard disks, SSDs, and the like. The one or more memory devices 2006 may include volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and/or non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.).
Computer program products containing mechanisms to effectuate the systems and methods in accordance with the presently described technology may reside in the data storage devices 2004 and/or the memory devices 2006, which may be referred to as machine-readable media. It will be appreciated that machine-readable media may include any tangible non-transitory medium that is capable of storing or encoding instructions to perform any one or more of the operations of the present disclosure for execution by a machine or that is capable of storing or encoding data structures and/or modules utilized by or associated with such instructions. Machine-readable media may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more executable instructions or data structures.
In some implementations, the computer system 2000 includes one or more ports, such as an input/output (I/O) port 2008 and a communication port 2010, for communicating with other computing, network, or vehicle devices. It will be appreciated that the ports 2008-710 may be combined or separate and that more or fewer ports may be included in the computer system 2000.
The I/O port 2008 may be connected to an I/O device, or other device, by which information is input to or output from the computing system 2000. Such I/O devices may include, without limitation, one or more input devices, output devices, and/or environment transducer devices.
In one implementation, the input devices convert a human-generated signal, such as, human voice, physical movement, physical touch or pressure, and/or the like, into electrical signals as input data into the computing system 2000 via the I/O port 2008. Similarly, the output devices may convert electrical signals received from computing system 2000 via the I/O port 2008 into signals that may be sensed as output by a human, such as sound, light, and/or touch. The input device may be an alphanumeric input device, including alphanumeric and other keys for communicating information and/or command selections to the processor 2002 via the I/O port 2008.
In one implementation, a communication port 2010 is connected to a network by way of which the computer system 2000 may receive network data useful in executing the methods and systems set out herein as well as transmitting information and network configuration changes determined thereby. Stated differently, the communication port 2010 connects the computer system 2000 to one or more communication interface devices configured to transmit and/or receive information between the computing system 2000 and other devices by way of one or more wired or wireless communication networks or connections. Examples of such networks or connections include, without limitation, Universal Serial Bus (USB), Ethernet, Wi-Fi, Bluetooth®, Near Field Communication (NFC), Long-Term Evolution (LTE), and so on. One or more such communication interface devices may be utilized via the communication port 2010 to communicate one or more other machines, either directly over a point-to-point communication path, over a wide area network (WAN) (e.g., the Internet), over a local area network (LAN), over a cellular (e.g., third generation (3G) or fourth generation (4G)) network, or over another communication means. Further, the communication port 2010 may communicate with an antenna or other link for electromagnetic signal transmission and/or reception.
In an example implementation, health data, air filtration data, and software and other modules and services may be embodied by instructions stored on the data storage devices 2004 and/or the memory devices 2006 and executed by the processor 2002. The computer system 2000 may be integrated with or otherwise form part of the system shown in
The system set forth in
While this disclosure has focused on buck converter embodiments, these methods and circuits are also applicable to boost topologies and other topologies. For instance, while synchronous buck converters have been noted, non-synchronous buck converters could also be used. The primary requirement is that the power conversion stages be able to source and sink power. Although the load has often been described as a plasma load, many other loads can also be implemented. For instance, this disclosure could be used to drive audio speakers or an electrical motor in an electric vehicle.
The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in processor-executable code encoded in a non-transitory tangible processor readable storage medium, or in a combination of the two. Referring to
This display portion 2412 generally operates to provide a user interface for a user, and in several implementations, the display is realized by a touchscreen display. In general, the nonvolatile memory 2420 is non-transitory memory that functions to store (e.g., persistently store) data and processor-executable code (including executable code that is associated with effectuating the methods described herein). In some embodiments for example, the nonvolatile memory 2420 includes bootloader code, operating system code, file system code, and non-transitory processor-executable code to facilitate the execution of a method described with reference to
In many implementations, the nonvolatile memory 2420 is realized by flash memory (e.g., NAND or ONENAND memory), but it is contemplated that other memory types may be utilized as well. Although it may be possible to execute the code from the nonvolatile memory 2420, the executable code in the nonvolatile memory is typically loaded into RAM 2424 and executed by one or more of the N processing components in the processing portion 2426.
The N processing components in connection with RAM 2424 generally operate to execute the instructions stored in nonvolatile memory 2420 to enable production of a summarized PWM output that is up or down converted from a dynamic setpoint waveform. For example, non-transitory, processor-executable code to effectuate the methods described with reference to
In addition, or in the alternative, the processing portion 2426 may be configured to effectuate one or more aspects of the methodologies described herein (e.g., the methods described with reference to
The input component 2430 operates to receive signals (e.g., the reference waveform, the dynamic setpoint waveform, or the setpoint) that are indicative of one or more aspects of the controllers 301 and 2501 or the flash power converter 400. The output component generally operates to provide one or more analog or digital signals to effectuate an operational aspect of the controllers 301 and 2501 or the flash power converter 400. For example, the output portion 2432 may provide the dynamic setpoint waveform from the setpoint generator, the reference waveform from the reference generator, or the summarized PWM output described with reference to at least
The depicted transceiver component 2428 includes M transceiver chains, which may be used for communicating with external devices via wireless or wireline networks. Each of the M transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).
Some portions are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those of ordinary skill in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is a self-consistent sequence of operations or similar processing leading to a desired result. In this context, operations or processing involves physical manipulation of physical quantities. Typically, although not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared or otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals or the like. It should be understood, however, that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, it is appreciated that throughout this specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” and “identifying” or the like refer to actions or processes of a computing device, such as one or more computers or a similar electronic computing device or devices, that manipulate or transform data represented as physical electronic or magnetic quantities within memories, registers, or other information storage devices, transmission devices, or display devices of the computing platform.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
As used herein, the recitation of “at least one of A, B and C” is intended to mean “either A, B, C or any combination of A, B and C.” The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present Application for patent is a Continuation-in Part of U.S. patent application Ser. No. 16/505,954 entitled “ADDITIVE SYNTHESIS OF INTERLEAVED SWITCH MODE POWER STAGES FOR MINIMAL DELAY IN SET POINT TRACKING” filed Jul. 9, 2019, pending, which is a Continuation of U.S. patent application Ser. No. 16/405,251 entitled “ADDITIVE SYNTHESIS OF INTERLEAVED SWITCH MODE POWER STAGES FOR MINIMAL DELAY IN SET POINT TRACKING′ filed May 7, 2019 and issued as U.S. Pat. No. 10,447,174 on Oct. 15, 2019, which claims priority to Provisional Application No. 62/767,421 entitled “ARBITRARY WAVEFORM POWER GENERATOR” filed Nov. 14, 2018, both assigned to the assignee hereof and hereby expressly incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 62767421 | Nov 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16405251 | May 2019 | US |
| Child | 16505954 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16505954 | Jul 2019 | US |
| Child | 16847457 | US |
