Address Buffer

Abstract

An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock, but receives an external address. The third input circuit receives an internal refresh address and is activated by an internal refresh address. The address buffer cooperates with a switcher which produces the internal refresh address timing clock and the external address timing clock, alternatively, by switching a basic timing clock generated by an address drive clock generator.

Description

BACKGROUND OF THE INVENTION

The present invention relates to an address buffer of a semiconductor memory circuit and, more particularly, to an address buffer used in a dynamic memory which contains therein an address counter for achieving a refresh operation with respect to the stored data in the memory.

As is well known, a dynamic memory, such as a RAM, needs a refresh operation to prevent the stored data in the memory from fading away. In a typical and conventional dynamic memory, an address for achieving the refresh is sequentially supplied, every time a refresh operation is necessary, from an external address generator located outside the memory. However, lately it has been the tendency to generate such an address inside the memory, so that it is not necessary to prepare and employ the above-mentioned external address generator. Such an internal address generator is called a refresh counter. Accordingly, the memory needs no external refresh address, but merely requires an external instruction to commence each refresh operation. Every time the refresh instruction is supplied to the memory, the internal refresh address is sequentially supplied, one by one to the word lines of the memory.

During each rest term of the refresh operation, the memory cooperates periodically with the peripheral units, such as a central processing unit (CPU). In this case, the memory is accessed not by the internal refresh address, but by an external address supplied from the peripheral unit. Therefore, the memory is accessed by the internal refresh address and the external address, selectively. Either the internal refresh address or the external address is then applied to an address decoder, by way of the address buffer. The present invention refers to the address buffer. Generally, the address buffer has two major functions. The first function is to produce both the address (A) and the inverting address (A), simultaneously, where address (A) is identical to the supplied internal refresh address or the supplied external address. The second function is to convert the level of the supplied address, such as a TTL level, into the high level address (A, A), such as the MOS level.

The currently used address buffer cannot perform a high speed operation. The reason for this will be explained in detail hereinafter. Thus, the currently used address buffer does not have a sufficient capability to cope with the very high speed data processing in, for example, a super computer system.

SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to provide an address buffer having the capability of performing a very high speed operation.

The present invention will be more apparent from the ensuing description with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a dynamic memory which contains a currently used address buffer;

FIG. 2 is a detailed circuit diagram of the address buffer (ADD BUF) and the multiplexer 8 shown in FIG. 1;

FIG. 3 is a timing diagram used for explaining the operation, especially the refresh operation, of the circuit shown in FIG. 2;

FIG. 4 is a circuit diagram of a dynamic memory which employs an address buffer and its neighboring members according to the present invention;

FIG. 5 is a detailed circuit diagram representing the address buffer (ADD BUF) shown in FIG. 4;

FIG. 6A is a timing diagram used for explaining the operation of the address buffer shown in FIG. 5, during the refresh operation mode; and

FIG. 6B is a timing diagram used for explaining the operation of the address buffer shown in FIG. 5, during the normal operation mode.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a circuit diagram of a dynamic memory which contains therein a currently used address buffer to which the present invention refers. In FIG. 1, the reference numeral 1 represents a refresh clock generator (REF CLK GEN), 2 an address drive clock generator (ADD DRV CLK GEN), 3 an internal refresh address counter (REF ADD CNT), 4 memory cell arrays, 5 a sense amplifier (S/A) including column decoders (not shown) therein, 6 row decoders (ROW DEC), 7.sub.1 through 7.sub.n address buffers (ADD BUF), and 8.sub.1 through 8.sub.n multiplexers. The multiplexers 8.sub.1 through 8.sub.n produce inputs a.sub.0 through a.sub.n, respectively, to be supplied to the address buffers 7.sub.1 through 7.sub.n. The inputs a.sub.0 through a.sub.n are specified by either the external address ADD.sub.0 through ADD.sub.n during the normal operation mode or the refresh address R.sub.0 through R.sub.n, which are the output of the internal refresh address counter 3, during the refresh operation mode.

The refresh clock generator 1 receives an external clock RFSH and then produces clocks PRF, PRF and RF. The clock RFSH is logic "L" when the refresh operation is to occur. Therefore, when the clock RFSH is logic "H", a normal operation is to occur, which is called a normal operation mode. According to the logic of the clock RFSH, the logic of the clock PRF or the clock PRF becomes "H." When the logic of the clock RFSH is "L," the clock PRF is changed to logic "H", and accordingly, the refresh address R.sub.0 through R.sub.n is selected as the inputs a.sub.0 through a.sub.n, via transistors Q.sub.32 through Q'.sub.32. However, if the clock RFSH is logic "H," the clock PRF is made logic "H," and, accordingly, the external address ADD.sub.0 through ADD.sub.n is selected as the inputs a.sub.0 through a.sub.n, via transistors Q.sub.31 through Q'.sub.31. The clock RF (also shown in FIGS. 3 and 6A) is used for activating the address drive clock generator 2. The generator 2 receives the clock RF and then produces clocks .phi..sub.0, .phi..sub.1 and AD, sequentially. The generator 2 is triggered by a trigger pulse RAS (row address strobe). The pulse RAS is generated synchronously with a machine cycle, and it is used in the normal operation mode.

In the memory cell arrays 4, the reference symbol WL denotes a word line, BL a bit line, and MC a memory cell. A memory cell MC is located at every cross point of the word lines WL and bit lines BL.

FIG. 2 is a detailed circuit diagram of the address buffer (ADD BUF) and the multiplexer 8 shown in FIG. 1. Since, in FIG. 1, the address buffers 7.sub.1 through 7.sub.n have the same construction and also the multiplexers 8.sub.1 through 8.sub.n have the same construction, only one of the address buffers 7 and only one of the multiplexers 8 are illustrated in FIG. 2. The multiplexer 8 receives, at its inputs, the external address ADD and the refresh address R, selectively, and the address buffer 7 produces the addresses A and A, according to the output of the multiplexer 8. It should be understood that the reference symbols ADD, R, a, A, A, 7 and 8 are respectively classified into each bit of address by using the suffixes 0 through n.

As previously mentioned, in the multiplexer 8, the MOS transistor Q.sub.31 is controlled at its gate by the clock PRF, so that if the external clock RFSH (FIG. 1) is changed to logic "H", the clock PRF is changed to logic "H", and, the external clock ADD becomes effective. On the other hand, the MOS transistor Q.sub.32 is controlled at its gate by the clock PRF so that if the external clock RFSH (FIG. 1) is changed to logic "L", the clock PRF is changed to logic "H", and, the refresh address R supplied from the counter 3 (FIG. 1) becomes effective. Consequently, during the normal operation mode, logical conditions stand, that is RFSH is "H" and also PRF is "H". In this case, since the MOS transistor Q.sub.31 is turned to ON, the input a for the address buffer 7 is specified by the external address ADD. However, when the refresh operation mode occurs, the logic of the external clock RFSH changes from "H" to "L", as shown in FIG. 3. FIG. 3 is a timing diagram used for explaining the operation, especially the refresh operation, of the circuit shown in FIG. 2. At this time, the output from the reference clock generator 1 (FIG. 1), that is the clock PRF, changes from logic "H" to logic "L", while the clock PRF changes from logic "L" to Logic "H". Accordingly, the MOS transistor Q.sub.32 is turned ON and the input a is specified by the refresh address R. The timing diagram of FIG. 3 is depicted by taking, as an example, a case where the refresh address Q has logic "H" and the external address ADD has logic "L".

The address buffer 7 is comprised of MOS transistors Q.sub.1 through Q.sub.15, as shown in FIG. 2. Of these transistors, the MOS transistors Q.sub.1 through Q.sub.5 comprises a flip-flop FF which functions as a main amplifier. The flip-flop FF includes nodes N.sub.1 and N.sub.2 which function as a pair of input terminals and a pair of output terminals of the flip-flop FF, alternately. The node N.sub.1 is provided with an external address input circuit IN.sub.1 which is comprised of the MOS transistors Q.sub.6 and Q.sub.8 connected in series. The node N.sub.2 is provided with a reference voltage input circuit IN.sub.2 which is comprised of the MOS transistors Q.sub.7 and Q.sub.9 connected in series. Further, the nodes N.sub.1 and N.sub.2 are provided with an output circuit OUT which is comprised of the MOS transistors Q.sub.10 through Q.sub.15. The output circuit OUT functions to pick up the amplified signal produced from the flip-flop (main amplifier) FF and produces the addresses A and A.

The address buffer 7 is started by the application of the clock .phi..sub.0. That is, when the clock .phi..sub.0 starts rising, as shown by a curve .phi..sub.0 in FIG. 3, the MOS transistors Q.sub.6 and Q.sub.8 are turned ON. In this case, the MOS transistor Q.sub.9 is always maintained in a conductive state due to the presence of the reference voltage REF, at its gate. Accordingly, the level at the node N.sub.2 is set to a certain level which is determined by the ratio of the mutual conductances g.sub.m between the transistors Q.sub.2 (depletion MOS transistor), Q.sub.7 and Q.sub.9. Generally, the value of the mutual conductance g.sub.m is determined by various factors, such as the size of the MOS transistor and voltage level applied to the gate.

On the other hand, the MOS transistor Q.sub.8, with the input a applied to its gate, is turned ON or OFF in accordance with logic "H" or "L" of the input a. When the input a is logic "H", the transistor Q.sub.8 is turned ON, and, accordingly, a current flows through the MOS transistors Q.sub.1 (depletion MOS transistor), Q.sub.6 and Q.sub.8. At this time, the voltage level at the node N.sub.1 is determined by the ratio of the mutual conductances g.sub.m defined by the respective transistors Q.sub.1, Q.sub.6 and Q.sub.8. In this case, the value of g.sub.m defined by the transistor Q.sub.8 is designed in advance to be larger than the value of g.sub.m defined by the aforementioned transistor Q.sub.9 receiving the reference voltage REF. As a result, the relationship V.sub.N1 <V.sub.N2 is obtained, where the symbols V.sub.N1 and V.sub.N2 denote the voltage levels developed at the nodes N.sub.1 and N.sub.2, respectively. However, if the input a is changed to logic "L", the relationship V.sub.N1 >V.sub.N2 is obtained, where the voltage V.sub.N1 is almost the same as the voltage level V.sub.CC (FIGS. 2 and 3). Thus, either the relationship V.sub.N1 <V.sub.N2 or the relationship V.sub.N1 >V.sub.N2 is created in accordance with the logic "H" or "L", respectively, of the input a. Generally, the difference between the voltages V.sub.N1 and V.sub.N2 is very small, and, therefore, the above recited two relationships are not remarkably distinguished from each other. In order to achieve a remarkably distinguished voltages between these two relationships, the voltage levels V.sub.N1 and V.sub.N2 are amplified by the aforementioned flip-flop (main amplifier) FF. The flip-flop FF is energized by the clock .phi..sub.1 to be applied to the gate of the transistor Q.sub.5. The clock .phi..sub.1 follows after the clock .phi..sub.0, as shown in FIGS. 6A and 6B, but not shown in FIG. 3. When the transistor Q.sub.5 is turned ON by the clock .phi..sub.1, the voltage level at node N.sub.3 is changed to a ground level V.sub.SS (FIGS. 2 and 3), wherein node N.sub.3 is common to each source of the transistors Q.sub.3 and Q.sub.4. Thus the flip-flop FF is energized, and if the relationship V.sub.N1 <V.sub.N2 stands (a="H"), the transistor Q.sub.3 is turned ON and at the same time the transistor Q.sub.4 is turned OFF, the voltage V.sub.N1 is thus reduced to the voltage level V.sub.SS. At the same time, the voltage V.sub.N2 is increased to the voltage level V.sub.CC. This means that the flip-flop FF has functioned as a voltage amplifier. However, if the relationship V.sub.N1 >V.sub.N2 stands (a="L"), the transistor Q.sub.3 is turned OFF and, at the same time the transistor Q.sub.4 is turned ON. The voltage V.sub.N1 is raised to the voltage level V.sub.CC and, at the same time, the voltage V.sub.N2 is decreased to the voltage level V.sub.SS.

During the term preceding the application of the clock .phi..sub.0, a certain state is provided in which the voltage levels at both the nodes N.sub.6 and N.sub.7 (corresponding to the drains of the transistors Q.sub.10 and Q.sub.11, respectively) are precharged to a level of (V.sub.CC -V.sub.th). In this state, the voltage V.sub.CC is directly applied to the nodes N.sub.1 and N.sub.2. Therefore, the transistors Q.sub.10 and Q.sub.11 are conductive, so that the nodes N.sub.6 and N.sub.7 are charged up with certain reduction of the voltage (threshold voltage V.sub.th of each of the transistors Q.sub.10 and Q.sub.11). However, when the above-mentioned state is changed to the next state, in which the clock .phi..sub.1 is activated, since the flip-flop FF is energized, either one of the transistors Q.sub.10 and Q.sub.11 is turned OFF in accordance with the logic of the input a. For example, if the logic of the input a is "L", the transistor Q.sub.10 is turned OFF and, at the same time, the transistor Q.sub.11 is turned ON, because, in this state, the voltage levels at the nodes N.sub.1 and N.sub.2 are set to be V.sub.N1, equal to V.sub.CC, and V.sub.N2 nearly equal to V.sub.SS, respectively; that is, V.sub.N1 =V.sub.CC and V.sub.N2 .perspectiveto.V.sub.SS. Then, the electric charges stored at the node N.sub.7 are absorbed toward the node N.sub.2 having the level V.sub.SS, via the conductive transistor Q.sub.11. In this state, since the transistor Q.sub.10 is nonconductive, the electric charges stored at the node N.sub.6 remain as they are. Due to the presence of the electric charges at the node N.sub.6, the MOS transistor Q.sub.12 is made fully conductive when the clock AD, having the level of V.sub.CC, is generated, because the bootstrap effect is effected to the transistor Q.sub.12 by the above-mentioned electric charges. Then the address A, having logic "H," is produced. The waveform of the clock AD is not shown in FIG. 3, but is shown in FIGS. 6A and 6B. In this state, since the transistor Q.sub.15 is turned ON, while the transistors Q.sub.13 and Q.sub.14 are turned OFF, the address A is changed to logic "L" being equal to the level of V.sub.SS. The above-mentioned operation is performed under the condition where the input a has logic "L". Thereby, the address A becomes logic "L", identical to the logic of the input a, while the inverting address A becomes logic "H".

If the operation of the circuit shown in FIG. 2 is achieved under the condition where the input a has logic "H", the voltage level V.sub.N1 is almost the same as the level of V.sub.SS and V.sub.N2 is the same as the level V.sub.CC. Therefore, the transistor Q.sub.10 is turned ON, but the transistor Q.sub.11 is turned OFF. Under such conditions, when the clock AD is generated, the transistors Q.sub.13 and Q.sub.14 are turned ON, while the transistors Q.sub.12 and Q.sub.15 are turned OFF. As a result, both the address A having logic "H" and the inverted address A having logic "L" are produced simultaneously.

During the refresh operation mode, the following operations are executed sequentially in the memory until the production of both the addresses A and A are completed: (1) changing of the external clock RFSH.fwdarw.(2) generating the clocks PRF and PRF from the refresh clock generator 1.fwdarw.(3) exchanging the external address ADD with the refresh address R under control of the clocks PRF and PRF.fwdarw.(4) generating the clock RF.fwdarw.(5) generating the clock .phi..sub.0 from the address drive clock generator 2.fwdarw. . . . and so on. In executing the above-mentioned operations, certain defects arise in that it takes a relatively long time from when the above operation (2) is executed to the time when the above operation (5) is executed. In other words, the generation of the clock .phi..sub.0 should not be started until the logic level of the input a from the multiplexer 8 is fully saturated to a predetermined level (refer to a time t.sub.0 in FIG. 3). Thus, a waiting time should be created in the address buffer 7. With reference to FIG. 3, the waiting time is indicated by the reference symbol t.sub.w. This is the reason why the address buffer 7 of FIG. 2 cannot operate with a high speed. To be more specific, the above-mentioned defect is derived from the existence of both the multiplexer 8 and the input circuit IN, shown in FIG. 2, which will be clarified hereinafter.

The present invention intends to improve the operating speed of the memory, specifically to shorten the length of the above-mentioned waiting time t.sub.w.

FIG. 4 illustrates a circuit diagram of a dynamic memory which employs therein an address buffer and its neighboring members according to the present invention. In FIG. 4, members which are identical to those of FIG. 1 are represented by the same reference numerals and symbols. Therefore, members 10 and 17.sub.1 through 17.sub.n are newly employed in the memory of FIG. 4. However, members corresponding to the address buffer (ADD BUF) 17.sub.1 through 17.sub.n are shown in FIG. 1 as the address buffer 7.sub.1 through 7.sub.n. The member 10 is called a switcher. During the normal operation mode, the switcher 10 switches the clock .phi..sub.0 produced from the address drive generator 2 to a first signal path for transferring a clock .phi..sub.ON ; alternately, the switcher 10 switches the clock .phi..sub.0 to a second path for transferring a clock .phi..sub.OR. In this case, during the normal operation mode, the refresh clock generator 1 produces the clock PRF having logic "H", and, accordingly, the logic at node N.sub.21 is changed to " H", via a MOS transistor Q.sub.41, with a voltage level equal to (V.sub.CC -V.sub.th). The symbol V.sub.th is a threshold voltage of the transistor Q.sub.41. Then, the clock .phi..sub.0 is transferred, as the clock .phi..sub.ON, from the address drive clock generator 2 to the inputs of the address buffers 17.sub.1 through 17.sub.n via a MOS transistor Q.sub.42. In this case, it is preferable to maintain the voltage level of the clock .phi..sub.ON equal to or higher than that of the source clock .phi..sub.0, to strongly drive the address buffers 17.sub.1 through 17.sub.n. In order to accomplish this, the MOS transistor Q.sub.41 is employed. Theoretically, in the switcher 10, the clock .phi..sub.0 can be switched to the clock .phi..sub.ON or .phi..sub.OR by using the gate transistors Q.sub.42 and Q.sub.44 controlled directly by the clocks PRF and PRF, where the voltage levels of the clocks .phi..sub.ON and .phi..sub.OR are lower than that of the clock .phi..sub.0. However, if the combination of the transistors Q.sub.41 and Q.sub.42 and also the combination of the transistors Q.sub.43 and Q.sub.44 is introduced into the switcher 10, the bootstrap effect is created in each of these combinations. In this case, the voltage levels at the nodes N.sub.21 and N.sub.22 are maintained at a level higher than the level V.sub.CC.

During the refresh operation mode, the refresh clock generator 1 produces the clock PRF having logic "H", and, accordingly, the MOS transistor Q.sub.44 is turned ON, so that the clock .phi..sub.0 is transferred, as the clock .phi..sub.OR to the inputs of the address buffers 17.sub.1 through 17.sub.n. Thus, the clock .phi..sub.OR and the above-mentioned clock .phi..sub.ON are supplied alternatively from the switcher 10. In accordance with the clock .phi..sub.ON or .phi..sub.OR, the external address ADD.sub.0 through ADD.sub.n, the refresh address R.sub.0 through R.sub.n or the inverting address R.sub.0 through R.sub.n are selectively applied to the address buffers 17.sub.1 through 17.sub.n.

FIG. 5 is a detailed circuit diagram of the address buffer (ADD BUF) shown in FIG. 4. This circuit diagram corresponds to that of FIG. 2. Accordingly, members which are identical to those of FIG. 2 are represented by the same reference numerals and symbols. Since, in FIG. 4, the address buffers 17.sub.1 through 17.sub.n have the same construction as each other, only one of them is illustrated, as indicated by the reference numeral 17. In FIG. 5, as compared with the cirucit diagram of FIG. 2, the external address input circuit (first input circuit) IN.sub.1 and also the reference voltage input circuit (second input circuit) IN.sub.2 are still useful in the address buffer 17. However, the following three points should be noticed. First, the multiplexer 8, which is employed in the address buffer of FIG. 2, is not used therein and no such multiplexer is shown in FIG. 5. The reason for this is that, due to the presence of the multiplexer 8, the voltage level of the input a (FIG. 2) rises very slowly to its saturation level within the aforementioned waiting time t.sub.w (FIG. 3). This is because the mutual conductances g.sub.m of the MOS transistors Q.sub.31 and Q.sub.32 comprising the multiplexer 8 prevent the input a level from rising quickly. Second, the input circuits IN.sub.1 and IN.sub.2 of FIG. 5 do not directly receive the clock .phi..sub.0, as in FIG. 2, but receive the clock .phi..sub.ON via the switcher 10 (FIG. 4). Third, a third input circuit IN.sub.3 and a fourth input circuit IN.sub.4 are newly employed. The third input circuit IN.sub.3 is connected, as a whole, in parallel with the first input circuit IN.sub.1. In addition, the circuit IN.sub.3 receives the clock .phi..sub.OR and the refresh address R. The fourth input circuit IN.sub.4 is connected, as a whole, in parallel with the second input circuit IN.sub.2. In addition, the circuit IN.sub.4 receives the clock .phi..sub.OR and the inverted refresh address R. In this case, the first and second input circuits IN.sub.1 and IN.sub.2 are activated by the application of the clock .phi..sub.ON, while the third and fourth input circuits IN.sub.3 and IN.sub.4 are activated by the application of the clock .phi..sub.OR. That is, the MOS transistors Q.sub.6 and Q.sub.7 of the input circuits IN.sub.1 and IN.sub.2 are turned ON by the clock .phi..sub.ON during the normal operation mode. The third input circuit IN.sub.3 is comprised of MOS transistors Q.sub.45 and Q.sub.47 connected in series, and MOS transistor Q.sub.45 is turned ON by the clock .phi..sub.OR only during the refresh operation mode. Similarly, the fourth input circuit IN.sub.4 is comprised of MOS transistors Q.sub.46 and Q.sub.48 connected in series, and MOS transistor Q.sub.46 is turned ON by the clock .phi..sub.OR only during the refresh operation mode.

FIG. 6A is a timing diagram used for explaining the operation of the address buffer shown in FIG. 5, during the refresh operation mode. FIG. 6B is a timing diagram used for explaining the operation of the address buffer shown in FIG. 5, during the normal operation mode. In FIG. 6A, during the refresh operation mode, first the logic of the clock RFSH is changed from "H" to "L" and then the logic of the clock PRF is changed from "L" to "H"; at the same time, the logic of the clock PRF is changed from "H" to "L" (these clocks PRF and PRF are produced from the refresh clock generator 1). These operations are identical to those represented in FIG. 3. However, in FIG. 6A, the clock .phi..sub.0 and, accordingly, the clock .phi..sub.OR can be generated soon after the logic changes of the clocks PRF and PRF. In other words, it is not necessary to wait until the time the voltage level of the slow rising input a reaches its saturation level to generate the clock .phi..sub.0, as occurs in FIG. 3. As a result, the waiting time t.sub.w of FIG. 3 is considerably shortened to a waiting time t.sub.w ' as shown in FIG. 6A, and a high speed operation of the address buffer can be expected. The reason why the input a can be removed from the address buffer 17 is that no member similar to the multiplexer 8 of FIG. 2 is used. Instead of multiplexer 8, the third and fourth input circuits IN.sub.3 and IN.sub.4 are employed in FIG. 5. Thus, the dynamic memory based on the present invention can operate with a high operating speed as compared to that of FIG. 1.

In FIG. 6A, the characteristic curves N.sub.21, N.sub.22, PRF, PRF, RF and RFSH indicate the respective levels appearing in FIG. 4, but not in FIG. 5. Regarding characteristic curves .phi..sub.0, RF, PRF, and PRF, since the clock .phi..sub.0 is produced with a certain time delay after the generation of the clock RF, the clocks RF, PRF, and PRF may be activated approximately at the same time. Regarding characteristic curve N.sub.22, the voltage level at the node N.sub.22 can be increased over the level V.sub.CC due to the previously mentioned bootstrap effect.

In FIG. 6B, during the normal operation mode, the logic of the clock .phi..sub.ON is changed to "L" and, accordingly, the first and second input circuits are left in an idle state. Thus, a current flows through the third input circuit IN.sub.3 or the second input circuit IN.sub.2 (also the fourth input circuit IN.sub.4). Since the transistor Q.sub.9 is always made conductive by the reference voltage REF, the above-mentioned current can flow through the circuit IN.sub.2 and also circuit IN.sub.4. Consequently, it should be noticed that the fourth input circuit IN.sub.4 can be theoretically be omitted from the address buffer 17. However, it is actually preferable to employ not only the third input circuit IN.sub.3, but also the fourth input circuit IN.sub.4. This is because it is preferable to mount the same load (IN.sub.3, IN.sub.4) seen from each of the nodes N.sub.1 and N.sub.2 in view of circuit balance.

Returning again to FIGS. 5 and 6A, the flip-flop FF is liable to be latched in either one of the two states, according to the logic of the refresh addresses R and R. For example, when the address R is set to logic "H" and, accordingly, the address R is "L", the following relationship stands between the voltage levels V.sub.N1 at the node N.sub.1 and V.sub.N2 at the node N.sub.2, that is V.sub.N1 <V.sub.N2. Accordingly, the clock .phi..sub.1 is applied from the clock generator 2 to the transistor Q.sub.5 at its gate and the flip-flop FF is activated so as to make the transistors Q.sub.3 and Q.sub.4 ON and OFF, respectively. Then, the voltage level V.sub.N1 is changed to the level V.sub.SS, while the voltage level V.sub.N2 is changed to the level V.sub.CC. As a result, the output circuit OUT produces both the address A of logic "H" and the address A of logic L, simultaneously, accessing the memory arrays 4 (FIG. 4).

In FIG. 6B, during the normal operation mode, the clocks PRF of logic "H" and PRF of logic "L" are produced from the clock generator 1 (FIG. 4), and, thereby, the clocks .phi..sub.ON of logic "H" and .phi..sub.OR of logic "L" are generated in the switcher 10 (FIG. 4). Thus, only the first and the second input circuits IN.sub.1 and IN.sub.2 are activated.

As explained in detail, almost no time for switching the external address ADD to the refresh address R and vice versa is required, and, accordingly, a considerably high speed operating address buffer can be realized.

Claims

1. An address buffer, for a dynamic memory, having a normal operation mode and a refresh operation mode, the dynamic memory including an address drive clock generator, operatively connected to receive an external address or internal refresh address, for generating a timing clock signal, and a refresh clock generator, operatively connected to the address drive clock generator, for generating an external address timing clock or an internal refresh address timing clock, comprising:

a flip-flop, having a first input/output terminal operatively connected to receive the external address or the internal refresh address and a second input/output terminal operatively connected to receive a reference voltage, said flip-flop latched in either one of two states in dependence upon the external address or the internal refresh address supplied alternately;

an output circuit, operatively connected to said flip-flop, providing an output address and an inverted output address;

a first circuit, operatively connected to said first input/output terminal of said flip-flop and operatively connected to receive the external address and the external address timing clock, for receiving the external address upon receipt of the external address timing clock;

a switcher, operatively connected to the refresh drive clock generator and the address drive clock generator, for receiving the external address timing clock and the internal refresh timing clock and operatively connected to said first input circuit, for transferring to said first input circuit the external address timing clock during the normal operation mode and the internal refresh address timing clock during the refresh operation mode by switching said timing clock signal of the address drive clock generator;

a second input circuit, operatively connected to said second input/output terminal of said flip-flop, for receiving the reference voltage upon receipt of the external address timing clock; and

a third input circuit, operatively connected to receive the internal refresh address clock and the internal refresh address and operatively connected in parallel to said first input circuit, for receiving the internal refresh address upon receipt of the internal refresh address timing clock.

2. An address buffer as set forth in claim 1, further comprising a fourth input circuit, operatively connected in parallel to said second input circuit and operatively connected to receive the internal refresh address timing clock and the internal refresh address, for inverting the internal refresh address upon receipt of the internal refresh address timing clock.

3. An address buffer as set forth in claim 1 or 2, wherein said switcher comprises:

a first gate transistor, operatively connected to the refresh clock generator and operatively connected to receive the external address timing clock, for transferring the external address timing clock; and

a second gate transistor, operatively connected to said refresh clock generator and operatively connected to receive the internal refresh address timing clock, for transferring the internal refresh address timing clock, alternately with that of the external address timing clock of said first transistor.

4. An address buffer as set forth in claim 3, wherein said first gate transistor and said second gate transistor are operatively connected to said third transistor and said fourth transistor, respectively, the combination of said first and third transistors and the combination of said second and fourth transistors creating a bootstrap effect.

5. An address buffer as set forth in claim 1, wherein:

said first input circuit is operatively connected to said flip-flop and operatively connected to receive the external address timing clock and the external address and comprises a first transistor and a second transistor operatively connected in series with said first transistor, said first and second transistors each having a gate operatively connected to receive the external address timing clock and the external address, respectively;

said second input circuit is operatively connected to receive the reference voltage and the external address timing clock and comprises a third transistor and a fourth transistor, operatively connected in series with said third transistor, each having a gate for receiving the external address timing clock and the reference voltage, respectively; and

said third input circuit is operatively connected between said first input circuit and said flip-flop and operatively connected to receive the internal refresh address timing clock and the internal refresh address, and comprises a fifth transistor having a gate for receiving the internal refresh address timing clock and a sixth transistor operatively connected in series with said fifth transistor, having a gate for receiving the internal refresh address.

6. An address buffer as set forth in claim 2, wherein said fourth input circuit is operatively connected between said second input circuit and said flip-flop and comprises a first transistor having a gate and a second transistor having a gate and operatively connected in series with said first transistor, said first and second transistors operatively connected to receive at said gates the internal refresh address timing clock and said inverted internal refresh address, respectively.

7. A dynamic memory comprising:

an address drive clock generator, operatively connected to receive an external address or internal refresh address, for generating a timing clock signal;

a refresh clock generator, operatively connected to said address drive clock generator, for receiving said timing clock signal for generating an external address timing clock or an internal refresh address timing clock;

an address buffer, operatively connected to said address drive clock generator and said refresh clock generator, and operatively connected to receive a reference voltage, said address buffer having a normal operation mode and a refresh operation mode and comprising:

a flip-flop, having a first input/output terminal operatively connected to receive said external address or said internal refresh address and a second input/output terminal, operatively connected to receive the reference voltage, said flip-flop latched in either one of two states in dependence upon the external address or the internal refresh address supplied alternately from said address drive clock generator;

an output circuit, operatively connected to said flip-flop and operatively connected to receive the external address or the internal address, for providing an output address and an inverted output address;

a first input circuit, operatively connected to said first input/output terminal of said flip-flop and said refresh clock generator, and operatively connected to receive the external address upon receipt of said external address timing clock;

a second input circuit, operatively connected to said second input/output terminal of said flip-flop and said refresh clock generator, for receiving the reference voltage upon receipt of said external address timing clock; and

a third input circuit, operatively connected to said refresh clock generator and in parallel to said first input circuit, and operatively connected to receive said internal refresh address, for receiving said internal refresh address upon receipt of said internal refresh address timing clock;

a switcher, operatively connected to said refresh clock generator, said address drive clock generator, and said flip-flop, for receiving said external address timing clock and said internal refresh address timing clock, and for transferring to said first input circuit said external address timing clock during said normal operation mode and said internal refresh address timing clock during said refresh operation mode by switching said timing clock signal supplied by said address drive clock generator.