Claims
- 1. An address generating circuit comprising:
- a latch means (101) for temporarily latching a base address value of a base pointer (Bp);
- a first arithmetic circuit means (102, 103) for receiving an output from said latch means as a first value and receiving an address distance value (d) as a second value and for performing one of addition and subtraction operations between said first value and said second value to output a first address composed of a first set of most significant bits and a first set of least significant bits;
- a data hold means (106; 111) for holding loop width information of a memory bank, said loop width information including a second set of most significant bits;
- a second arithmetic circuit means (104; 404), coupled to said first arithmetic circuit means (102; 103) and said data hold means (106; 111), to receive said first set of most significant bits of said first address and said second set of most significant bits of said loop width information and for performing one of addition and subtraction operations therebetween to output partial address information;
- a selection signal producing means (107, 108) responsive to said first set of most significant bits of said first address, for producing a selection signal that assumes a first level when said first address is within said memory bank and a second level when said first address is outside of said memory bank;
- a selecting means (109), coupled to said first arithmetic circuit means (102; 103) and said second arithmetic circuit means (104; 404), to receive said first set of most significant bits of said first address and said partial address information for outputting said first set of most significant bits of said first address when said selection signal assumes said first level and said partial address information when said selection signal assumes said second level; and
- an output means (110), coupled to said first arithmetic circuit means (102; 103) and said selecting means (109), for outputting a second address that has a third set of most significant bits composed of one of said first set of most significant bits of said first address and said partial address information that is outputted by said selecting means (109) and a second set of least significant bits composed of said first set of least significant bits of said first address.
- 2. The address generating circuit according to claim 1, and further comprising an inverter means (112), receiving a given data (.+-.) and being coupled to said second arithmetic circuit means to output an inverted data thereto, said second arithmetic circuit means outputting said partial address information in dependence on said inverted data.
- 3. An address generating circuit comprising:
- a first latch means (101) for temporarily latching a base address value of a base pointer (Bp);
- a first arithmetic circuit means (102) for receiving an output from said first latch means (101) as a first value and a given address distance value (d) as a second value and for performing one of addition and subtraction operations between said first value and said second value to output a first address composed of a first set of most significant bits and a first set of least significant bits;
- a first data hold means (106) for holding a set of loop width data each corresponding to any of a plurality of numbered memory banks and for outputting a specified one of said loop width data that is specified by a given first memory bank number, said specified one of said loop width data including a second set of most significant bits;
- a second arithmetic circuit means (104), coupled to said first arithmetic circuit means (102) and said first data hold means (106), to receive said first set of most significant bits of said first address and said second set of most significant bits of said specified one of said loop width data and for performing one of addition and subtraction operations therebetween to output partial address information;
- a second data hold means (107), coupled to said first arithmetic circuit means (102), to receive said first set of most significant bits of said first address for outputting a second memory bank number to which a memory address indicated by said first address belongs;
- a coincidence detecting means (108) for receiving said first memory bank number and said second memory bank number to output a selection signal that assumes a first level when said first memory bank number is equal to said second memory bank number and a second level when said first memory bank number is unequal to said second memory bank number;
- a selecting means (109), coupled to said first arithmetic circuit means (102) and said second arithmetic circuit means (104), to receive said first set of most significant bits of said first address and said partial address information for outputting said first set of most significant bits of said first address when said selection signal assumes said first level and said partial address information when said selection signal assumes said second level; and
- a second latch means (110), coupled to said first arithmetic circuit means (102) and said selecting means (109), for outputting a second address that has a third set of most significant bits composed of one of said first set of most significant bits of said first address and said partial address information that is outputted by said selecting means (109) and a second set of least significant bits composed of said first set of least significant bits of said first address.
- 4. The address generating circuit according to claim 3, and further comprising an inverter means (112), receiving a given data (.+-.) and being coupled to said second arithmetic circuit means to output an inverted data thereto, said second arithmetic circuit means outputting said partial address information in dependence on said inverted data.
- 5. An address generating circuit comprising:
- a first latch means (101) for temporarily latching a base address value of a base pointer (Bp);
- an adder (102) for receiving an output from said first latch means (101) and a given address distance value (d) and performing an addition operation therebetween to output a first address composed of a first set of most significant bits and a first set of least significant bits;
- a first data hold means (111) for holding an output of a constant data representing a loop width of an arbitrary one of a plurality of numbered memory banks, said constant data including a second set of most significant bits;
- a subtracter means (404), coupled to said adder means (102) and said first data hold means (111), for receiving said first set of most significant bits of said first address and said second set of most significant bits of said constant data and performing a subtraction operation therebetween to output partial address information;
- a second data hold means (107), coupled to said adder means (102), for receiving said first set of most significant bits of said first address to output a first memory bank number to which a memory address indicated by said first address belongs;
- a coincidence detecting means (108) for receiving said first memory bank number and a given second memory bank number to output a selection signal that assumes a first level when said first memory bank number is equal to said second memory bank number and a second level when said first memory bank number is unequal to said second memory bank number;
- a selecting means (109), coupled to said adder means (102) and said subtracter means (404), for receiving said first set of most significant bits of said first address and said partial address information to output said first set of most significant bits of said first address when said selection signal assumes said first level and said partial address information when said selection signal assumes said second level; and
- a second latch means (110), coupled to said adder means (102) and said selecting means (109), for outputting a second address that has a third set of most significant bits composed of one of said first set of most significant bits of said first address and said partial address information that is outputted by said selecting means (109) and a second set of least significant bits composed of said first set of least significant bits of said first address.
- 6. An address generating circuit for a memory consisting of a plurality of numbered memory banks each accessible in a looping manner, said address generating circuit generating a target address data representing a target address in said memory in response to a combination of a first given data (d) representative of a relative distance of said target address to a varying base address in said memory, a second given data (.+-.) representative of an algebraic sense of said relative distance and a given first bank number data representative of a first bank number identifying an associated one of said plurality of memory banks with said base address, said address generating circuit comprising:
- means for receiving a base pointer (Bp) indicating said base address;
- a first latch means (101) for latching a current value of said base pointer (Bp) to thereby output a first address data composed of a first area data consisting of a plurality of first most significant bits cooperatively identifying, as a first relevant area, an arbitrary one of a plurality of equi-width memory areas in said memory and a first intra-area data consisting of a plurality of first least significant bits cooperatively defining said base address in said first relevant area, said plurality of first most significant bits and said plurality of first least significant bits cooperating with each other to constitute a predetermined bit width;
- a first arithmetic circuit means (102, 103), coupled to said first latch means, for determining a first algebraic addition between said first address data and said first given data (d) in dependence on said second given data (.+-.) to thereby output a second address data composed of a second area data including a plurality of second most significant bits cooperatively identifying, as a second relevant area, a related one of said plurality of memory areas to a resultant address from said first algebraic addition and a second intra-area data consisting of a plurality of second least significant bits cooperatively defining said resultant address in said second relevant area;
- a first data hold means (106) for holding a plurality of loop width data each including a plurality of stored most significant bits cooperatively representing a predetermined loop width of a corresponding one of said plurality of memory banks;
- said first data hold means (106) responding to said first bank number data to output from among said plurality of loop width data a corresponding loop width data to one of said plurality of memory banks identified by said first bank number;
- an inverter means (112) for inverting said second given data (.+-.) to output an inverted data;
- a second arithmetic circuit means (104, 105), coupled to said inverter means, for determining a second algebraic addition between said second area data and said corresponding loop width data in dependence on said inverted data to thereby output a third area data including a plurality of third most significant bits cooperatively identifying among said plurality of memory areas a respective area with a result of said second algebraic addition;
- a second data hold means (107) for holding a plurality of second bank number data each identifying an associated one of said plurality of memory banks with an arbitrary one of said plurality of memory areas;
- said second data hold means (107) responding to said plurality of second most significant bits to output from among said plurality of second bank number data a second bank number data representative of a second bank number identifying an associated one of said plurality of memory banks with said second relevant area;
- a coincidence detecting means (108), coupled to said first data hold means and said second data hold means, for detecting a coincidence between said first bank number represented by first bank number data and said second bank number represented by said representative second bank number data;
- said coincidence detecting means (108) outputting a coincidence signal when detecting said coincidence and a non-coincidence signal when not detecting said coincidence;
- a selecting means (109), coupled to said coincidence detecting means, for selecting said plurality of second most significant bits in response to said coincidence signal or said plurality of third most significant bits in response to said non-coincidence signal to output as a fourth area data; and
- a second latch means (110), coupled to said selecting means, for latching said fourth area data and said second intra-area data to thereby output as said target address data a third address data composed of said fourth area data and said second intra-area data, said third address data having said predetermined bit width.
Priority Claims (1)
Number |
Date |
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Kind |
2-417198 |
Dec 1990 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 07/812,706, filed Dec. 23, 1991 now abandoned.
US Referenced Citations (7)
Continuations (1)
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Number |
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812706 |
Dec 1991 |
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