Claims
- 1. A reconfigurable logic system, comprising
a reconfigurable functional unit adapted to implement a number of functions; and an address-generating memory unit operably connected to the reconfigurable functional unit, the address-generating memory unit including a memory and at least one address generator adapted to construct an address for the memory.
- 2. The reconfigurable logic system of claim 1 wherein the address generator is able to construct a sequence of addresses for the memory.
- 3. The method of claim 2 wherein the address generator includes an incrementor.
- 4. The reconfigurable logic system of claim 3 wherein the incrementor comprises an increment register and an adder.
- 5. The reconfigurable logic system of claim 1 wherein the address generator includes configuration bits to control the configuration of the address generating unit.
- 6. The reconfigurable logic of claim 1 wherein the address generator includes a mask value to produce a masked address value.
- 7. The reconfigurable logic system of claim 1 wherein the addresses provided by the address generator can include an incremented value.
- 8. The reconfigurable logic system of claim 1 wherein the address generator such that the address provided by the address generator can be fed back the address value.
- 9. The reconfigurable logic system of claim 1 wherein the address is provided by the address generator can be a cycling address sequence.
- 10. The reconfigurable logic system of claim 1 wherein the address is provided by the address generator includes a base register value.
- 11. The reconfigurable logic system of claim 1 wherein the address generator includes a multiplexer to select multiple different generated addresses.
- 12. A reconfigurable logic system, comprising
a reconfigurable functional unit adapted to implement a number of functions and an address-generating memory unit operably connected to the reconfigurable functional unit, the address-generating memory unit including a memory and at least one address generator adapted to construct an address for the memory, the address generator able to construct a sequence of addresses for the memory using an incrementor.
- 13. The reconfigurable logic system of claim 12 wherein the incrementor includes an adder.
- 14. The reconfigurable logic system of claim 13 wherein the incrementor includes a register to store an increment value.
- 15. The reconfigurable logic system of claim 12 wherein the address generator includes a masking portion.
- 16. The reconfigurable logic system of claim 12 wherein the address generator can provide a cycling sequence of addresses.
- 17. The reconfigurable logic system of claim 12 wherein the address generator includes a multiplexer to aid in selecting the address output.
- 18. The reconfigurable logic system of claim 12 wherein the address generator has different modes.
- 19. The reconfigurable logic system of claim 12 wherein the address generator has bits that allow the selection of different types of address output.
DESCRIPTION OF THE RELATED ART
[0001] This application is a Continuation-in-Part of Application Ser. No. 09/343,477 filed Jun. 30, 1999, which is incorporated herein by reference.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09343477 |
Jun 1999 |
US |
Child |
09967855 |
Sep 2001 |
US |