Claims
- 1. A circuit for checking to see if a memory address made up of a group of M high order digits plus a group of K low order digits can fall within a range of contiguous memory addresses comprising:
- first means for receiving the low order K-digits of an address at one end of said range of contiguous addresses,
- second means for receiving c-digits that indicate the number of addresses in said range of contiguous addresses,
- first logic means responsive both to the K-g high order digits of said K low order digits received in said first means where g is a number of digits less than K digits and equal to or greater than c digits and to the correspondingly ordered K-g high order digits of said lower order digits in the memory address being checked to test for the existence of conditions of the K-g digits which would indicate the memory address can fall within said range and in response to the test provide a first set of signals indicative of the results of the test,
- second logic means responsive both to said low-order g digits of said K low order digits received in said first means, and to the correspondingly ordered g low order digits of the memory address being checked and also responsive to said c digits received by said second means for testing the occurrence of a particular one of a plurality of further conditions of the g digits which would indicate that the memory address can fall within the range and provide a second set of signals indicative to the results of the testing, and
- third logic means responsive to the first and second set of signals from said first and second logic means respectively to determine concurrence of one of the plurality of further conditions with one of the first mentioned conditions and thereby indicate whether said memory address does fall in said range.
- 2. The apparatus of claim 1 in which said first means specifies the address at the low end of the range of contiguous addresses.
- 3. The apparatus of claim 2 in which said memory address is
- ODR=ODR.sub.1 . . . , ODR.sub.(M+K)
- said end of the range of contiguous addresses is:
- ICR=ICR.sub.1 . . . , ICR.sub.(M+K)
- said first, second and third logic means together solve the expression
- [E.sub.M+1 +G.sub.M+2 + . . . +G.sub.M+K-g +B].multidot.[E.sub.M+1 +L.sub.M+2 ].multidot. . . . .multidot.[E.sub.M+K-g-1) +L.sub.(M+K-g) ].multidot.[E.sub.M+K-g +A]
- where
- G.sub.i =[ODR.sub.i >ICR.sub.i ]=ODR.sub.i .multidot.ICR.sub.i
- L.sub.i =[ODR.sub.i <ICR.sub.i ]=ODR.sub.i .multidot.ICR.sub.i
- E.sub.i =[ODR.sub.i =ICR.sub.i ]=ODR.sub.i .multidot.ICR.sub.1 +ODR.sub.i .multidot.ICR.sub.i ##EQU7##
- 4. The apparatus of claim 1 wherein,
- a first of said first mentioned conditions of said K-g digits is that each of said K-g digits received in said first means is equal to "1" when each of said K-g digits in the memory address is equal to "0",
- a second of said first mentioned conditions of said K-g digits is that one digit i of the K-g digits of the memory address equals "1" while the corresponding digit i in the K-g digits received in said first means equals "0" while each higher order digit of said K-g digits in said memory address is equal to its corresponding digit of the K-g digits received in said first means and all lower order digits in said K-g digits of the memory address equal "0" and lower order of said K-g digits received in said first means equals "1",
- a third of said first mentioned conditions of the K-g digits is that each of the digits in the memory address is equal to the corresponding digit in the K-g digits received by said first means,
- a first of the further conditions equals [(ODR.sub.(M+K-g+1)-(M+K)) minus (ICR.sub.(M+K-g+1)-(M+K) plus RANGE SIZE)<-2.sup.g ]
- a second of the further conditions equals [(ICR.sub.(M+K-g+1)-(M+K)).ltoreq.(ODR.sub.(M+K-g+1)-(M+K))<(ICR.sub.(M+K-g+1)-(M+K) plus RANGE SIZE)]
- said first set of signals are X, Y and Z where X.multidot.Y=the OR of the first and second of the first mentioned conditions and Z.multidot.Y=n the third of the first mentioned conditions
- where said third logic means performs the logical function X.multidot.Y.multidot.A+B.multidot.Y.multidot.Z to determine if the memory address can be within said range.
Parent Case Info
This is a continuation of application Ser. No. 199,143 filed Oct. 22, 1980, now abandoned.
US Referenced Citations (5)
Continuations (1)
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Number |
Date |
Country |
Parent |
199143 |
Oct 1980 |
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