Claims
- 1. A GPS receiver comprising:
address translation logic adapted to provide a plurality of translated addresses each based on an address from memory access logic; said memory access logic adapted to provide each said address to said address translation logic; memory adapted to store data in a plurality of memory locations corresponding to said plurality of translated addresses; and circuitry adapted to provide said data to said memory based on a signal received by the GPS receiver, wherein said data comprises a plurality of subsets each having a plurality of data elements.
- 2. The GPS receiver of claim 1 further comprising transform circuitry adapted to receive said data from consecutive ones of said plurality of memory locations and transform said data into a frequency domain to produce transformed data.
- 3. The GPS receiver of claim 1 wherein said circuitry comprises a plurality of correlators each providing a one of said plurality of subsets based on said signal.
- 4. The GPS receiver of claim 1 wherein said circuitry is further adapted to provide said data to said memory by multiplexing said plurality of subsets.
- 5. The GPS receiver of claim 1 wherein said address translation logic provides said plurality of translated addresses based on organizing said data such that each of said plurality of data elements associated with each of said plurality of subsets are grouped together in said memory.
- 6. The GPS receiver of claim 5 wherein each of said plurality of subsets corresponds to results of a correlation of said signal with a generated frequency and a generated code at a one of a plurality of time offsets.
- 7. The GPS receiver of claim 6 wherein each of said plurality of data elements in each of said plurality of subsets corresponds to a partial correlation sample from a time limited accumulation of data from the results of the correlation of said signal with said generated frequency and said generated code at said one of said plurality of time offsets.
- 8. The GPS receiver of claim 1 wherein said memory access logic comprises a direct memory access controller.
- 9. A GPS receiver comprising:
address translation logic adapted to provide a plurality of translated addresses each based on an address from memory access logic; said memory access logic adapted to provide said address to said address translation logic; memory adapted to store data in a plurality of memory locations corresponding to said plurality of translated addresses; circuitry adapted to provide said data to said memory based on a baseband signal, wherein said data comprises a plurality of subsets each having a plurality of data elements; and a receiver frontend adapted to receive a GPS signal and provide said baseband signal to said circuitry based on said GPS signal.
- 10. The GPS receiver of claim 9 further comprising transform circuitry adapted to receive said data from consecutive ones of said plurality of memory locations and transform said data into a frequency domain to produce transformed data.
- 11. The GPS receiver of claim 9 wherein said circuitry comprises a plurality of correlators each providing a one of said plurality of subsets based on said signal.
- 12. The GPS receiver of claim 9 wherein said circuitry is further adapted to provide said data to said memory by multiplexing said plurality of subsets.
- 13. The GPS receiver of claim 9 wherein said address translation logic provides said plurality of translated addresses based on organizing said data such that each of said plurality of data elements associated with each of said plurality of subsets are grouped together in said memory.
- 14. The GPS receiver of claim 13 wherein each of said plurality of subsets corresponds to results of a correlation of said signal with a generated frequency and a generated code at a one of a plurality of time offsets.
- 15. The GPS receiver of claim 14 wherein each of said plurality of data elements in each of said plurality of subsets corresponds to a partial correlation sample from a time limited accumulation of the results of the correlation of said signal with said generated frequency and said generated code at said one of said plurality of time offsets.
- 16. The GPS receiver of claim 9 wherein said memory access logic comprises a direct memory access controller.
- 17. A GPS receiver comprising:
means for providing a plurality of translated addresses each based on an address; means for providing each said address to said means for providing said plurality of translated addresses; means for storing data in a plurality of memory locations corresponding to said plurality of translated addresses; and means for providing said data to said means for storing said data based on a signal received by the GPS receiver, wherein said data comprises a plurality of subsets each having a plurality of data elements.
- 18. The GPS receiver of claim 17 further comprising means for receiving said data from consecutive ones of said plurality of memory locations and transforming said data into a frequency domain to produce transformed data
- 19. The GPS receiver of claim 17 wherein said means for providing said plurality of translated addresses provides said plurality of translated addresses based on organizing said data such that each of said plurality of data elements associated with each of said plurality of subsets are grouped together in said means for storing said data.
- 20. The GPS receiver of claim 19 wherein each of said plurality of subsets corresponds to results of a correlation of said signal with a generated frequency and a generated code at a one of a plurality of time offsets.
- 21. The GPS receiver of claim 20 wherein each of said plurality of data elements in each of said plurality of subsets corresponds to a partial correlation sample from a time limited accumulation of the results of the correlation of said signal with said generated frequency and said generated code at said one of said plurality of time offsets.
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
[0001] This U.S. patent application is related to the following concurrently filed U.S. patent applications:
[0002] i) USING FFT ENGINES TO PROCESS DECORRELATED GPS SIGNALS TO ESTABLISH FREQUENCIES OF RECEIVED SIGNALS by Warloe et al.;
[0003] ii) SAVING POWER IN A GPS RECEIVER BY CONTROLLING DOMAIN CLOCKING by Warloe et al.;
[0004] iii) AVOIDING INTERFERENCE TO A GPS RECEIVER FROM WIRELESS TRANSMISSIONS BY TIME MULTIPLEXING GPS RECEPTION by Warloe et al.; and
[0005] iv) IMPROVED GPS RECEIVER by Warloe et al., wherein these related U.S. patent applications are incorporated herein by reference in their entireties.