Patent Application
20050285831
This invention relates to the addressing of nematic liquid crystal displays having at least two stable states, in particular bistable nematic liquid crystal devices, in which the selection between stables states is made using pulses of opposite polarity. For the purposes of this specification the term nematic (which includes long pitch chiral nematic materials) shall be taken to include long pitch cholesteric materials.
One known multistable device is the bistable nematic liquid crystal described in International patent application WO97/14990 and is known as a zenithal bistable device (ZBD™). This device comprises a thin layer of nematic or long pitch cholesteric material contained between cell walls. One or both cell walls are surface treated with a surface alignment grating structure to permit liquid crystal molecules to adopt either of two pretilt angles in the same azimuthal plane at the surface. Opposite surfaces may have pretilt in differing azimuthal planes. The cell can be electrically switched between these two states by application of voltage pulses of suitable polarity which couples with the polarisation of the liquid crystal molecule induced by the surface such as the flexoelectric polarisation. By use of suitable polarisers, dyes etc the two states may be observed as dark and light states allowing information to be displayed which will persist after removal of a voltage until electrically switched to the other state. Various schemes of addressing this type of liquid crystal device are described in patent application WO00/52671.
Another further zenithal bistable nematic device is described in International Patent Application WO97/14990 which uses a liquid crystal material with a negative dielectric anisotropy.
Conventional monostable liquid crystal display devices, such as twisted nematic (TN) or supertwisted nematic (STN) devices, are addressed using rms addressing methods. Applying a suitable electric field across the cell causes the liquid crystal molecules to adopt a particular configuration which differs from the configuration of the monostable state induced by the surface alignment. When the rms voltage falls below a certain level the liquid crystal material relaxes to the monostable state. Various well known addressing schemes are used which rely on the ac rms voltage values. This is convenient because liquid crystal materials deteriorate when the applied voltage has a net dc for any substantial duration.
Another type of bistable device is the ferroelectric liquid crystal display (FLCD) which exhibits bistability in the smectic phase with suitable cell wall surface alignment treatments. In such a device the application of a pulse of suitable polarity, amplitude and duration will cause the liquid crystal material to switch from one state into the other. For instance a suitable positive pulse will cause the material to switch to a first state and application of a suitable negative pulse will cause the material to switch to the other state. Usually the cell configuration is such that one state is dark (or black) and the other is light (or white). However again the liquid crystal material degenerates under application of dc voltages and therefore most known FLCD addressing schemes tend to ensure that there is a net zero dc voltage, at least within the frame time. Also it is wished to avoid a net dc effect forcing one state to be preferred. A net zero dc voltage is where the integration of the applied voltages over time leads to a sum of zero.
There are many known schemes for addressing FLCDs. Due to the fact that switching of bistable nematic devices of the type described above also depends upon the polarity of the applied pulse many addressing schemes for ferroelectric devices may be suitable for addressing such bistable nematic liquid crystal devices.
There are many schemes of ‘line at a time’ addressing where data is continuously applied to one set of electrodes during the time taken to write an entire frame and the other set of electrodes is addressed one at a time. Two general types of line at a time addressing schemes are known, two field addressing and blanking.
In two field addressing a strobe waveform is applied to the row electrodes whilst a data waveform is applied is applied to the column electrodes. For bistable devices there are usually two different data waveforms, conveniently called ON and OFF, which may conveniently be a pulse of +Vd for one time slot and −Vd for another time period and its inverse, i.e. −Vd followed by +Vd. This allows for ease of dc balancing of the data waveforms within the time taken to address a single line. This is essential to prevent latching of a pixel into an unwanted state following several lines with the same data waveform. The data waveforms may also be designed to give appropriate latching, with three or more slots. For example, one time slot at +Vd, one at −Vd followed by one time slot of zero (0) volts, and the inverse waveform −Vd, +Vd, 0.
As used herein the terms row and columns are not intended to restrict the waveforms to application to a particular set of electrodes. Rather the terms are used simply to distinguish the two sets of electrodes and could be consistently interchanged throughout. Also, other electrodes are possible, from alphanumeric characters, to axial and radial circular electrodes.
In the simplest schemes a unipolar strobe pulse of one polarity is applied to each row in turn whilst one of the two data waveforms is applied simultaneously to the columns. The voltage levels are chosen such that combination of the strobe pulse and data ON or data OFF waveforms will either result in the liquid crystal material adopting the light state configuration or not. However this will only generally set all the pixels required to be light to adopt the light state. It is then necessary to readdress all the pixels using a unipolar strobe pulse of the opposite polarity in combination with the opposite data waveforms to set all the pixels that should be in the dark state to be in that state. Using strobe pulses of opposite polarity but equal amplitude and duration achieves dc balance. Other strobe schemes such as bipolar waveforms are also known.
One problem with this scheme however is the need to address the entire display twice to write one frame which doubles the time taken to address the entire display.
Another known scheme employs what is termed a blanking pulse. Here a pulse of sufficient voltage and duration is supplied to the/a row or rows ahead of the strobe pulse. The blanking pulse is adapted to be sufficient to ensure that all the pixels in that row adopt one state, usually the dark state, regardless of what, if any, data waveform might be being applied to the columns. Subsequently it is only necessary to cause those pixels desired to be light to adopt the light state using an appropriate strobe waveform. Hence the total addressing time of the display may be reduced. However, blanking to the dark state inherently means that the pixels intended to be in the light state for that frame are in the wrong state for the time between the blanking pulse and the subsequent addressing of that pixel. Thus the overall brightness of the device is reduced. Of course blanking to the light state is possible but again this deleteriously affects the display contrast.
Another problem with using a blanking pulse is the effect on operating window. The term operating window describes the range voltage levels and duration of pulses within which the display will operate correctly, despite temperature, cell gap, alignment variations that occur across a display panel (or from panel to panel in a production process). Obviously it is desired that the blanking pulse is sufficient to cause the liquid crystal material to adopt one particular configuration, irrespective of what data pulse may be supplied during the blanking process. However the strobe waveform needs to allow for discrimination between states depending on what data waveform is supplied. Incorrect design of the blank can limit the operating window for the strobe waveform.
Ideally the blanking pulse together with the strobe waveform should give dc balance. GB2, 314, 446 describes improvements in blanking pulses for FLCDs.
U.S. Pat. No. 5,963,186 and GB 2, 262, 831 describe a scheme wherein the strobe pulse may extend beyond the line address time for a particular row into a following row or rows. As used herein the term line address time shall be taken to mean the duration in which data specific for that particular row is being applied to the columns, i.e. often the time taken to write the appropriate ON or OFF waveforms to the columns that are appropriate for that particular row. U.S. Pat. No. 5,963,186 teaches that the strobe can be extended beyond the line address time into the following lines to give a total effective resultant which gives good switching properties but without causing incorrect switching. The effective line address time of a display addressed in this manner can be shortened resulting in a faster frame update rate or the voltage levels need to operate the display at the required rate may be reduced.
It should be noted that with multistable devices such as described the addressing schemes are designed such that the liquid crystal material remains in the desired stable configuration when the field is removed. This will be referred to hereinafter as latching. Application of a field will still cause the liquid crystal director profile to alter for a short period due to the rms effect of the applied field. However this does not necessarily cause the material to latch into a different stable state. Hence latching will be used the indicate that the resultant waveform at a particular pixel was sufficient to ensure that it remains in the desired stable state.
It is an object of the invention to provide schemes for addressing multistable nematic liquid crystal devices which are optimised therefor and which offer faster, lower voltage or wider operating windows than conventional schemes.
According to the present invention therefore there is provided a scheme for addressing a multistable nematic liquid crystal device having a layer of nematic liquid crystal material disposed between two cell walls and row and column electrodes disposed on the cell walls to form an addressable matrix of pixels, and having a cell wall surface treatment such that the liquid crystal material is latchable between at least two stable molecular configurations upon application of appropriate voltage pulses comprising the steps of applying a strobe waveform to each row electrode in a sequence and applying one of at least two data waveforms, to each column electrode simultaneously wherein each data waveform has a duration equal to the line address time and has a zero net dc value and wherein the strobe waveform has a net zero dc value over a whole frame time and comprises a blanking portion, which in combination with any data waveform will cause the liquid crystal material to adopt a first particular state, immediately preceding a discriminating portion, which in combination with one data waveform will cause the liquid crystal material to remain in the first stable state and in combination with the another data waveform to latch to the another stable state, characterised in that only one strobe waveform is applied to each row when addressing a particular frame and in that during the line address time wherein the appropriate data waveform is applied to each column for the pixels of a particular row at least part of the blanking portion and at least part of the discriminating portion is applied to that row.
Conveniently the liquid crystal material is latchable between two stable molecular configurations, i.e. the device is bistable. In this case there are preferably two data waveforms.
Multistable devices with more than two states could be used however. Here there could be a plurality of data waveforms, the number of different data waveforms being equal to the number of stable states. Multistable devices offer advantages in being able to produce greyscale. Multistability may be produced by having a pixel separated into two or more domains, each having a different grating producing bistability but latchable at different applied electrical energies. Therefore a data pulse may latch all of the pixel into one state or the other or latch part (one domain) of the pixel into one state whilst keeping the other part in the other state. Alternatively a single grating could be used which allows for more than one stable configuration.
Having the blanking portion of the strobe waveform immediately precede the discriminating portion reduces the amount of time that pixels may spend in the wrong latched state. Indeed at least part of the blanking portion is applied during the line address time for that row, i.e. the time at which the appropriate data waveform is being written, and as such the time that the pixel may spend in the wrongly latched state is minimised.
By incorporating a blanking portion as part of the strobe waveform there is no need for two field addressing. Also having the blanking portion immediately preceding the discriminating portion in the line addressing time maximises the possible addressing speed in other ways as will be described.
It might be helpful here to clarify what is meant by the various terms used. As mentioned a strobe waveform is applied to the row electrodes and data waveforms are applied to all column electrodes. The time taken to write an entire row is known as the line address time, and this is equivalent to the duration of the data waveform. The duration of the strobe waveform may be greater than the line address time. However a particular part of the strobe waveform is designed to coincide with the appropriate data waveforms for that row and it is this part of the strobe waveform that is referred to in the context of the line address time. The term blanking portion is taken to mean a part of the strobe waveform where a voltage is maintained of one polarity (although the actual voltage level may vary) and is sufficient to cause latching of the liquid crystal into one particular state irrespective of what data waveform might be applied to the column during the duration of the blanking portion. In the present invention, the blanking portion must be at least partly contained within the line address time. The term discriminating portion is then a part of the strobe waveform of opposite polarity to the blanking portion which also must be at least partly within the line address time. It is noted that obviously the data appropriate for that row will only be applied to columns during the line address time for that row and so the part of the discriminating portion that occurs within the line address time is what selects which state the liquid crystal latches into. However extending the discriminating portion beyond the line address time may aid the latching response as will be described later.
In one embodiment the whole of the blanking portion of the strobe waveform is applied to a row during the line address time when the appropriate data waveform is applied to each column.
Zenithal bistable devices may be designed to have an asymmetry in their latching response as will be described later. Thus it is easier to latch from a first state to the second than from the second to the first. The concept of ease of latching is thought of as less energy is required to latch, i.e. the product of the voltage and duration of pulse required to latch is lower. The present invention exploits this fact and enables a suitable strobe waveform to be applied that allows blanking to occur during the first part of the line address time, whatever data waveform is applied but allows discrimination between the two stable states towards the end of the line address time depending upon which data waveform is applied and still maintain dc balance.
Therefore the strobe waveform can be made to be the same duration as the data waveform in a single field addressing scheme.
The present invention is equally applicable to azimuthal bistable devices however such as are disclosed in European patent EP0744041 and U.S. Pat. No. 5,796,459. Any multistable liquid crystal devices where the latching between states depends on the polarity of the applied voltage can benefit from the present invention.
Conveniently the data waveforms may comprise a first waveform comprising a positive pulse followed by a negative pulse of equal duration and equal but opposite magnitude and a second waveform which is the inverse of the first waveform. The data waveform may also comprise a period of zero voltage.
In one embodiment of the present invention, the strobe waveform comprises a waveform which comprises a first pulse and a second pulse, the first and second pulse being of equal duration and equal and opposite magnitude. The polarity of the first pulse will depend on a number of factors including the liquid crystal material used, the cell geometry and the way in which the device is used as will be well understood by person skilled in the art.
A system wherein the data waveform is a two slot simple waveform and a single row waveform is applied during a frame address time, that waveform also being a two slot simple waveform offers advantages in speed and ease of addressing and the corresponding electronics needed to drive a cell.
Apart from causing blanking a pulse of opposite polarity immediately preceding the discriminating pulse of the strobe waveform can also make latching easier. When a field of a particular polarity is applied to a liquid crystal cells ions present in the liquid crystal material will start to migrate to the appropriate electrodes. Obviously the effect of the applied field will be to cause the ions to migrate to reduce the effect of the field. Thus the actual field across the cell will decay over time. When a field of the alternate polarity is then applied however the ions will tend to migrate in the opposite direction. The ions are relatively slow moving however and so immediately on reversal of the field the ionic effects will actually serve to enhance the field and so the effective applied voltage will be greater. Thus preceding the discriminating pulse with a pulse of opposite polarity will actually cause the discriminating pulse to initially have a larger effective amplitude. This will therefore enhance the latching characteristic of the liquid crystal material allowing for faster latching or a lower voltage to be used.
In another embodiment therefore the discriminating portion of the strobe waveform is immediately preceded by the blanking portion of opposite polarity and the blanking portion of the strobe pulse is applied to the row electrode before the appropriate data waveform is applied thereto, i.e. the blanking portion if pre-extended before the line address time into previous lines.
Note that the principle of using a pulse of opposite polarity before a discriminating potion would apply even if the pulse did not actually cause blanking. Therefore another aspect of this invention is the use of a strobe waveform having a discriminating portion of one polarity, immediately preceded by a first portion of opposite polarity, the length of the first portion extending beyond the line address time into previous lines. This could be used where a separate blanking pulse has already been applied earlier, or where two field operation is preferred. Conveniently the strobe waveform also has a dc balancing portion which immediately precedes the blanking portion. As the modulus of the voltage time product of the blanking portion may exceed the modulus of the voltage time product for the discriminating portion there is a need to dc balance the overall strobe waveform and a convenient way would be to have a pulse of appropriate polarity and duration precede the blanking portion of the strobe waveform. The dc balancing portion could be separate but as will be described later the rms effects of having the dc balancing portion immediately precede the blanking portion lead to this embodiment being preferred. The DC poling (or ionic) effect of the dc balancing pulse, also helps ensure the blanking action of the blanking portion of the waveform if the balancing pulse immediately precedes the blanking portion.
The longer the blanking portion the greater the ionic effect will be and so faster latching times and/or lower latching voltages will be possible. There is a duration longer than which this dc poling effect will have no further advantage, and may begin to cause some deleterious effects in the liquid crystal material. This will depend on the material used, and other variables such as the temperature of the display.
The duration of the discriminating portion of the strobe waveform may extend beyond the line address time during which the appropriate data waveform is applied to the columns into subsequent lines.
The discriminating portion of the strobe waveform must be sufficient that for the operating range of the device it can discriminate, in combination with the appropriate data waveform, between the different stable states of the device. However actual latching can be aided by a pulse extending beyond the line addressing time of that particular row. The person skilled in the art would be well aware of the effects of strobe extension in this manner as is described in U.S. Pat. No. 5,963,186 and U.S. Pat. No. 5,823,344. The amount of extension chosen, if any, could depend on some operating parameter such as the temperature.
Extending the duration of the discriminating portion of the strobe waveform again requires dc balance to be achieved. Conveniently therefore the modulus of the dc voltage time product of the blanking portion is equal to the modulus of the dc voltage time product of dc balancing portion and the discriminating portion. It is possible for the blanking portion to extend into previous line addressing times and the discriminating portion to extend into following line address times and achieve dc balance without the need for a dc balancing portion. However, as mentioned, it is preferred to have a dc balancing portion immediately preceding the blanking portion.
Whenever an electric field is applied there is a degree of ac poling of the liquid crystal material due to its RMS response. Where the strobe waveform is a series of short pulses of opposite polarity this ac poling of the liquid crystal material occurs even though the pulses are of insufficient duration to cause significant dc poling effect from the ions. The material behaves as a normal nematic material and is aligned by the field according to its dielectric anisotropy. For materials with a positive dielectric anisotropy the effect will be that the liquid crystal material tends to align with the field. This alignment will reduce contrast of the device as the liquid crystal material in the bulk of the device may be held in an incorrect state by the RMS effect of the applied field. However the effect of the ac poling will also concentrate the elastic distortion of the liquid crystal closer to the surface of the cell wall and therefore increase the magnitude of the flexoelectric polarisation in the vicinity of the grating. As the latching between states is a result of the resultant of the discriminating pulse and data waveform polarity coupling with the flexoelectric effect the latching of the liquid crystal material into either state is hence increased by pre-stressing the liquid crystal material by a certain amount of ac bias.
Therefore the strobe waveform may be preceded by an ac component. It should noted here that even a dc field would cause poling effect as described as the nematic material would be responding to the quadripolar effect of the field, i.e. the response of the liquid crystal material proportional to E squared. Therefore the term ac component should be taken to mean any applied field which has such an effect. The ac component is preferably a series of relatively short pulses of opposite polarity however to achieve dc balance and also to reduce problems in losing discrimination in latching. Further there may be ionic breakdown problems associated with long periods of applied dc.
Also the discriminating portion may be followed by a final portion of opposite polarity to the discriminating portion. This can provide for additional dc balancing and can reduce pixel pattern effects. Also after the field is removed it can be advantageous to reduce ionic effects as soon as possible and a portion of opposite polarity aids in regaining ionic equilibrium faster.
In another aspect of the present invention there is provided a multistable nematic liquid crystal device comprising a layer of nematic liquid crystal material disposed between two cell walls, at least one cell wall having a surface treatment such that the liquid crystal material is latchable between at least two stable molecular configurations upon application of appropriate voltage pulses, row and column electrodes disposed on the cell walls to form an addressable matrix of pixels, and driving means for applying a strobe waveform to each row electrode in a sequence and one of at least two data waveforms, to each column electrode simultaneously wherein each data waveform has a duration equal to the line address time and has a zero net dc value and wherein the strobe waveform has a net zero dc value over a whole frame time and comprises a blanking portion, which in combination with any data waveform will cause the liquid crystal material to adopt a first particular state, immediately preceding a discriminating portion, which in combination with one data waveform will cause the liquid crystal material to remain in the first stable state and in combination with the another data waveform to latch to the another stable state, characterised in that the driving means is adapted such that only one strobe waveform is applied to each row when addressing a particular frame and in that during the line address time wherein the appropriate data waveform is applied to each column for the pixels of a particular row at least part of the blanking portion and at least part of the discriminating portion is applied to that row.
Preferably the device includes means for optically distinguishing between the at least two stable liquid crystal configurations.
Conveniently the surface treatment is such that there are two stable liquid crystal states.
Preferably the surface treatment is adapted such that latching from a first stable state to a second stable state requires less energy than latching from the second stable state to the first.
A range of different device drivers for supplying the voltage waveforms to the row and column electrodes could be used but in some instances it is preferred to use commercially available STN drivers, currently used to address STN liquid crystal devices. STN drivers are readily available, reliable and inexpensive and therefore are useful for low cost applications.
Therefore in another aspect of the invention therefore there is provided a method for addressing a bistable nematic liquid crystal device having a layer of nematic liquid crystal material disposed between two cell walls and row and column electrodes disposed on the cell walls to form an addressable matrix of pixels, the liquid crystal material being latchable between two stable molecular configurations upon application of appropriate voltage pulses and having at least one row driver for applying voltages to said row electrodes and at least one column driver for applying voltages to said columns, the method comprising the steps of;
The method of this aspect of the invention can be implemented using STN drivers.
As will be explained in more detail later the STN drivers are arranged generally to output only a fixed number of voltage levels (four for the row driver and four for the column driver), all of the same polarity. As mentioned above voltage resultants of differing polarities are needed to achieve selective latching of the liquid crystal material at a pixel. A positive voltage resultant at a pixel can be achieved by having a positive voltage on the relevant row and no voltage on the relevant column. A negative voltage resultant is then achieved by having a positive voltage on the relevant column and no voltage on the row. Thus the method of this aspect of the invention uses voltage waveforms on the row and column electrodes which combine to form the required resultant—that is one having a blanking portion immediately preceding a discriminating portion.
It should be noted that when a high positive voltage is applied to a column, to achieve a negative resultant at a pixel being addressed, that voltage is also applied to all the other pixels on that column. To prevent unwanted switching of these pixels each non addressed row is addressed with a voltage waveform to reduce the voltage resultant. For instance a positive voltage applied to each non addressed row reduces the resultant at the non addressed rows.
Therefore this aspect of the present invention is akin to applying voltage reduction waveforms to the addressing schemes described above.
Using STN drivers requires the effective strobe signal to be wholly applied during the line address time for addressing the row. Also it is not possible to produce a zero voltage resultant at any time but with these exceptions the method of this aspect of the invention can be used to implement any of the resultant waveforms discussed with respect to the other aspects of the invention and in particular resultant waveforms may benefit from any of a dc poling portion prior to the blanking portion, an ac poling portion prior to the blanking portion and an ionic reduction portion after the discriminating portion.
The invention will now be described by way of example only with reference to the accompanying drawings of which;
a and 3b show a cross section of a stylised cell configuration illustrating two stable states,
A row driver 8 supplies voltage to each row electrode 6. Similarly a column driver 9 supplies voltage to each column electrode 7. Control of applied voltages is carried out by control logic 10 connected to voltage source 11 and clock 12.
Either side of the cell are polarisers 13, 13′ arranged with their polarisation axis substantially crossed with respect to one another and at an angle of substantially 45° to the alignment direction R, if any, on the adjacent wall 3, 4. Additionally one or more optical compensation layers 17 of, for example, stretched polymer may be added adjacent the liquid crystal layer 2 between cell wall and polariser. Of course, the skilled person will be aware of other embodiments that could be implemented using one polariser or no polarisers at all.
A partly reflecting mirror 16 may be arranged behind the cell 1 together with a light source 15. These allow the display to be seen in reflection and lit from behind in dull ambient lighting. For a transmissive device the mirror 16 may be omitted. Alternatively an internal reflecting surface may be used such as an internal Aluminium electrode.
Prior to assembly at least one of the cell walls 3, 4 are provided with a surface alignment grating to provide a bistable pretilt. The other surface may be provided with either a planar, tilted or homeotropic monostable surface or another bistable surface.
The surface alignment grating structures providing bistable pretilt may be manufactured using a variety of techniques as described in WO97/14990.
The cell is filled with any suitable nematic material for example E7, ZLI2293, TX2A (Merck), ZLI4788, ZLI4415 or MLC6608 (Merck).
Small amounts, for example 1-5%, of a dichroic dye may be incorporated into the liquid crystal material. This cell may be used with or without a polariser to provide colour, improve contrast, and brightness if the dye is fluorescent, or to operate as a guest host type device. The polariser(s) of the device may be rotated to optimise contrast between the two latched states of the device.
One suitable cell configuration to allow latching between the stable states is shown in
The near surface distortion in both states leads to a macroscopic flexoelectric polarisation, represented schematically by the vector F. A dc pulse can couple to this polarisation and, depending upon its polarity, will either favour or disfavour one of the states.
The latching characteristics of a bistable nematic liquid crystal cell of this type is shown in
It is noted that the arrangements described above with respect to
The actual energy to latch from one state to the other can be controlled by varying the shape of the surface alignment grating structure.
In some embodiments the latching response could be symmetrical however an asymmetric response can give improved performance.
The asymmetry in this response allows for a pulse of a particular duration and voltage to always cause latching to one state but in combination with an appropriate other pulse allow selective latching into the other state.
This is illustrated with respect to
A strobe voltage Vs may be applied for a duration τ such that the product is above the white-black latching curve 30 but below the black-white latching curve 32. This strobe pulse is combined with a data pulse however of a voltage Vd. It is well known that the resultant voltage, Vr across the cell at a particular pixel is equivalent to the voltage applied to the row minus the voltage applied to the column, in this case equal to Vs−Vd.
Of course both the strobe and data pulses may be positive or negative. Thus there are four possible resultants ±Vs±Vd. It should also be remembered that the white-black transition only occurs at a different polarity to the black-white transition as shown.
The resultant voltages of the effective pulse can be seen on
A first embodiment of the invention is therefore shown in
The first pulse of the strobe waveform is a blanking portion and will cause the liquid crystal material to latch into the black state (or white state depending upon the design) whatever data waveform is applied. It also ensures dc balancing of the strove waveform on each row.
The blanking first pulse can also cause the liquid crystal to change to a non stable configuration during the blanking portion due to the rms effect. This in effect pre-stresses the liquid crystal material at that pixel by coupling to the dielectric anisotropy. This concentrates the elastic distortion of the liquid crystal material closer to the grating surface which results in an increase of the magnitude of the flexoelectric polarisation. This can enable the liquid crystal to be latched to a stable state with less electrical energy, i.e. at a lower τV. Preferably the liquid crystal material has a positive dielectric anisotropy such that the material couples with the applied field. However in alternative arrangements materials with a negative dielectric anisotropy would be preferred.
Further the applied field of the first blanking pulse induces an ionic drift in the ions present in the liquid crystal material across the cell at that pixel. Positive ions will be drawn to a negative cell wall and negative ions to a positive cell wall. Build up of the ions at the cell walls will slowly start to reduce the effective field across the cell. The effect of the applied field causes the ionic species to move which could be seen as building up a reverse field themselves. When the polarity of the applied field is reversed the ions start to migrate in the other direction and thus the ionic effect reduces. However the ions move relatively slowly and thus take some time to migrate. Immediately after the field is reversed the effect of the accumulated ions will be relatively large and will slowly decay. However in the present invention the polarity reversal happens during the line address time synchronously as the appropriate data waveform is applied. Thus the build of ions due to the blanking pulse will increase the overall voltage of the resultant during the line address time where the appropriate data waveform is applied and thus the line address time and/or voltage may be reduced. This effect is related to the resistivity of the liquid crystal material. If the resistivity is too high (eg above 1011 Ωcm), the ionic poling effect is small, and the advantage of the pre-extended waveform is diminished. However, if the resistivity is low (eg below 108 Ωcm at 25° C.) the operating window is reduced by the ion induced reverse switching. The material chosen for the present study has a measured resistivity of 5×109 Ωcm.
The discriminating portion of the strobe pulse may also be extended beyond the line address time as is known to increase speed of operation. However the blanking potion may also be extended into previous lines to aid the latching response.
b illustrates a strobe which is four time slots long. The blanking portion is positive for two time slots and then the discriminating portion is negative for two time slots. This scheme is dc balanced.
For all these schemes latching again occurs with the discriminating portion and blanking occurs for the first part. For some applications blanking to the black state is preferred. However in some applications it will be preferred to blank to the white state.
The resultant waveforms are shown on the right hand side. Where the strobe is extended beyond the line address time the resultant may have different forms depending on the pixel pattern, i.e. the data being applied to the preceding and following rows. The dotted lines represent the possibilities.
Extending the discriminating part of the strobe waveform allows latching between states to occur at a lower voltage or in a shorter period. The device however must not latch into the wrong state due to later waveforms being applied. The operating window is defined by the worst case scenario as would be well understood by a person skilled in the art, that is the data waveform or pixel pattern that lead to the highest τV for the select, i.e. latch, resultant and the lowest τV for the non-select resultant.
Extending the blanking portion of the strobe waveform into preceding lines similarly ensures a wide blanking window of operating conditions. However the extended pulse of opposite polarity to the discriminating pulse also has the ionic polling effect mentioned above as well as increasing the amount of pre-stressing thus increasing latching speed. Also it ensures that the strobe waveform is dc balanced. Extending the blanking portion before the line address time gives greater time for the relatively slow moving ions to migrate.
This effect of increasing the latching response by use of a pulse of opposite polarity to a discriminating portion can be used in standard addressing schemes. A scheme using a separate blanking waveform earlier in the frame time can still benefit from having a strobe waveform having a pulse of opposite polarity immediately precede the discriminating portion, the pulse of opposite polarity extending before the line address time. This is somewhat contrary to what might be expected.
Experimental results for the schemes shown in
It can be seen that the greater the degree of extension the faster the possible latching line address time is. However the operating window is reduced.
Partly this will be due to the fact that extending the whole discriminating portion of the strobe means that the difference between a latching resultant waveform and non latching resultant waveform is less in relative terms. In other words the ratio of the data voltage to the entire discriminating portion of the strobe is being reduced by extension of the discriminating portion. Thus whilst extending the discriminating portion of the strobe would be expected to reduce the required line address time or reduce the voltage required there will also be less discrimination.
Further the first part of the pulse, the blanking pulse is a unipolar pulse and is not preceded by a pulse of the opposite polarity. Referring back to
The discriminating portion of the strobe waveform however has a prepulse of the opposite polarity and therefore is represented by curve 46. The effect therefore is that the fastest latching speed would be expected to be increased but that also the two curves have been moved closer together and hence the operating window has been reduced.
In another embodiment of the present invention therefore the strobe is extended into the preceding lines in an asymmetric fashion, i.e. there is more pre-extension than post extension relative to the part of the strobe waveform corresponding to the line address time. This not only moves the latching curve of the blanking portion but also maximises the effect of pre-stressing and ionic poling of the liquid crystal material. A suitable scheme is shown is
Here the strobe waveform has a first dc balancing portion 60, a blanking portion 62 and a discriminating portion 64. Again the line address time is two slots and the data waveforms are the same as schemes previously described. However the blanking portion 62 extends into the previous rows by a number of time slots, the length dc balancing portion 60 being equal to the number of slots by which the blanking portion is extended.
The dc balancing portion 60 not only ensures dc balancing but also serves to improve the efficiency of the blanking portion 62 by pre-stressing and pre-poling the liquid crystal material. The amount by which the strobe extends into the preceding rows may be greater than the line address time. If greater than the line address time it is possible that the dc balancing portion will be sufficient to latch the liquid crystal state into the opposite state to which it is to be blanked. This may have an effect on the efficacy of the blanking portion. However the liquid crystal material is also responding to the applied field and will, if a positive dielectric anisotropy liquid crystal material is used, tend to line up with the field which may counter this effect depending on the cell arrangement. The precise duration of the extension will be influenced by a number of factors such as effective operating window and contrast effects. The skilled person would be well aware of this and could readily determine an appropriate duration. Further the amount of extension may be varied to compensate for operating variations such as changes of temperature.
It can be seen that the fastest line address time is again increased with an extended scheme and the operating window, although reduced, remains relatively large.
In a further embodiment an additional amount of AC is applied before the blanking portion and dc balancing portion if present. As mentioned the effect of the AC field is to cause a liquid crystal material with a positive dielectric anisotropy to line up with the applied field thus increasing the flexoelectric polarisation.
Whilst it is simpler in driving circuitry to minimise the number of voltage levels of the row drivers to three, +Vs, −Vs and 0, the blanking portion need not be of the same voltage as the discriminating portion.
A summary of the results for various strobe waveforms is given in the table below. This table shows various strobe waveforms which are expressed in units of Vs. The slowest line address time (l.a.t.) which allows discrimination and fastest l.a.t. allowing discrimination are illustrated. The range is the ratio of the slowest l.a.t. to the fastest l.a.t. and gives and indication of the operating range. Where the strobe waveform has been illustrated in the drawings the reference is given as the results. The period of the line address time is indicated in bold.
The first waveform is the unextended strobe consisting of two pulses of opposite polarity and the next two waveforms show the effect of increasing both the blanking portion and the discriminating portion. An increase in speed for latching between states is observed but the operating range is reduced. The next two waveforms show extension of the blanking portion along with a dc balancing portion. Here the range is preserved and faster latching observed. The next two waveforms have a certain amount of ac biasing and, at these conditions, allow a greater operating range.
Finally the last two waveforms, which are similar to the generic waveform shown in
Further results on addressing schemes according to the present invention were obtained using a cell of different geometry. Again a display such as described in WO97/14990 was used however in this cell the liquid crystal material had a twisted nematic geometry. That is, one surface had a grating designed to give zenithal bistability and the other surface was a conventional planar homogeneous surface formed, for example, by rubbing a polymer coated surface or using photo-alignment techniques. The preferred alignment direction (e.g. rubbing direction) of this other surface is set at an angle (90° in this example) to the orientation of the director at the other surface when in the defect state. In this cell, the defect state forms a twisted (90°) nematic configuration and the continuous (or non-defect) state forms a hybrid aligned or HAN geometry. The liquid crystal material used was the positive Δε liquid crystal mixture MLC 6204 available from E Merck. The device was chosen to be 4.4 μm so that it operated in the first minimum configuration well known to those skilled in the art of TN LCDs. This allowed the device to be used either between crossed polarisers, or with parallel polarisers, to give good optical contrast between the states. All of the results shown here were taken with a crossed polariser configuration, so that the defect (TN) state was strongly transmissive (white) and the continuous (HAN) state appeared weakly transmissive (ie black). The following results were taken at 25° C. and used a 5V bipolar data waveform of two time slots.
This figure clearly demonstrates that the state of the pixel after the strobe in each frame is determined by the data applied during the line address time. As well as the improved voltage/speed of operation noted earlier, this type of operation also allows the highest contrast and brightness to be achieved, since each pixel spends the least time possible in the incorrect state. For example, a pixel that should be white between consecutive frames should only be blanked black for the shortest time, and this is immediately before the pixel is returned to its desired white state.
Again using the strobe waveform shown in
All the schemes described herein have been using a two slot data waveform. The skilled person would readily understand however that three or more slot data schemes could be used that the waveforms could include a part which is zero for some time or different magnitudes, for instance −2Vd, +Vd, +Vd. One suitable scheme is shown in
Preferably in such a scheme the field reversal in the strobe during the line address time is synchronised with the field reversal in the data waveform. This design gives two slots of the strobe to latch the cell, thereby leading to a faster or lower voltage latching. An advantage of using this kind of strobe over simple pre-extension is that as the data voltage is zero for the last time slot so that the latching portion always has the same amplitude irrespective of the data on the preceding line. This means that there is a lower pixel pattern dependence and therefore a wider operating range.
It is noted that a combination of the waveforms described herein may be used to provide a wide range of operating conditions, any particular waveform being used to give the required speed, voltage and operating window for a given set of conditions.
Where the strobe waveform is greater than the line address time as described above it may be advantageous to address the display array in a manner other than by subsequently addressing adjacent lines.
All of the embodiments described herein have used bistable devices. Multistable devices could with more than two states may be used with an appropriate number of data waveforms for the number of stable states. The data waveforms could then have different amplitudes, for instance three different two slot data waveforms for a tristable device could be (0,0), (+Vd, −Vd), (+2Vd, −2Vd) or similar. Alternatively or additionally the phase of the data waveforms could be altered so that the resultant when combined with the discriminating portion of the strobe waveform is varied.
The present invention can be implemented using a range of driving circuitry. However it would be advantageous to use commercially available electronic device drivers presently used to address STN devices, termed STN drivers, as such drivers are readily available at low cost and high reliability. In another aspect of the invention therefore the addressing scheme is implemented using STN drivers.
The host microcontroller 301 runs the application software for the particular display application. When a new image is required a display image is written to the RAM of the microcontroller via a display routine. Display control software then reads the bitmap stored in the display RAM and writes it to a display module, taking temperature compensation into account.
The microcontroller 301 provides each common (row) driver 304 with a clock signal ROW_CLK which clocks the driver's shift register. The SYNC signal is input to the shift register and ripples through the shift register to select each active row in turn.
Each common (row) driver also has a DISPOFF input which disables the drivers when the input is low, i.e. a DISPOFF signal of logic 1 enables the drivers and a signal of logic 0 disables the drivers.
Each driver also receives a modulation signal M. Changing the level on this signal inverts the output voltages generated by the row and column drivers as will be described in more detail below. In driving an STN device the M signal is used to maintain DC balance. The M signal for the row drivers M_ROW may be connected to the same I/O port of the microcontroller 301 as for the columns M_COL.
The column drivers 305 also receive a clock signal DATA_CLK and an M signal. Data is supplied to the driver on parallel lines D0 . . . D7 (for an eight bit driver). The latch pulse signal LP is used by the segment (column) driver to transfer the column data from the input shift register to the output data register.
When connected to a matrix display conventional STN drivers are capable of outputting one of six different voltage levels, referred to as V0, V1, V2, V3, V4 and V5. V5 is usually the lowest output voltage and in this arrangement is connected to ground (0V). V0, the highest output, is also referred to as VLCD. V1, V2, V3 and V4 are generated by the LCD power supply circuitry 302 for example either using a buffered resistor ladder arrangement (with fixed or programmable bias voltage) or by generating a fixed voltage and using op-amps to multiply and/or subtract the various voltages.
It will be apparent that this arrangement allows any one driver to output voltages of one polarity only and as mentioned bistable liquid crystal devices require polarity dependent switching. The addressing scheme therefore relies on an appropriate voltage being supplied to the row and the column for each pixel to create a voltage resultant of the correct polarity. For instance, using the convention that the resultant voltage at any pixel is equal to the voltage on the relevant row minus the voltage on the relevant column, if the row voltage was +22V and the column voltage was 0V the resultant would be +22V. However with a voltage of 0V on the row and +22V on the column the resultant is −22V. Therefore both positive and negative resultants can be achieved by appropriate application of voltage to both the rows and the columns.
It will be appreciated that although a positive voltage, +Vs say, can be implemented by applying Vs to the row, generating a negative resultant requires a voltage of at least Vs to be generated on the column.
It would be possible to arrange a driver to be able to output both positive and negative voltages but STN drivers have a maximum operable voltage range. Therefore a 24V driver can only create a maximum difference in output of 24V. This could be arranged so that the output varies from +12V to −12V utilising the full 24V range. The row driver could then be arranged to output a +Vs of +12V and a −Vs of −12V. However if instead the row driver output 0V to 24V and it was combined with a column driver of the same range the resultant range of −24V to +24V could be achieved, i.e. a range of 48V. Therefore using STN drivers in this manner reduces the voltages that have to be applied to the rows for addressing whilst maintaining a large voltage swing.
The values of V0 to V5 are then arranged to provide selective switching as described previously. The voltage levels are generally calculated in terms of Vs and Vd. V0 (or VLCD) is the highest output and so is equal to Vs+Vd. The relationship of the other voltage levels is shown in table 1 below
Each of the row and column drivers actually only outputs any four of these voltage levels. The row drivers are provided with voltage levels V0, V1, V4 and V5 and the column drivers with V0, V2, V3 and V5. The voltages generated by the row (common) and column (segment) drivers have a standard relationship to the row or column data value, the value of the M signal and the DISPOFF signal as summarised in table 2 below where H indicates a high value (logic 1) and L a low value (logic 0).
Table 2 can be re-arranged to show the pixel resultants in terms of V0 . . . V5, Vs and Vd and also example voltages as shown in
An active row, i.e. the row being addressed, is selected by applying an H signal to that row and an L signal to all the other rows. Thus when M is high the active row is at a voltage of V5 (0V) and when M is low the active row is at V0 (Vs+Vd). The column drivers receive the same M signal but the voltage output depends on the column data applied. A high M signal (during which the row voltage is 0V) with a column data H gives an output on the relevant column of V0 (Vs+Vd). The resultant, the row voltage minus the column voltage, is then −(Vs+Vd) which would latch the pixel to one state. If M was high and the column data was low the column voltage would be V2 (Vs−Vd) and the resultant would be −(Vs−Vd) which would be insufficient to cause latching. Similarly if M was low (the active row is at Vs+Vd) a high data signal on the column driver (column at V5=0V) gives a resultant of +(Vs+Vd) which would cause latching to the other state and a low data signal on the column driver (output at V3=2Vd) gives a resultant of +(Vs−Vd) which would not cause latching.
This illustrates that for an active row (data on the row is high) a data of logic 1 (H) on the column data gives a switching resultant and a data of logic 0 (L) on the column data gives a non-switching resultant. The polarity of the resultant depends on the M signal and changing the M signal effectively changes the polarity of the resultant. Thus a bipolar pulse can be achieved by changing the M signal without actually changing the data on either the row or the column drivers.
For a non-active row (i.e. the row data is L) the row is held at a voltage of V1 (Vs) when M is high and V4 (Vd) when M is low. The select data on the column, i.e. column data is H, gives a column output of V0 (Vs+Vd) and V5 (0V) when M is high and low respectively leading to respective resultants of −Vd and +Vd. The non-select data (L) on the column driver gives an output of V2 (Vs−Vd) and V3 (2Vd) respectively leading to resultants of +Vd and −Vd respectively.
It should be clear therefore that on all non-active rows the resultants will be +Vd or −Vd whatever the column data which obviously will not cause latching. For an active row a latching resultant can be achieved by applying a data 1 to the appropriate column data and a non-switching resultant by applying a data 0. The polarity of each of the resultants can be inverted by changing to M signal from a 1 to a 0 or vice versa.
Therefore any of the resultant waveforms described above can be implemented using this aspect of the invention with the exception of waveforms which have a 0V resultant at any time—it will be apparent that it is not possible to achieve a 0V resultant without disabling an entire driver through use of the DISPOFF signal.
For instance consider the waveforms shown in
Using STN drivers the driver would receive a data 1 for row 1 throughout the two time slots to maintain it as the active row but after one time slot the M signal would switch from 1 to 0. Row 2, non active during this period receives data 0. The pixel in column 1 is receiving the select data and so the column data is 1, again through the whole period although as mentioned M does change after the first slot. As seen above this means the resultant voltage for the pixel at row 1 for the first time slot (M=1, Row data=1, Col data=1) is −(Vs+Vd). In the second slot (M=0, Row data=1, Col data=1) the resultant is +(Vs+Vd). Therefore the resultant voltage waveform at the pixel is the same as if the waveforms shown in
Therefore the STN drivers create on each pixel on an active row a voltage resultant which has a blanking portion (latches each pixel to one stable state) immediately preceding a discriminating portion which selectively latches to the other stable state or not depending on the data for the particular column. On the non-active rows the voltage resultant for all pixels is insufficient to latch the pixel away from the stable state it is in.
One can therefore think of the driving scheme of the present invention as akin to using voltage reduction waveforms, i.e. the actual voltage waveforms applied to the rows can be obtained by taking the addressing scheme of
It will be apparent to one skilled in the art that the use of STN drivers requires careful arrangement of the voltages on the rows and columns to achieve the desired resultants and that during the line address time of one row a voltage waveform is applied to all other rows (as mentioned this can be seen as being akin to a voltage reduction waveform applied to the strobe and data waveforms previously described). This means however that the strobe for one row can not extend beyond the line address time for that row as described in some embodiments above.
The skilled person would be well aware of the various STN drivers which could be used to implement the present invention. Typical STN drivers, i.e. passive matrix common and segment drivers include the following; Samsung S6B0741, S6B1713 and s1d0605; Solomon Systech SSD1701; Novatech NT7701 and NT7702, Seiko Epsom S1D17A03. The skilled person would be well aware of the type of drivers termed STN drivers (or five level drivers) and all have the same basic characteristics as discussed above. However for some devices the pin names used vary from those described above (although they have the same function). Table 3 below compares the pin names described above and shown in
Where [COM] or [SEG] is indicated, this reflects the COMmon or SEGment mode of operation of a dual Common/Segment driver IC.
Time period 3401 represents the line address time for the first row, time period 3402 that for the second row and so on. In the present example the line address time is six time slots long although other schemes could of course be used. The row signals Row SR(1), Row SR(2) and Row SR(3) indicate the data signal for rows 1, 2 and 3 respectively. It can be seen that during time period 3301 the signal on row 1 is high (logic 1) and that row is active whilst the signal on rows 2 and 3 is low (logic 0). In time period 3402 the data for row 2 is high and all other rows are low. In this manner the rows are selected sequentially, the active row being changed by the clock signal ROW_CLK.
Note that the row data for an active row is held at logic 1 throughout the whole of the relevant line address time but the M signal is changed twice during each line address time, between the second and third time slots and also between the fifth and sixth time slots. This changes the voltage output on the row from high to low to high or vice versa depending whether it is an active row or now. The output voltages on rows 1 and 2 are shown by the signals Row Driver 1 o/p and Row Driver 2 o/p.
The column data on lines D0 . . . D7 are clocked into the input shift register on the DATA_CLK signal. The LP signal then causes transfer of the information to the output register.
The column data is arranged, in this example, to blank the pixel into a white state in the first four time slots and then either latch or not latch to the black state in the last two time slots. For pixel intended to be white the column data is logic 1 for the first 4 time slots and then logic 0 for the last two time slots. For a pixel to be latched black the column data is logic 1 for all six time slots.
The resultant column outputs are shown for latching white and black; White Col Drv o/p and Black Col Drv output. As the black column is logic 1 all the time the signal changes from low to high to low with the change in M. This results in a resultant voltage on the active row shown as Black Pixel Row 1. The voltage starts at +(Vs+Vd) which as discussed previously provides dc poling of the liquid crystal material. Between time slots 2 and 3 the M signal changes with no change to the data on the row or column. This inverts the voltage level to −(Vs+Vd). This blanks the pixel into the white state. Between time slots five and six the M signal is changed again but again there has been no change to the column data and so the voltage is switched back to +(Vs+Vd) which latches the pixel into the black state.
For a pixel intended white the data on the column is again logic 1 for the first four time slots which, on an active row as illustrated by White Pixel Row 1, results in a switch from +(Vs+Vd) to −(Vs+Vd) between time slots 2 and 3 blanking the pixel white. At time slot five however the data on the column changes to logic 0 but there is no change in the M signal. Thus the voltage resultant level is still of negative polarity but is reduced to −(Vs−Vd). At time slot 6 the change in the M signal inverts the resultant voltage to +(Vs−Vd). This swing is insufficient to latch the pixel and so the pixel remains white. Thus in a six slot switching scheme the row may be blanked and selectively addressed.
As the column data changes from logic 1 to logic 0 during the line address time column data has to be loaded into the input register twice per line address time. During the first four time slots of the line address time, the selective data is clocked into the input register and then transferred to the output register at the falling edge of a first latch pulse (LP). Then during the last two time slots, the selective portion of the addressing cycle, the shift register needs to clock in the new column data (i.e. all logic 1) for the first part of the next data waveform. At present there is a limit to how fast one can clock in the data to the input register. Given this needs to be clocked in twice the fastest possible line address time would be twice the speed at which the data can be read into the driver. Further updating the column data is a significant power consumption in the writing process and reducing the number of updates reduces the power requirement.
An alternative scheme is shown in
It will be apparent that in this scheme the voltage resultant at a pixel to be latched white does not exceed |Vs−Vd|. However it will be remembered that latching of a liquid crystal material depends not only on the voltage level applied but also on the duration of the pulse. Thus a voltage of −(Vs−Vd) applied for two time slots may be sufficient to latch to the white state white a voltage of +(Vs−Vd) for one time slot is insufficient to latch to the black state. The duration of the blanking portion can be set as necessary to allow blanking. Additionally or alternatively the liquid crystal device may be designed so that it requires less energy to latch from the black to the white state than the other way round. Thus a voltage of −(Vs−Vd) may be sufficient to latch to the white state whereas a voltage of +(Vs−Vd) is insufficient to latch to black again allowing discrimination.
Therefore an addressing scheme using STN drivers can be designed where the data on the column is the same throughout the addressing period thus needing only one read operation and modulation is achieved by modulation of the M signal.
The scheme may also be used to perform partial update of a device. Where only part of a device is to be updated the panel could be quickly scanned with waveforms on the rows and columns that do not cause latching until the start line for an addressed block is reached. At this point the block is addressed to update the image as described above. The rest of the device could then again be quickly scanned to complete the frame. It should be noted that there could be more than one separated blocks to be updated.
As mentioned above the microcontroller may perform temperature compensation in response to changes in temperature of the liquid crystal device as monitored by an embedded temperature sensor. As the temperature changes the time/voltage characteristics of the liquid crystal material changes. At lower temperatures the liquid crystal material needs more time and/or a greater voltage to latch between states. Therefore the microcontroller can change the maximum voltage level, VLCD, and/or the line address time to compensate for any temperature changes. It may also swap between an addressing scheme as described with reference to
For example imagine a liquid crystal device is designed for operation at room temperature and has 22V range drivers and a microprocessor which can update the column driver register in 100 microseconds. At room temperature the device may be designed to operate using a scheme as shown in
If the temperature went down the voltage level VLCD could be increased to compensate until the maximum value of 22V was reached. After this stage has been reached the line address time could be increased to allow for decreased temperature. This is illustrated in
If however the temperature increased the level of VLCD could be dropped to compensate. The drivers do however have a minimum operating voltage, say 7V. Therefore VLCD can not be dropped below this voltage level. If the temperature went higher than could be compensated for by voltage reduction alone (T2) the line address time would have to be shortened to compensate. At some point above this temperature the addressing scheme may shift to that shown in
Note in the discussion above shortening or extending the line address time may shorten or extend the blanking portion more or less than the discriminating portion as required, that it the whole waveform need not be simply scaled up or down.
The present invention therefore also allows use of STN drivers to address bistable nematic liquid crystal devices. Any of the waveforms of the present invention can be implemented using STN drivers—with the exception of those which require a zero voltage resultant and bearing in mind that the strobe must be applied during the line address time. However STN drivers could implement resultant waveforms that use any of the advantages of ac poling, dc poling and ionic reduction as described herein.
It should be noted that whilst all of the embodiments shown have used zenithal bistable devices the invention is equally applicable to azimuthally bistable devices such as described in European patent EP0744041 or U.S. Pat. No. 5,796,459.
Other embodiments and schemes of the present invention will be apparent to the skilled person and this invention is not restricted to any of the embodiments shown herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0022055.8 | Sep 2000 | GB | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10363465 | Mar 2003 | US |
| Child | 11120185 | May 2005 | US |
