ADJUSTABLE AND BUFFERED REFERENCE FOR ADC RESOLUTION AND ACCURACY ENHANCEMENTS

Abstract

An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

Description

TECHNICAL FIELD

This Application is directed, in general, to an adjustable reference for an Analog to Digital Converter (ADC) and, more specifically, to an adjustable and buffered reference for an ADC resolution and accuracy enhancements.

BACKGROUND

Increased demand on ADC performance is imposing harder and harder requirements on the ADC resolution, resulting in longer design cycles, facing semiconductor technology challenges.

The demand on ADC accuracy and resolution is increasing. Especially for new μC architectures, being under cost pressure and having to migrate to cost optimized process nodes for digital, it is difficult to keep up with the integration of high performance of analog, like ADCs.

Therefore, there is a need in the art as understood by the present inventors to addresses at least some of the concerns of the usage of the prior art.

SUMMARY

A first aspect provides an apparatus as described herein.

A second aspect provides an apparatus, comprising: an analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

A third aspect provides an apparatus, comprising: means for an analog to digital conversion (ADC); a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is now made to the following descriptions:

FIG. 1 illustrates an adjustable and buffered reference for an ADC system 100.

DETAILED DESCRIPTION

Turning to FIG. 1, illustrated is one aspect of an adjustable and buffered reference for an ADC system 100. An ADC core 110 receives input. The ADC core 110 receives Vref+ and Vreg− two input signals. By a reference voltage generator 130. The ADC core 110 also controls inputs of the window comparator 120, to determine whether the inputs are to be conveyed to the window comparator 120 from the ADC core itself, or from an input directly. The window comparator 120 is then used to control the reference voltage generator 130, which generates V ref+ and Vref−, and also receives the bandgap reference 140 as a basis of control.

Generally, the window comparator 120 controls and switches the selected reference voltage range used for input comparison, and delivers and contributes to the AD conversion result. The window comparator 120 uses the conversion result to control the reference voltage generator 130.

Generally, in the system 100, instead of increasing only the number of ADC bits (10 bit, 12 bit, 16 bit . . . ) an intelligent method of adjusting the reference voltages to the input signal range is used by the window comparator 120, and thus avoid, on one hand, wasting ADC resolution, or even to focus the ADC resolution to a limited input signal range, and thus use the ADC resolution in an optimum way. Moving to dynamic reference voltage range switching by the window comparator 120 allows even focusing the entire ADC resolution to a certain input range interval. Compared to an ADC solution, where the reference voltage is fixed to OV-Vref+, this would reduce the required number of bits of the ADC, to achieve the same resolution and accuracy.

The straight forward solution, increasing the number of bits of the ADC is imposing more and more risk on the implementation side, increasing the risks in the analog design, especially on mixed signal devices.

In a further aspect, generally, Instead of increasing the number of bits of the ADC from 10 bit to 12 bit to 16 bit and more, a lower resolution ADC could be used. The approach of the present disclosure would be achieved by adjusting the ADC range by a configurable and buffered reference source for both positive and negative voltage reference, dependent on the input signal range.

In a yet further aspect, a fast 10 bit, 12 bit ADC, capable of operation with lowest possible reference voltage difference (Vref−/Vref+). The reference voltage reference generator 130 can be a multiplexer e.g. resistive ladder. Two reference voltage buffers, supplying the resulting voltage references, such as selected from VsRef+ and VsRef−.

In one example implementation, the system 100 is employed in a Temperature Sensor with analog output for temperature-range output levels in the range of 500 mV-1200 mV. However, the Goal is 0.7 mV resolution

In the prior art, this can be achieved by a 12 bit ADC and 1.5V reference (OV/1.5V). However, with the approach of the present disclosure, a focusing of the ADC range to 500 mV/1200 mV a 10 Bit ADC would be sufficient.

Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.

Claims

1. An apparatus as described herein.

2. An apparatus, comprising: an analog to digital converter (ADC) core;a reference voltage generator coupled to an input of the ADC core;a bandgap reference coupled to the reference voltage generator; anda window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

3. The apparatus of claim 2, wherein the ADC resolution is mapped to an effective number of bits of a targeted signal input range.

4. The apparatus of claim 2, wherein the ADC core is a ten bit ADC core.

5. The apparatus of claim 2, wherein the reference voltage generator comprises a voltage reference multiplexer.

6. The apparatus of claim 5, further comprising a plurality of voltage taps, selectable/available for the window comparator and ADC, to support the focus of the ADC range, to the measured ADC input signal.

7. The apparatus of claim 5, wherein the voltage reference multiplexer comprises a resistive ladder.

8. An apparatus, comprising: means for an analog to digital conversion (ADC);a reference voltage generator coupled to an input of the ADC core;a bandgap reference coupled to the reference voltage generator; anda window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

9. The apparatus of claim 8, wherein the ADC resolution is mapped to an effective number of bits of a targeted signal input range.

10. The apparatus of claim 8, wherein the means for analog to digital conversion is a ten bit ADC core.

11. The apparatus of claim 8, wherein the reference voltage generator comprises a voltage reference multiplexer.

12. The apparatus of claim 8, further comprising a plurality of voltage taps, selectable/available for the window comparator and ADC, to support the focus of the ADC range, to the measured ADC input signal

13. The apparatus of claim 8, wherein the voltage reference multiplexer comprises a resistive ladder.