Claims
- 1. An adjustable duty cycle clock generator comprising:
- (a) a first delay line, for delaying an input clock, having an input coupled to receive the input clock and an output;
- (b) a programmable second delay line, for delaying an input clock, having an input coupled to receive the input clock and an output;
- (c) a latch having a set input, a reset input, and an output;
- (d) a first edge detector coupled between the output of the first delay line and the set input on the latch, to detect edges of a first polarity and to generate a pulse only when an edge of the first polarity is detected; and,
- (e) a second edge detector coupled between the output of the second delay line and the reset input on the latch, to detect edges of a second polarity opposite that of the first polarity and to generate a pulse only when an edge of the second polarity is detected.
- 2. The adjustable duty cycle clock generator as recited in claim 1 wherein the first delay line has a fixed delay.
- 3. The adjustable duty cycle clock generator as recited in claim 1 further comprising (f) a second latch having set and reset inputs cross coupled with respect to the set and reset inputs of the latch in (c) and having a complimentary output to the output of the latch in (c).
- 4. The adjustable duty cycle clock generator as recited in claim 1 wherein the first edge detector (d) detects rising edges.
- 5. The adjustable duty cycle clock generator as recited in claim 1 wherein the second edge detector (e) detects failing edges.
- 6. An adjustable duty cycle clock generator comprising:
- (a) first delay line means, coupled to receive an input clock, for delaying the input clock a first delay time to control low time of an adjustable duty cycle clock signal;
- (b) programmable second delay line means, coupled to receive the input clock, for delaying the input clock a second delay time to control high time of the adjustable duty cycle clock signal;
- (c) first edge detector means, coupled to the first delay line means, for generating a pulse responsive only to detecting an edge on the input clock of a first polarity which was delayed for the first delay time;
- (d) second edge detector means, coupled to the second delay line means, for generating a pulse responsive only to detecting an edge on the input clock of a second polarity opposite that of the first polarity which was delayed for the second delay time; and,
- (e) S-R latch means, responsive to the first and second edge detector means, for generating the adjustable duty cycle clock signal.
- 7. The adjustable duty cycle clock generator as recited in claim 6 wherein the first delay time is fixed.
- 8. The adjustable duty cycle clock generator as recited in claim 6 further comprising (f) second S-R latch means cross coupled with respect to the S-R latch means in (e), for further generating a complimentary adjustable duty cycle clock signal.
- 9. The adjustable duty cycle clock generator as recited in claim 6 wherein the first edge detector means (c) detects rising edges.
- 10. The adjustable duty cycle clock generator as recited in claim 6 wherein the second edge detector means (d) detects falling edges.
- 11. A method of generating an adjustable duty cycle clock signal comprising the steps of:
- (a) delaying an input clock signal a first delay time to produce a first delayed signal to control low time of the adjustable duty cycle clock signal;
- (b) delaying the input clock signal a programmable second delay time to produce a second delayed signal to control high time of the adjustable duty cycle clock signal;
- (c) generating a pulse responsive only to detecting an edge of a first polarity on the first delayed signal;
- (d) generating a pulse responsive only to detecting an edge on the second delayed signal of a second polarity opposite that of the first polarity; and,
- (e) generating the adjustable duty cycle clock signal in response to steps (c) and (d).
- 12. The method as recited in claim 11 wherein the first delay time in step (a) is fixed.
- 13. The method as recited in claim 11 further comprising step (f) generating a complimentary adjustable duty cycle clock signal in response to steps (c) and (d).
- 14. The method as recited in claim 11 wherein the edge in step (c) is a rising edge.
- 15. The method as recited in claim 11 wherein the edge in step (d) is a falling edge.
CROSS-REFERENCES TO RELATED APPLICATIONS
This patent is related to commonly assigned U.S. patent application Ser. No. 08/413,199 (now U.S. Pat. No. 5,550,499) entitled "Single Delay Line Adjustable Duty Cycle Clock Generator", concurrently filed herewith.
US Referenced Citations (8)
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