Patent Application
20160182156
This disclosure relates configuration of signal reception circuitry. This disclosure also relates to signal reception circuitry in optical receivers.
High speed networks form part of the backbone of what has become indispensable worldwide data connectivity. The networks include wireless, optical, and coaxial connections between devices. Optical networking provides for high throughput data channels and is used to form backbone connections in many high-speed data networks. As consumer demand for bandwidth increases, the installed base of optical networking components increasingly pushes the high-throughput optical network closer to the consumer premises. Improvements in optical component operation will ease deployment as the installed base increases.
The discussion below concerns techniques and architectures for addressing configuration inputs in an adjustable receiver with configurable parameters. The techniques and architectures may allow for independent parameter addressing through a compact set of pins. Through these pins, virtually any number of parameters for the adjustable receiver may be controlled. In an example system, the adjustable receiver may include a trans-impedance amplifier (TIA) for an optical receiver, such as a receiver optical subassembly (ROSA). The addressable parameters may be automatically controlled. For example, digital signal processing (DSP) circuitry for processing received signals may control the adjustable receiver via feedback controls.
The device 100 may include optical receiver components 102 (e.g., photodiodes or other detection circuitry, ROSAs, coherent receivers, modulators, or other components) to support the reception of optical communication signals, one or more processors 104 to support execution of applications and control the general operation of the device. The device 100 may include memory 106 for execution support and storage of system instructions 108 and operational parameters 112. Signal processing circuitry 114 (e.g., Analog to Digital Converters (ADCs), baseband processors, digital-to-analog converters (DACs), and/or other signal processing circuits) may also be included to support reception of signals. The signal processing circuitry 114 may include amplifiers to adjust input signal levels to selected output levels. The signal processing circuitry 114 may also include an application specific component (e.g. a demodulator, or other application specific component) to process received signals.
In some cases, the adjustable receiver may allow for addressable adjustment one or more parameters. The parameters may be stored in any of the system circuitry, including the memory 106. The signal processing circuitry 114 may send signals to adjust the addressable parameters in the adjustable receiver. The optical receiver may include reception parameters 103 for control detector values, sensor settings and/or other parameters for reception. The reception parameters may be stored in addressable memory registers. The signal processing circuitry 114 may send commands to control operations of the optical receiver. The commands may be addressed to the individual parameters controlling reception in the optical receiver. For example, the signal processing circuitry 114 may implement a feedback control loop to maintain one or more signal level or signal quality thresholds and/or other signal characteristics by adjusting the adjustable amplifier in real-time or near real-time. The device 100 may also include a user interface 116 to allow for user operation of the device 100.
The signal processing circuitry may apply adjustment criteria to the signal (210). For example, the adjustment criteria may include signal level or quality thresholds. In an example scenario, signal amplitude of the signal may be lower than a selected threshold (e.g., a pre-stored or pre-determined threshold) specified by an adjustable or non-adjustable parameter. In response, the adjustment logic 200 may select a gain parameter of the amplifier to be increased. In another scenario, a signal-to-noise ratio (SNR) of the signal may be below a selected threshold and the amplitude of the signal may be above a selected threshold. In response, a gain parameter of the amplifier may be reduced to lower the amplitude and increase the SNR. In another example scenario, multiple parameters may be adjusted to increase a measured metric at the signal processing circuitry (e.g., gain, impedance, photodiode bias voltages, and/or other parameters). The adjustment logic 200 may also access status outputs from the adjustable receiver (212), such as peak indicators or other status outputs.
Further, the adjustment logic 200 may select management commands for the adjustable receiver (214). For example, the adjustment logic may issue a shutdown or startup command to the adjustable receiver. The adjustment logic 200 may select adjustments for the adjustable receiver based on the criteria (215). Once the parameter adjustments, status output, or management commands are selected, the adjustment logic 200 may determine the address for the parameter to be adjusted and/or read (216). For example, a given command or adjustment may be executed by changing or reading one or more values within an addressable memory register. The adjustment logic 200 may determine which addresses are associated with the parameters that will be changed or read to execute the commands or adjustments. The adjustment logic 200 may forward the commands or adjustments to the determined addresses (218).
In various implementations, addressing circuitry including addressable memory registers may implement the addressing system in the adjustable receiver. In some cases, the addressing system may operate at a lower frequency than that of the data channels of the receiver. For instance, the adjustable receiver may receive signals of up to 40 Gbps or more. However, the addressing circuitry implementing the addressing system of the adjustable receiver may accept addressing signals on a carrier signal. For example, a carrier signal at 400 KHz or 25 MHz may be used. However, carrier signals at other frequencies may be used. The bit-rate (and associated carrier) of the receiver and carrier frequency of the addressing signals may vary greatly. For example, the receiver carrier may be an optical or near infrared carrier, while the addressing carrier to the addressing circuitry may be a relatively low-speed radio frequency (RF) carrier. However, in a given system the addressing carrier need not necessarily be capable of supporting bit-rates of that of the data channel of the adjustable receiver system. Rather, the addressing carrier may be selected such that widely available RF electronics may be used.
The addressing circuitry 315 may be used to control multi-value parameters such as amplifier gain levels. Additionally or alternatively, the addressing circuitry may be used to control binary values such as device power-on states, and/or activation states. For example, a device may include a binary state for a monitor photodiode activation or deactivation. DACs and register writes may be used to control either multi-value or binary parameters. In some cases, binary controls may be implemented though the addressing circuitry 315 directly via switching instead of DAC-based implementations.
In some cases, a parameter (e.g., binary or multi-value) may control a block such as a programmable sine wave generator instead of a DAC that is accessible by memory register. The sine wave generator may indicate the parameter value through generation of a particular sine wave values associated with particular parameter values. For example, the amplitude and frequency of the sine wave may be controlled by these parameter values. In some cases, the sine wave generator may implement a DAC to accomplish sine wave generation. However, the use of a DAC is not necessarily required.
The signal processing circuitry 399 may control other devices via the communications bus 310, and other devices may access the addressing circuitry 315 via the communications bus. For example, a remote monitoring terminal may access sensor 301 values via the communications bus 310 to allow for remote management of the adjustable receiver. The communications bus 310 may connect to a modem or network interface device for wide area network or local area network connectivity to facilitate remote or centralized management. For example, signal processing circuitry located on a central server may control multiple optical receiver devices, which may be spread over various physical locations or concentrated within a system housing. Additionally or alternatively, multiple control units, such as signal processing circuitry, remote terminals, and/or other control units, may control the adjustable receiver concurrently. For example, signal processing circuitry may control the adjustable receiver via an automated loop, while an operator may manually adjust parameters through a human interface.
In some implementations, external pins 314 may be reserved for power supply inputs and reference grounds. However, the usage these inputs may still be controlled within the addressing circuitry 315. In other cases, these inputs may be controlled outside the addressing circuitry 315. In various cases, power supply inputs may be implemented through addressing circuitry 315 and may not necessarily use reserved external pins. For example, the addressing circuitry may receive power though the communication bus pins and provide power signals through DACs 306. The addressing circuitry 315 may be coupled to the communications bus 310 via pins 316. In various implementations, the communications bus 310 may include an inter-integrated circuit (I2C) bus, a management data input/output (MDIO), a serial peripheral interface bus (SPI), a proprietary bus design, and/or other bus type.
Table 1 shows the pin usage of the type 1 form factor receiver.
Table 2 shows the pin usage of the type 2 form factor receiver.
In various implementations, the TIA power supply, ground, and photodiode bias pins may be reserved and made available to board/circuit designers. However, other pins (e.g., shutdown, manual/automatic gain selection, output amplitude and gain adjust, peak indicator) may be made addressable through the addressing circuitry. The voltage for controlling the addressable parameters can be controlled using DACs whose values are settable via register writes of the memory register in the addressing circuitry. Addressable outputs, (e.g., a peak indicator, or other outputs) may be implemented using ADCs whose values are accessible through register reads of the memory registers of the addressing circuitry. Therefore, the function of multiple external pins used in the above form factors may be performed by the addressing circuitry the DACs and ADCs associated with the addressable values in the memory register.
The 40 pins of the type 1 form factor may be implemented via 18 pins while reserving ground and power supply pins (4 TIA power supply pins, 4 ground pins, 8 photodiode bias pins, and 2 communication pins). Alternatively, combined pins may be used for the power supplies, grounds, and/or photodiode biases. In the combined reserved pin layout, 3 pins in addition to the bus pins may be used. In some cases (e.g., 12C, MDIO) two bus pins may be used. Other bus types may use other numbers of pins, for example SPI buses may use 4 pins.
The 34 pins of the type 2 form factor may be implemented using 18 pins with separate power, ground, and bias pins. The type 2 form factor may be implemented using 5 pins when combined power, ground, and bias pin layouts are used.
The pin combinations discussed here are example layouts and other pin configurations may be used. For example, one or more values controlled by the addressing circuitry may also have associated reserved pins for control of the parameter on the device chassis. Thus, the values may be controlled via pin input or parameter addressing control. A setting within the memory register of the addressing circuitry may indicate whether an addressable value or the pin input will be used for a given parameter. In other cases, addressing circuitry control may be applied to selected parameters. For example, in a given system, control via the addressing circuitry may be applied to a parameter such as gain adjustment but not to a parameter such as output amplitude adjustment. Thus, the parameters that are controlled via addressing circuitry need not necessarily include all parameters that theoretically could be controlled via the addressing circuitry.
In some cases, feedback control via DSP may replace manual correction of the adjustable receiver parameters. For example, an automatic gain control (AGC) sweep executed by a user through a user interface may be automated through the feedback control. For example, a DSP algorithm may directly manipulate the addressable parameters via the communication buses to achieve selected targets for performance. Alternatively or additionally, peak searching algorithms may be used to find performance extrema (or local extrema) such as highest signal levels, lowest error rates, and/or extrema for other metrics. Selected settings can be stored and loaded after power up, reset, periodically, aperiodically, and/or at triggering events. Receiver characteristics may change with the age of the receiver. The DSP feedback controls may adjust the parameters of the adjustable receiver to mitigate effects of aging. Additionally or alternatively, continuously adaptive parameter adjustment with running traffic is possible using feedback control. Thus, the system may have tuned performance in real-time or near real-time.
The methods, devices, processing, and logic described above may be implemented in many different ways and in many different combinations of hardware and software. For example, all or parts of the implementations may be circuitry that includes an instruction processor, such as a Central Processing Unit (CPU), microcontroller, or a microprocessor; an Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or Field Programmable Gate Array (FPGA); or circuitry that includes discrete logic or other circuit components, including analog circuit components, digital circuit components or both; or any combination thereof. The circuitry may include discrete interconnected hardware components and/or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a Multiple Chip Module (MCM) of multiple integrated circuit dies in a common package, as examples.
The circuitry may further include or access instructions for execution by the circuitry. The instructions may be stored in a tangible storage medium that is other than a transitory signal, such as a flash memory, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM); or on a magnetic or optical disc, such as a Compact Disc Read Only Memory (CDROM), Hard Disk Drive (HDD), or other magnetic or optical disk; or in or on another machine-readable medium. A product, such as a computer program product, may include a storage medium and instructions stored in or on the medium, and the instructions when executed by the circuitry in a device may cause the device to implement any of the processing described above or illustrated in the drawings.
The implementations may be distributed as circuitry among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many different ways, including as data structures such as linked lists, hash tables, arrays, records, objects, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library, such as a shared library (e.g., a Dynamic Link Library (DLL)). The DLL, for example, may store instructions that perform any of the processing described above or illustrated in the drawings, when executed by the circuitry.
Various implementations have been specifically described. However, many other implementations are also possible.
This application claims priority to provisional application Ser. No. 62/096,325, filed Dec. 23, 2014, which is entirely incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62096325 | Dec 2014 | US |
