Claims
- 1. An integrated circuit device, comprising:
a first diffusion region; a second diffusion region; an isolation region formed between the first diffusion region and the second diffusion region; and a first region beneath the isolation region, the first region being selectively implanted with a channel stop implant to selectively control a threshold voltage at which conduction occurs from the first diffusion region to the second diffusion region.
- 2. The integrated circuit device of claim 1, wherein the magnitude of the threshold voltage is higher when the first region is implanted with a channel stop implant, than when the first region is not implanted with a channel stop implant.
- 3. The integrated circuit device of claim 1, wherein the first region is implanted with the channel stop implant except along a path connecting the first diffusion region to the second diffusion region.
- 4. The integrated circuit device of claim 3, wherein the magnitude of the threshold voltage at which conduction occurs from the first diffusion region to the second diffusion region is lower along the path, than it is elsewhere in the first region.
- 5. The integrated circuit device of claim 1, further comprising a first active device, the first active device comprising:
a drain region; a gate electrode; and a source region formed by the first diffusion region.
- 6. The integrated circuit device of claim 5, further comprising a second active device, the second active device comprising:
a drain region; a gate electrode; and a source region formed by the first diffusion region.
- 7. The integrated circuit device of claim 6, wherein the first active device and the second active device are of similar device type.
- 8. The integrated circuit device of claim 1, further comprising a gate electrode formed from a conductive region above the isolation region.
- 9. The integrated circuit device of claim 8, wherein the conductive region is polysilicon.
- 10. The integrated circuit device of claim 1, wherein the isolation region is a relatively thick oxide.
- 11. The integrated circuit device of claim 1, further comprising a doped well region, the first region residing in the doped well region to adjust the threshold voltage at which conduction occurs.
- 12. The integrated circuit device of claim 1, wherein the threshold voltage ranges from 2 volts to 20 volts.
- 13. The integrated circuit device of claim 1, wherein the threshold voltage is greater than any voltage supply on the integrated circuit when the first region is implanted with the channel stop implant.
- 14. The integrated circuit device of claim 1, wherein the threshold voltage is below 20 volts when the first region is not implanted with the channel stop implant.
- 15. The integrated circuit device of claim 1, wherein the threshold voltage is at or below the high voltage used to configure memory cells on the integrated circuit.
- 16. The integrated circuit-device of claim 15, wherein the threshold voltage ranges between 6 volts and 16 volts.
- 17. The integrated circuit device of claim 1, further comprising a third diffusion region, wherein the isolation region separates the first, second, and third diffusion regions, a second region beneath the isolation oxide region being selectively implanted with a channel stop implant leaving a path with no channel stop implant connecting the first, second, and third devices.
- 18. The integrated circuit device of claim 1, wherein the width of the path is of similar width of the first diffusion region.
- 19. The integrated circuit device of claim 6, wherein the first active device and the second active device are similarly oriented such that lengths of the first active device are parallel with lengths of the second active device.
- 20. An integrated circuit device, comprising:
a first diffusion region; a second diffusion region; an isolation region formed between the first diffusion region and the second diffusion region; and a first region beneath the isolation oxide region, the first region being implanted with a channel stop implant of selected lengths to selectively control a threshold voltage at which conduction occurs from the first diffusion region to the second diffusion region.
- 21. The integrated circuit device of claim 20, further comprising a doped well surrounding the first region.
- 22. The integrated circuit device of claim 21, wherein the doped well is a p-well.
- 23. The integrated circuit device of claim 22, wherein the doped well is an n-well.
- 24. A method for forming a semiconductor device comprising the steps of:
providing a first diffusion region; providing a second diffusion region; providing an isolation region between the first and second diffusion regions; and selectively implanting a channel stop implant beneath the isolation region to control the voltage threshold at which conduction occurs from the first diffusion region to the second diffusion region.
- 25. The method of claim 24, wherein the length of the channel stop implant is chosen to control the voltage threshold of the isolation region transistor.
- 26. The method of claim 24, further comprising selectively doping a well beneath the isolation region transistor to varying the voltage threshold for the isolation region transistor.
- 27. A method of forming a semiconductor device, comprising the steps of:
growing a pad oxide layer on a substrate; growing a silicon nitride layer on the pad oxide; etching isolation regions from the silicon nitride layer and the pad oxide layer; depositing a spacer oxide; etching an opening in the spacer oxide in selected ones of the isolation regions; implanting a channel stop implant in the openings; removing the spacer oxide; growing a field oxide in the isolation regions; removing the silicon nitride layer; depositing a polysilicon layer; etching the polysilicon layer; and implanting diffusion regions.
- 28. A method of forming a semiconductor device, comprising the steps of:
growing a pad oxide layer on a substrate; growing a silicon nitride layer on the pad oxide; etching isolation regions from the silicon nitride layer and the pad oxide layer; depositing a spacer oxide; etching the spacer oxide to form openings in the isolation regions, wherein the openings are larger in a first set of the isolation regions than in a second set of isolation regions; implanting a channel stop implant in the openings; removing the spacer oxide; growing a field oxide in the isolation regions; removing the silicon nitride layer; depositing a polysilicon layer; etching the polysilicon layer; and implanting diffusion regions.
Parent Case Info
[0001] This application claims the benefit of Provisional Application Ser. No. 60/044,243, filed Apr. 23, 1997, incorporated herein by reference for all purposes.
Provisional Applications (1)
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Number |
Date |
Country |
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60044243 |
Apr 1997 |
US |