Patent Application
20230215885
The present document relates to complementary metal-oxide semiconductor (CMOS) image sensors. More particularly, embodiments relate to adjustable well capacity pixel designs for use with CMOS image sensor (CIS) pixels.
Many modern electronics applications include integrated digital cameras and/or other imaging systems, which are based on complementary metal-oxide semiconductor (CMOS) image sensor (CIS) technologies. A CIS can typically include an array of pixels, each including a single photo-sensor (e.g., photodiode), or a grouping of multiple photo-sensors. Each imaging pixel can include a photosensing element that responds to light to generate photocharge, and in-pixel circuitry for processing the generated photocharge to produce an electrical pixel output signal and for controlling operations of each imaging pixel. The in-pixel circuitry includes transistors for performing sensing and control functions.
Performance of an imaging sensor pixel relates to how well the pixel can convert photons into electrical charges. Such performance can depend on a number of physical and electrical characteristics of the pixel, such as well capacity, dynamic range, and conversion gain. Well capacity relates to the amount of charge that can be held by the imaging pixel during integration (i.e., during exposure to light, prior to readout). It can be desirable to have a large dynamic range, which indicates that the pixel performs well over a large range of lighting conditions, such as from very low-light conditions up to high-light conditions (i.e., where full well capacity, or FWC, may be reached). It can also be desirable to have higher conversion gain, which indicates a larger increase in output signal voltage with any increase in accumulated charge. Typically, the output signal level corresponds to the ratio between the accumulated charge in the well and the well capacitance. For example, a smaller well can tend to have less capacity to accumulate charge and correspondingly smaller well capacitance, which can tend to result in a larger change in output signal level for any change in charge accumulation in the well.
Doping profiles and/or other parameters can be adjusted and controlled during manufacturing of pixels to form photodiodes with a desired well size (e.g., a particular pin voltage potential). A larger well size can theoretically support a higher FWC, but it can also lead to spill-back lag after charge transfer. For example, if the highest fully-depleted potential of the photodiode is too high, residual accumulated charge may remain in the well after transfer, thereby manifesting as a lag. As such, conventional photodiodes tend to be designed with a lower fully-depleted potential and a smaller corresponding FWC to avoid spill-back lag and/or other concerns.
Embodiments disclosed herein include, among others, an imaging pixel design with a unique photo-sensor block structure that provides for dynamic control of well capacity in the photodiode region, referred to herein as a well capacity adjustment (WCA) gate photo-sensor block. The photodiode region includes a doped well in which photocharge is accumulated responsive to exposure to incident illumination. The capacity of the well corresponds to a well potential. WCA structures (e.g., deep trench regions) form walls at least partially surrounding and capacitively coupling with the doped well, such that biasing of the WCA structures changes the well potential and the corresponding well capacity. As such, the WCA structures can be biased during integration to increase the well potential to a high level for large well capacity, and the WCA structures can be differently biased during photocharge transfer to decrease the well potential to a sufficiently low level that avoids lag and/or other conventional concerns.
According to a first set of embodiments, a method is provided for selective photodiode well capacity adjustment in an imaging sensor pixel. The method includes first configuring the WCA gate photo-sensor block to operate in an integration mode for an integration time window by: setting a transfer gate of a well-capacity-adjustment (WCA) gate photo-sensor block to form a potential barrier between a photodiode region of the WCA gate photo-sensor block and a floating diffusion (FD) region of the WCA gate photo-sensor block, the photodiode region having a doped well implanted in a semiconductor substrate to have a well capacity defined at least by a well potential; setting a WCA gate of the WCA gate photo-sensor block to a first biasing, the WCA gate integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well, such that the first biasing pushes the well potential to a first well potential that corresponds to a full well capacity; and directing exposing the photodiode region to incident illumination to cause accumulation of photocharge in the doped well during the integration time widow. The method further includes second configuring the WCA gate photo-sensor block to operate in a transfer mode for a transfer time window subsequent to the integration time window by: setting the transfer gate to form a current channel between the doped well and the FD region; and setting the WCA gate to a second biasing to pull the well potential to a second well potential that corresponds to a reduced well capacity, the second well potential being less than a channel potential of the current channel, the channel potential being less than a FD potential of the FD region. In some such embodiments, the second configuring causes the photocharge accumulated in the doped well during the integration time window to transfer to the FD region via the current channel as transferred photocharge, and the method further includes third configuring the WCA gate photo-sensor block to operate in a spill-back suppression mode for a spill-back suppression time window subsequent to the transfer time window by re-setting the transfer gate to form the potential barrier between the doped well and the FD region while continuing the setting of the WCA gate to the second biasing. In some such methods, the method further includes fourth configuring the WCA gate photo-sensor block to operate in a readout mode for a readout time window subsequent to the spill-back suppression time window by directing readout of the transferred photocharge from the FD region by readout circuitry coupled with the FD region with the transfer gate set to form the potential barrier.
According to another set of embodiments, an imaging sensor pixel is provided. The pixel includes: a well-capacity-adjustment (WCA) gate photo-sensor block configured selectively to operate in at least an integration mode and a transfer mode, the WCA gate photo-sensor block comprising: a photodiode region having a doped well implanted into a semiconductor substrate to accumulate photocharge responsive to exposure of the WCA gate photo-sensor block to incident illumination, the doped well having a well capacity defined at least by a well potential; a WCA gate integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well, such that the well potential is based at least on biasing of the WCA gate; a floating diffusion (FD) region implanted into the semiconductor substrate to have a FD potential; and a transfer gate to selectively form a current channel between the doped well and the floating diffusion region, the current channel having a channel potential less than the FD potential, wherein, in the integration mode, the WCA gate is first-biased to set the well potential to a first well potential corresponding to a full well capacity, and wherein, in the transfer mode, the WCA gate is second-biased to set the well potential to a second well potential that is less than the first well potential, is less than the channel potential, and corresponds to a reduced well capacity.
In another set of embodiments, a complementary metal-oxide semiconductor (CMOS) imaging sensor (CIS) is provided. The CIS includes: an array of imaging pixels, each imaging pixel comprising a well-capacity-adjustment (WCA) gate photo-sensor block, each WCA gate photo-sensor block including: a photodiode region having a doped well implanted into a semiconductor substrate to accumulate photocharge responsive to exposure of the WCA gate photo-sensor block to incident illumination, the doped well having a well capacity defined at least by a well potential; a WCA gate integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well, such that the well potential is based at least on biasing of the WCA gate; a floating diffusion (FD) region implanted into the semiconductor substrate to have a FD potential; and a transfer gate to selectively form a current channel between the doped well and the floating diffusion region, the current channel having a channel potential less than the FD potential. The CIS also includes a controller coupled with the array of imaging pixels to selectively configure each imaging pixel to operate in at least an integration mode and a transfer mode, such that: the controller is to configure each imaging pixel to operate in the integration mode by setting the transfer gate of the imaging pixel to form a potential barrier between the doped well of the imaging pixel and the FD region of the imaging pixel, setting the WCA gate of the imaging pixel to a first biasing to push the well potential of the imaging pixel to a first well potential that corresponds to a full well capacity, and directing exposing the imaging pixel to incident illumination to cause accumulation of photocharge in the doped well of the imaging pixel during an integration time widow; and the controller is to configure each imaging pixel to operate in the transfer mode by setting the transfer gate of the imaging pixel to form a current channel between the doped well of the imaging pixel and the FD region of the imaging pixel, and setting the WCA gate of the imaging pixel to a second biasing to pull the well potential of the imaging pixel to a second well potential that corresponds to a reduced well capacity, the second well potential being less than a channel potential of the current channel, the channel potential being less than a FD potential of the FD region.
The drawings, the description and the claims below provide a more detailed description of the above and other aspects of transistors with a hybrid structure, their implementations and features of the disclosed technology.
The accompanying drawings, referred to herein and constituting a part hereof, illustrate embodiments of the disclosure. The drawings together with the description serve to explain the principles of the invention.
In the appended figures, similar components and/or features can have the same reference label. Further, various components of the same type can be distinguished by following the reference label by a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
In the following description, numerous specific details are provided for a thorough understanding of the present invention. However, it should be appreciated by those of skill in the art that the present invention may be realized without one or more of these details. In other examples, features and techniques known in the art will not be described for purposes of brevity.
Many modern electronics applications include integrated digital cameras and/or other imaging systems, which are based on complementary metal-oxide semiconductor (CMOS) image sensor (CIS) technologies. A CIS can typically include an array of pixels, each including a single photo-sensor (e.g., photodiode), or a grouping of multiple photo-sensors. Each imaging pixel can include a photosensing element that responds to light to generate photocharge, and in-pixel circuitry for processing the generated photocharge to produce an electrical pixel output signal and for controlling operations of each imaging pixel.
The pixel 105 also includes additional components (in-pixel circuitry) to facilitate usage of the photo-sensor block 110 for optical sensing. As illustrated, embodiments can include a dual conversion gain (DCG) block 120, a reset block 130, a source-follower block 140, and a select block 150. Each can be implemented using at least one corresponding transistor. The reset block 130 can selectively reset the pixel 105 components. The source-follower block 140 can support conversion of outputs from the photo-sensor block 110 into an electrical signal indicative of optical information detected by the photo-sensor block 110. The select block 150 can support selection of the pixel 105 signals from among the array of pixels 105, for example responsive to a control signal received via a bus 160. For example, the bus 160 may be a column select bus, or the like.
Certain features described herein involve setting components of the pixel 105 array for multiple modes of operation, such as including some or all of an integration mode, a transfer mode, a spill-back suppression mode, and a readout mode. Further, certain features involve sequenced signaling (e.g., for biasing control) to support such modes. To direct such multi-mode operation, including controlling signaling to set components of the pixel 105 array, embodiments include control circuitry, illustrated as a controller 170. The controller can include a central processing unit CPU, an application-specific integrated circuit (ASIC), an application-specific instruction-set processor (ASIP), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC) processor, a complex instruction set computer (CISC) processor, a microprocessor, or the like, or any combination thereof. In some embodiments, the controller 170 is implemented on-chip with image sensor. For example, the array of pixels 105 and the controller 170 are implemented on a same integrated circuit.
For added context,
As illustrated, a transfer gate 215 can be activated by a Tx signal and can be isolated from the substrate 207 by an oxide layer 220. The substrate 207 can have a first doping type (e.g., P-type). The PPD 210 can be formed by implanting at least a collection region 230 of a second doping type (e.g., N-type) into the substrate 207 on one side of the transfer gate 215, and implanting a floating diffusion region 235 of the second doping type (e.g., N-type) into the substrate 207 on the other side of the transfer gate 215. The collection region 230 is generally referred to herein as the “well” of the PPD 210, and the maximum amount of photocharge that can be accumulated in the collection region 230 is the FWC of the PPD 210. Isolation regions 240 (e.g., shallow-trench isolation, STI) can be formed to electrically isolate structures of the pixel 200 from those of adjacent structures and/or pixels.
As photons reach the substrate 207, they can be converted into photocarriers (i.e., electrons and holes), one of which being attracted to and collected in the collection region 230. The accumulation of photocarriers in the collection region 230 can be considered generally as an accumulation of photocharge (also referred to herein generally as the accumulation of charge). For example, longer and/or brighter exposure can result in a greater accumulation of charge in the collection region 230. Activating the Tx signal can form a depletion region below the transfer gate 215, which effectively becomes a current channel between the two second-doping-type (e.g., N-type) regions: the collection region 230 and the floating diffusion region 235. As such, activation of the transfer gate 215 causes accumulated charge in the collection region 230 to transfer across the current channel to the floating diffusion region 235 (e.g., in the direction of arrow 247).
As illustrated, the in-pixel circuitry generally interfaces with the PPD 210 via the floating diffusion region 235. For example, components of the in-pixel circuitry are used to read out the accumulated charge after it is transferred to the floating diffusion region 235. Prior to transferring the accumulated charge from the collection region 230 to the floating diffusion region 235, the reset block 130 can be used to effectively flush accumulated charge from the floating diffusion region 235 to reset the pixel 200. Transferring the accumulated charge from the collection region 230 to the floating diffusion region 235 can effectively generate a gate voltage (corresponding to the amount of accumulated charge transferred to the floating diffusion region 235) at the gate of the source follower block 140. As illustrated, the select block 150 is coupled between a source terminal of the source follower block 140 and an output voltage terminal (Vout), and a constant current source is coupled between Vout and ground. As such, when the select block 150 is activated (e.g., as part of a row select operation), an output voltage is generated at Vout based on the gate voltage at the source follower block 140 (i.e., and thus based on the accumulated charge transferred to the floating diffusion region 235).
As illustrated, the reset block 130 can be implemented as a conventional MOSFET with an n-type source region (i.e., the floating diffusion region 235) and an n-type drain region 255 implanted in the semiconductor substrate 207 (e.g., p-doped silicon). Both the transfer gate 215 and the reset gate 250 can be implemented as polygate structures patterned on the substrate 207 on top of the gate oxide layer 220 (i.e., a metal-oxide layer). Conventionally, the gate oxide layer 220 is formed using a metal oxide, such as silicon dioxide. The gate oxide layer 220 forms a dielectric insulator layer between the polygate structures and formed current channels. As such, the gate oxide layer 220 electrically isolates both polygate structures from, and facilitates formations of respective channel regions below, the polygate structures. In particular, activating the transfer gate 215 forms a channel region between the collection region 230 and the floating diffusion region 235, and activating the reset gate 250 forms a channel region between the floating diffusion region 235 and the drain region 255. For example, applying a positive gate voltage to either polygate structure can attract negative charges to the channel region below the polygate structure in a p-doped substrate implementation, thereby forming an n-type current channel between adjacent n-type regions. Alternatively, applying a negative gate voltage to either polygate structure can attract positive charges to the channel region below the polygate structure in an n-doped substrate implementation, thereby forming a p-type current channel between adjacent p-type regions.
Performance of imaging pixels, such as pixel 200, can relate to how well the pixel can convert photons into electrical charges. Such performance can depend on a number of physical and electrical characteristics of the pixel, such as well capacity. As described above, the full well capacity (FWC) corresponds to the amount of photocharge that can be accumulated in the collection region 230 during integration (i.e., during exposure to light, prior to readout). It can be desirable in many applications to have a high FWC, such as to support higher dynamic range and improved signal-to-noise ratio. For example, higher dynamic range indicates that a pixel can perform well over a large range of lighting conditions, such as from very low-light conditions up to high-light conditions (i.e., where full well capacity, or FWC, may be reached).
However, achieving high FWC can be problematic. As a three-dimensional structure, the size of the well can be increased either by increasing its planar dimensions (i.e., its length and/or width with respect to layout view dimensions of the pixel), or by increasing its effective depth. The planar dimensions of the collection region 230 are typically limited by the overall pixel dimensions, which are shared by the photodiode(s) and any in-pixel circuitry. Such pixel layout dimensions have tended to decrease over time (e.g., with increasing demands for smaller image sensors and higher resolutions), which has tended to decrease the maximum layout area available for each photodiode collection region 230. The effective maximum depth of the collection region 230 can correspond to doping parameters and to a highest fully-depleted potential of the photodiode, sometimes referred to as the pinning voltage for a pinned photodiode, such as PPD 210. Doping profiles and/or other parameters can be adjusted and controlled during manufacturing of the photodiode to effectively set the pinning voltage potential to a desired level. A larger pinning voltage potential can theoretically support a deeper well in the same layout dimensions and a higher corresponding FWC. However, in conventional designs, increasing the maximum pinning voltage too much can lead to performance degradation, such as lag due to residual charge left in the collection region 230 after charge transfer.
For example,
Turning first to
As can be seen in
Turning first to
It may seem that such a concern can be addressed by increasing the channel potential 320 during transfer, but such an approach tends to result in a similar effect due to spill back. For example,
Turning first to
Embodiments described herein introduce an additional gate structure, referred to as a well capacity adjustment gate (WCAG) that at least partially surrounds the photodiode well. Controlling the WCAG can effectively provide control over the pinning voltage of the photodiode, so that the pinning voltage can be different in different modes of operation. For example, in an integration mode, the WCAG is controlled to increase the pinning voltage potential, thereby increasing FWC. In a relay transfer mode, the WCAG is controlled to decrease the pinning voltage potential, thereby avoiding lag.
The transfer gate 215 can be activated by a Tx signal and can be isolated from the substrate 207 by an oxide layer 220. The substrate 207 can have a first doping type (e.g., P-type). The photodiode region 610 can be formed by implanting at least a collection region 630 of a second doping type (e.g., N-type) into the substrate 207 on one side of the transfer gate 215. The floating diffusion region 235 can be implanted by doping a region using the second doping type (e.g., N-type) into the substrate 207 on the other side of the transfer gate 215. The collection region 630 is generally referred to herein as the “well” of the photodiode, and the maximum amount of photocharge that can be accumulated in the collection region 230 is the FWC. Isolation regions 240 (e.g., shallow-trench isolation, STI) can be formed to electrically isolate structures of the WCAG photo-sensor block 600 from those of adjacent structures, pixels, etc.
The illustrated wells and other structures of the WCAG photo-sensor block 600 are intended to provide clarity to the description, but are not intended to be accurate physical representations. For example, shapes and boundaries of structures implanted into the substrate are generally formed by etching, diffusion, and/or other processes, which may result in organically shaped regions with only statistically defined boundaries. Similarly, the actual amount of doping in different regions of the substrate may not match the effective structures that result from such doping. For example, the entire portion of the substrate 207 within the dashed photodiode region 610 may be doped with second-doping-type material, even though the effective collection region 630 only corresponds to a portion of the photodiode region 610.
As described with reference to
As illustrated, the WCAG 615 can include one or more deep trench structures. Some embodiments implement each WCAG 615 structure as a capacitive deep trench isolation region, such that each WCAG 615 structure is capacitively coupled with the photodiode region 610 (i.e., with the collection region 630). In some implementations, the WCAG 615 completely surrounds the photodiode region 610. For example, the illustrated WCAG 615 structures can represent two walls of a contiguous three-dimensional box around the photodiode region 610. In other implementations, the WCAG 615 partially surrounds the photodiode region 610. For example, the illustrated WCAG 615 structures can represent two of two or more walls on two or more sides of the photodiode region 610.
The WCAG 615 is coupled with a well capacity adjustment (WCA) terminal 620. Biasing of the WCAG 615 is controllable based on the voltage applied at the WCA terminal 620. For example, applying a positive voltage to the WCA terminal 620 can positively bias the WCAG 615 structures, effectively pulling down the pinning voltage potential and increasing the well size associated with the collection region 630 (represented as collection region 630a). Applying a negative voltage to the WCA terminal 620 can negatively bias the WCAG 615 structures, effectively pushing up the pinning voltage potential and decreasing the well size associated with the collection region 630 (represented as collection region 630b). As such, control of the WCAG 615 (via the WCA terminal 620) can effectively provide control over the FWC of the photodiode, such that the WCAG photo-sensor block 600 can operate in different modes with different associated FWCs.
As described with reference to
Some features of such multi-mode operation are described with reference to
The timing diagram 700 shows an illustrative signal applied at the gate of the select block (SEL 150), an illustrative signal applied at the gate of the reset block (RST 250), an illustrative signal applied at the WCA terminal (WCA 620), and an illustrative signal applied at the transfer gate (TX 215). At the start of each cycle of operation, the SEL 150 signal is actuated to select the pixel having the WCAG photo-sensor block 600 of interest (e.g., as part of a row select operation, or the like). For example, the pixel is selected from among a large array of pixels, each with respective instances of the WCAG photo-sensor block 600. Next, the RST 250 signal is actuated for a short time to reset the pixel, such as flushing any accumulated charge left in the floating diffusion region 235 from a preceding cycle.
The WCAG photo-sensor block 600 is now ready for photocharge integration and transfer. During an integration time window, the WCAG photo-sensor block 600 is exposed to illumination, and photocharge accumulates in the collection region 630. Time T1 is a representative time within the integration time window. As illustrated, WCA 620 is HIGH and TX 215 is LOW during this time.
As illustrated in
As illustrated in
Finally, as illustrated in
For added clarity,
Plots 910a and 910b represent operation of a conventional type of photo-sensor block during integration and transfer, respectively. In such a conventional implementation, TX 215 is OFF during integration, such that plot 910a shows a near-zero electrostatic potential (i.e., a potential barrier) in the transfer gate 215 region, and some well potential (e.g., around 1.75 volts) in the photodiode region 210. During transfer, TX 215 is ON, such that plot 910b shows a high electrostatic potential (e.g., around 3 volts, corresponding to a channel potential of a formed channel region) in the transfer gate 215 region, and approximately no change in the well potential (e.g., still around 1.75 volts) in the photodiode region 210. As illustrated, there can be some slight movement of the well potential close to the transfer gate 215 region due to fringe effects, or the like, but the well potential remains appreciably less than that of the channel potential. As noted above, such conventional designs purposefully design the well potential to stay appreciably less than that of the channel potential, such as to avoid lag concerns.
Plots 920a and 920b represent operation of a WCAG photo-sensor block 600 during integration and transfer, respectively. During integration, plot 910a shows that the electrostatic potential in the transfer gate 215 region can be substantially the same as for a conventional implementation, such that a potential barrier is formed. However, the photodiode region 210 is shown to be designed with a much greater potential of around 2.5 volts (i.e., corresponding to an appreciably larger FWC). During transfer, similar to the conventional case, plot 920b shows a high electrostatic potential corresponding to a channel potential of a formed channel region in the transfer gate 215 region. Unlike in the conventional case, plot 920b shows a large change in well potential (e.g., from around 2.5 volts to around 1.5 volts) in the photodiode region 210 during transfer facilitated by the novel configuration of the WCAG. For example, during integration, the WCAG can be biased so that the well potential is close to, or even below that of the channel potential (i.e., where the channel potential will be when TX 215 is ON during the transfer time window); and during transfer, the WCAG can be biased so that the well potential is decreased to a level far below that of the channel potential while the channel is ON.
Returning to
As described above, the multi-mode operation can involve additional modes for some embodiments. Some embodiments of the WCAG photo-sensor block 600 are configured selectively to operate further in a spill-back suppression mode. For example, in the integration mode, the transfer gate 215 is set to be OFF to form the potential barrier between the doped well and the floating diffusion region 235 with the WCAG 615 set to be first-biased during accumulation of photocharge in the photodiode region 610. In the transfer mode, the transfer gate 215 is set to be ON to form the current channel between the doped well and the floating diffusion region 235 with the WCAG 615 set to be second-biased, such that accumulated photocharge transfers from the doped well to the floating diffusion region 235 via the current channel as transferred photocharge. In the spill-back suppression mode, the transfer gate 215 is set to be OFF to form the potential barrier between the doped well and the floating diffusion region 235 with the WCAG 615 set to be second-biased (i.e., kept in the second-biased state after the transfer time window is complete). Some embodiments are configured selectively to operate further in a readout mode, in which the transfer gate 215 is set to be OFF (e.g., or kept off after the spill-back suppression time window) to form (e.g., maintain) the potential barrier between the doped well and the floating diffusion region 235 during readout of the transferred photocharge from the floating diffusion region. For example, readout circuitry is directed to readout the transferred photocharge from the floating diffusion region 235 during the readout time window. In some such embodiments, the WCAG 615 set to be first-biased during the readout mode.
The WCAG 615 can be designed in different ways to provide features described herein. One or more WCA structures 615 are electrically coupled with a WCA terminal 620 (as illustrated) and form the walls that at least partially surround and capacitively couple with the doped well. The WCA terminal 620 receives a biasing signal to bias the WCA structures 615. In some embodiments, the one or more WCA structures 615 are implemented as a single contiguous deep-trench structure that is integrated with the semiconductor substrate 207 and forms the walls that at least partially surround and capacitively couple with the doped well. In other embodiments, the one or more WCA structures 65 are implemented as multiple deep-trench structures integrated with the semiconductor substrate 207, each forming one or more of the walls that at least partially surround and capacitively couple with the doped well.
For example,
For example,
Such a structure may be used for a pixel array that is configured for rolling shutter readout. For example, all of the pixels 1110 are configured with deep doped wells for accumulation of photocharge during integration. When it is time to transfer and readout pixel 1110ba (e.g., to a readout line, such as line 1120), some or all of WCA structures 615b, 615c, 615ba, and 615bb can be biased together to form walls on some or all sides of the doped well. For example, all the WCA structures 615 for a particular row can be biased together to support row-wise readout. In this way, selectively biasing different sets of WCA structures 615 can provide individualized control over the well potential of particular pixels 1110. For example, because WCA structure 615b is adjacent to both pixel 1110ba and 1110aa, such that biasing WCA structure 615b for readout of pixel 1110ba also incidentally biases one of the WCA structures 615 adjacent to pixel 1110aa. However, biasing only the single adjacent WCA structure 615 can be insufficient to appreciably change the well potential for pixel 1110aa, such that pixel 1110aa can still integrate properly during readout of pixel 1110ba. To reduce biasing effects on adjacent pixels 1110, some embodiments also add biasing to the adjacent transfer gates. For example, while the second row of pixels 1110ba . . . 1110bn is being readout (i.e., and the WCA structures 615 adjacent to the sides of all the pixels 1110 in that row are biased to reduce well potentials), transfer gates for the first row of pixels 1110aa . . . 1110an and the third row of pixels 1110ca . . . 1110cn can be slightly biased (e.g., negatively) to further pull up the potential barrier. In other embodiments a non-contiguous arrangement of WCA structures can be used with a global shutter readout scheme.
For example, at stage 1208, embodiments can set a transfer gate of the WCA gate photo-sensor block (as part of the integration mode of operation) to form a potential barrier between a photodiode region of the WCA gate photo-sensor block and a floating diffusion (FD) region of the WCA gate photo-sensor block. As used herein, the term “potential” refers to electrostatic potential, such that a term like “potential barrier” refers to a region of sufficiently low (e.g., near-zero) electrostatic potential as to ensure that photocharge does not transfer from one region to another. As described above, the photodiode region has a doped well implanted in a semiconductor substrate (e.g., a collection region) that has a well capacity defined at least by a well potential.
At stage 1212, embodiments can set a WCA gate of the WCA gate photo-sensor block (as part of the integration mode of operation) to a first biasing. As described above, the WCA gate is integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well. Due to such capacitive coupling, the first biasing of the WCA gate pushes the well potential of the doped well to a first well potential that corresponds to a full well capacity. As described herein, the well potential in this mode can be higher (i.e., to FWC can be higher) than in conventional approaches. For example, the first well potential can be greater than the channel potential, and/or the first well potential can even be greater than the FD potential. At stage 1216, embodiments can direct exposing the photodiode region (as part of the integration mode of operation) to incident illumination to cause accumulation of photocharge in the doped well during the integration time widow. Such directing can involve permitting an exposure time to elapse, controlling a shutter, etc.
Embodiments of the method 1200 can continue at stage 1220 by configuring the WCA gate photo-sensor block to operate in a transfer mode for a transfer time window subsequent to the integration time window. As illustrated, stage 1220 can involve a number of internal stages, such as stages 1224-1228. At stage 1224, embodiments can set the transfer gate (as part of the transfer mode of operation) to form a current channel between the doped well and the FD region. For example, a TX signal is sent to the transfer gate to turn the gate ON, thereby causing a depletion region to form below the transfer gate between the doped well and the FD region. At stage 1228, embodiments can set the WCA gate (as part of the transfer mode of operation) to a second biasing to pull the well potential to a second well potential that corresponds to a reduced well capacity. The second well potential is less than a channel potential of the current channel, which is less than a FD potential of the FD region, such that a gradient is formed between the doped well and the FD region. In some embodiments, the setting of the transfer gate in stage 1224 is performed prior to the setting of the WCA gate in stage 1228. For example, in cases where the first well potential is greater than the channel potential, performance of stage 1224 prior to performance of stage 1228 can help to avoid residue lag, and/or other concerns.
Some embodiments of the method 1200 include additional stages to provide for additional modes of operation of the WCA gate photo-sensor block. In some embodiments, at stage 1230, the method 1200 can configure the WCA gate photo-sensor block to operate in a spill-back suppression mode for a spill-back suppression time window subsequent to the transfer time window. For example, the configuring in stage 1220 can cause photocharge accumulated in the doped well during the integration time window to transfer to the FD region via the current channel as transferred photocharge. As such, the configuring at stage 1230 can be performed by re-setting the transfer gate to form the potential barrier between the doped well and the FD region (as in stage 1208) while continuing to set the WCA gate to the second biasing.
In some embodiments, at stage 1240, the method 1200 can further configure the WCA gate photo-sensor block to operate in a readout mode for a readout time window subsequent to the spill-back suppression time window. Such configuring can include directing readout of the transferred photocharge from the FD region by readout circuitry coupled with the FD region with the transfer gate set to form the potential barrier. In some implementations, the configuring at stage 1240 also includes re-setting the WCA gate to the first biasing (i.e., to the increased FWC) during the readout time window. As described above, readout during such a readout mode can be performed in different ways for different pixel configurations, such as using a global shutter readout or a rolling shutter readout. The manner of setting the WCA gate in at least stage 1228 can be to support the different types of readout. For example, all WCA gate structures for all pixels may be concurrently biased in global shutter readout implementations, while sets of WCA gate structures adjacent to particular pixels may be biased in a particular sequence to support rolling shutter readout implementations.
As used herein, reference to “first biasing” and “second biasing” intends to convey a first biasing state and a second biasing state, where the second biasing state is sufficiently different from the first biasing state to provide the corresponding features described herein. In some implementations, one of the biasing states corresponds to a logic HIGH (e.g., a digital ‘1’), and the other corresponds to a logic LOW (e.g., a digital ‘0’). In other implementations, one of the biasing states corresponds to positive voltage level, and the other corresponds to a negative voltage level. In other implementations, one of the biasing states corresponds to positive or negative voltage level, and the other corresponds to a zero (or substantially zero) voltage level. For example, the doped well can be doped and implanted in a manner that provides a very deep well without any biasing on the WCA gate structures, such that setting the WCA gate to the first biasing (e.g., as in stage 1212) can involve removing biasing from the WCA gate and setting the WCA gate to the second biasing (e.g., as in stage 1228) can involve actively biasing the WCA gate. Alternatively, the doped well can be doped and implanted in a manner that provides a very deep well only with the help of biasing on the WCA gate structures, such that setting the WCA gate to the first biasing can involve actively biasing the WCA gate and setting the WCA gate to the second biasing can involve removing biasing from the WCA gate.
It will be understood that, when an element or component is referred to herein as “connected to” or “coupled to” another element or component, it can be connected or coupled to the other element or component, or intervening elements or components may also be present. In contrast, when an element or component is referred to as being “directly connected to,” or “directly coupled to” another element or component, there are no intervening elements or components present between them. It will be understood that, although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, these elements, components, regions, should not be limited by these terms. These terms are only used to distinguish one element, component, from another element, component. Thus, a first element, component, discussed below could be termed a second element, component, without departing from the teachings of the present invention. As used herein, the terms “logic low,” “low state,” “low level,” “logic low level,” “low,” or “0” are used interchangeably. The terms “logic high,” “high state,” “high level,” “logic high level,” “high,” or “1” are used interchangeably.
As used herein, the terms “a”, “an” and “the” may include singular and plural references. It will be further understood that the terms “comprising”, “including”, having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components. Furthermore, as used herein, the words “and/or” may refer to and encompass any possible combinations of one or more of the associated listed items.
While the present invention is described herein with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Rather, the purpose of the illustrative embodiments is to make the spirit of the present invention be better understood by those skilled in the art. In order not to obscure the scope of the invention, many details of well-known processes and manufacturing techniques are omitted. Various modifications of the illustrative embodiments, as well as other embodiments, will be apparent to those of skill in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications.
Furthermore, some of the features of the preferred embodiments of the present invention could be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles of the invention, and not in limitation thereof. Those of skill in the art will appreciate variations of the above-described embodiments that fall within the scope of the invention. As a result, the invention is not limited to the specific embodiments and illustrations discussed above, but by the following claims and their equivalents.
