1. Field of the Invention
The present invention relates to an aid design system and method for analog integrated circuits (ICs), and more particularly, to an aid design system and method for selecting peripheral components of analog ICs to perform an entire circuit simulation.
2. Description of the Related Art
Nowadays there are many aid design systems for digital ICs, but a well-defined aid design system for analog ICs which satisfies the user's need is rarely seen. This is because the digital ICs are easy to standardize and only need to consider logic zero and one. Besides, the component connection between digital ICs is easier than that between analog ICs. However, it is difficult to build up standard analog ICs, not only because individual companies manufacture product specifications that are inconsistent with each other, but also for some peripheral components, such as inductors, capacitors and diodes, whose parasitic capacitor needs to be considered when building up the entire circuit performance.
Generally speaking, most design flows of analog ICs need to look up the datasheet of the analog ICs involved. However, those datasheets are recorded in accordance with approximate mathematical model, which is inexact in the first place. Thereafter, users need to look up manuals of peripheral components to choose suitable peripheral components. Because most datasheets neglect the parasitic effect of the peripheral components, the users need to make a test board to physically test the output response and steady state analysis of the entire circuit including the analog ICs and the peripheral components. The above design flow usually involves a try error method to iteratively modify the selected components several times, and thus users would waste a lot of energy and time.
Because the technique of power ICs has been developed for several years, many models in connection with power converters, such as boost and buck, have been published. For example, the team led by Professor Marian K. Kazimierczuk published a lot of transfer functions of boost current mode converters and peak currents of boost inductors in IEEE Journals. Please refer to B. Bryant and M. K. Kazimierczuk, “Open-loop power-stage transfer functions relevant to current-mode control of boost PWM converter operating in CCM,” IEEE Trans. Circuits Syst., Part 1, vol. 52, pp. 2158-2164, October 2005. B. Bryant and M. K. Kazimierczuk,” Modelling the Closed-Current Loop of PWM Boost DC-DC Converters Operating in CCM with Peak Current-Mode Control,” IEEE Trans. Circuits Syst., Part 1, vol. 52, pp. 2404-2412, November 2005. B. Bryant and M. K. Kazimierczuk,” Voltage Loop of Boost PWM DC-DC Converters with Peak Current-Mode Control,” IEEE Trans. Circuits Syst., Part 1, vol. 53, pp. 99-105, January 2006. Because the computing capability of current computers is very strong, the simulation of the power converters using the above mathematical model is more and more accurate. However, if the above model simulation only considers analog ICs themselves and not users' needs, it would be less helpful to save time and energy for designers.
In short, finding a system and method to reduce the complexity of the design flow for analog ICs is an important issue right now.
The aid design system and method for analog ICs of the present invention is to help analog IC designers to automatically list the desired peripheral components. The present invention automatically lists suggested peripheral components from a peripheral component database according to the user's demand and simulation in the analog IC database. Thereafter, an estimated efficiency, output response and steady state analysis are displayed for the user's reference. Therefore, the present invention makes a more convenient design environment for users, and reduces the number of times needed to look up datasheet and try errors, thereby shortening the time to design product applications of analog ICs. The aid design system and method for analog ICs of the present invention can be used in any calculation platform, such as a personal computer, network server, smart phone or PDA.
The aid design system according to an embodiment of the present invention includes an analog IC database, a peripheral component database, an input module, a calculation simulation module, an output module and a selection module. The analog IC database includes a plurality of parameters of analog ICs. The peripheral component database includes parameters of the peripheral components cooperating with the analog ICs. The input module is configured so that a user can input a specification. The calculation simulation module connects to the input module, analog IC database and peripheral component database. The calculation simulation module includes transfer functions and equations of the plurality of analog ICs. The output module is configured to display suggested peripheral components according to the simulation result of the calculation simulation module. The selection module is configured to select peripheral components from the suggested peripheral components, where the selected peripheral component is submitted into the calculation simulation module to proceed with an entire circuit simulation.
The aid design method for analog ICs according to an embodiment of the present invention includes steps (a) to (f). In step (a), a user inputs a specification of a desired analog IC. In step (b), the aid design system calculates and lists all peripheral components satisfying the specification. In step (c), the user chooses peripheral components from the listed peripheral components. In step (d), the aid design system performs an entire circuit simulation including the analog IC and the chosen peripheral component. In step (e), the user determines whether the simulation result is acceptable. In step (f), the user reselects another analog IC or peripheral component and performs another entire circuit simulation if the result is not acceptable.
The invention will be described according to the appended drawings in which:
V
in=1.8V, Vout=5V, Io=250 mA, fsw=500 kHz
where Vin represents input voltage, Vout represents output voltage, Io represents output current and fsw represents switching frequency. The user inputs the specification requested by his or her customer to the aid design system 10 for analog ICs of the present invention, such as the “specification” field on the left side of
For example, according to the specification demand of fsw=500 kHz, AAT1415 will set up its frequency based on COSC=100 pF, ROSC=56 k Vout=5V, and therefore the voltage-dividing resistor is as follows:
The duty cycle and critical inductance value are as follows:
Because the circuit has a higher efficiency in CCM, an inductance value greater than 1.66μ must be chosen. The embodiment chooses a normally used inductor with 3.3μ. The peak current of the inductor is as below:
Therefore, the current limit must pick one greater than 1.17 A.
The embodiment collects a suitable list from the peripheral component database 13. Assume that using Mitsumi C4-K2.5L as the conductor is recommended, which has a current limit with 1.8 A and DCR with 33 mΩ. Assume that using DFLS220L as the diode is recommended, which has a current limit with 2A, VF=0.32 and CT=75 pF. The compensation capacitor Cc is calculated as below:
Where RL represents equivalent loading, rL represents DCR of inductor, rDS represents conductance resistance of inner MOS, RF represents forward equivalent resistance of diode, Rs represents resistance of current sense, and fc represents cross-over frequency. In CCM there is a zero point in the right half plane, whose frequency is
Normally, a crossover frequency fc will be set to lower than 20% from the switching frequency fRHPZ. The embodiment chooses fRHPZ≈115.7 kHz, and further decides fc=20 kHz and Cc≈1.86 nF. In order to satisfy the above requirement, a normally used capacitance Cc=2.2 nF is chosen. The compensation resistor is
where TD % represents the percentage of transient drop. Assume the demand is 5%, and then Rc≈66.86 k is inferred. The embodiment picks a normally used resistance Rc=68 k. Also, a loading pole of a voltage-regulating capacitor is selected to offset the zero point caused by RcCc, where
As such, Cout≈14.95 uF. The embodiment recommends the capacitor of YAIYO YUDEN LMK316BJ226K, which has Cout=22 uF, ESR=10 mΩ and outputs ripple voltage
There are two buttons, “stability analysis” and “transient response” on the top right side of
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by persons skilled in the art without departing from the scope of the following claims.
Number | Date | Country | Kind |
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096107783 | Mar 2007 | TW | national |