Claims
- 1. A method for supporting ASF in an ASD using one or more embedded processors, the method comprising:
providing a packet stream having both ASF and non ASF packets; filtering and separating the ASF packets from the non-ASF packets; accepting the ASF related packets to be processed; examining the ASF related packets using a firmware routines running on the one or more embedded processors; and generating an appropriate response.
- 2. A method as in claim 1 wherein the filtering of ASF packets comprises comparing packets in the packet stream in a programmable pattern detector.
- 3. The method of claim 1 wherein the one or more embedded processors comprise two embedded processors operating in parallel.
- 4. The method of claim 1 wherein the one or more embedded processors are running different aspects of the ASF protocol.
- 5. The method of claim 4 wherein examining the ASF related packets comprises interpreting a RMCP (Remote Management Control Protocol) packet.
- 6. The method of claim 5 wherein examining the ASF related packets comprises interpreting a SMBus message.
- 7. The method of claim 1 wherein examining the ASF related packets comprises interpreting a ASF packet.
- 8. The method of claim 5 wherein generating a response further comprises executing a firmware routine that generates a PET (Platform Event Trap) packet.
- 9. The method of claim 5 wherein generating a response further comprises executing a firmware routine that generates a RMCP response packet.
- 10. The method of claim 5 wherein generating a response further comprises executing a firmware routine that generates a SMbus response.
- 11. A method for processing communications packets in an ASD, the method comprising:
accepting a sequence of packets, the sequence of packets including a plurality of types of packets; detecting ARP (Address Resolution Protocol) packets; removing the ARP packets from the sequence of a plurality of types of packets, without affecting or slowing down the non ASF packets; and notifying at least one processor to process the ARP packets.
- 12. The method of claim 11 wherein detecting ARP packets comprises:
accepting the packets in a rules checker; and comparing the packets to the rules, defining ARP packets, in the rules checker.
- 13. The method of claim 11 wherein removing the ARP packets from the sequence of a plurality of types of packets comprises inserting the ARP packets into a queue for processing by an internal processor.
- 14. The method of claim 11 wherein processing a response to the ARP packets comprises:
generating an ARP response transmit packet; and transmitting the ARP response transmit packet.
- 15. A method for processing communications packets in an ASD, the method comprising:
accepting a sequence of packets, the sequence of packets including a plurality of types of packets; detecting RMCP (Remote Management and Control Protocol) packets; removing the Remote Management and Control Protocol (RMCP) packets from the sequence of a plurality of types of packets, without affecting or slowing down the non RMCP packets; and notifying at least one processor to process the RMCP packets.
- 16. The method of claim 15 wherein detecting RMCP packets comprises:
accepting the packets in a rules checker; and comparing the packets to the rules, defining RMCP packets, in the rules checker.
- 17. The method of claim 15 wherein removing the RMCP packets from the sequence of a plurality of types of packets comprises inserting the RMCP packets into a queue for processing by an internal processor.
- 18. The method of claim 15 wherein processing a response to the RMCP packets comprises:
generating an RMCP response transmit packet; and transmitting the RMCP response transmit packet.
- 19. A method of providing ASF timers the method comprising:
providing a plurality of hardware timers; loading the timers with a count; starting the timers counting; creating an indication of timer expiration on expiration of the count for each timer; and examining the indication of timer expiration of at least one of the timers.
- 20. The method of claim 19 wherein examining the indication of timer expiration of at least one of the timers comprises examining the indication during an idle loop of an embedded processor.
- 21. The method of claim 20 wherein examining the indication of timer expiration comprises examining the indication of status bits in an internal register.
- 22. The method of claim 19 wherein providing a plurality of hardware timers further comprises providing at least one time selected from the group of ASF timers consisting of a watchdog timer, a heartbeat timer, an ASF Sensor Poll Interval timer, a legacy sensor poll timer, a PET Re-transmission timer and a timestamp timer.
- 23. The method as in claim 19 wherein the indication of timer expiration is examined by at least one embedded processor.
- 24. The method of claim 19 wherein the timers are timed from a fixed clock source, which is not slowed when chip timing is slowed.
- 25. The method of claim 19 wherein the timers are timed from a fixed clock source, which does not vary dependant on link speed of the chip, or presence of PCI power.
- 26. The method of claim 19 wherein the timers are timed from a fixed clock source, which does not vary with PCI power presence.
- 27. A method for supporting ASF in an ASD using one or more embedded processors, the method comprising:
providing a packet stream having both ASF and non ASF packets; filtering and separating the ASF packets from the non-ASF packets; accepting the ASF related packets to be processed; examining the ASF related packets using a firmware routines running on the one or more embedded processors; and generating an appropriate response.
- 28. An apparatus for processing communications packets in an ASD, the apparatus comprising:
an input for accepting a sequence of packets, the sequence of packets including a plurality of types of packets; a pattern matching circuit for detecting ARP (Address Resolution Protocol) packets; a queue for placing the detected ARP packets in; and at least one processor to remove the ARP packets from the queue and process the ARP packets.
- 29. An apparatus for processing communications packets in an ASD, the apparatus comprising:
an input for accepting a sequence of packets, the sequence of packets including a plurality of types of packets; a pattern matching circuit for detecting RMCP packets; a queue for placing the detected RMCP packets in; and at least one processor to remove the RMCP packets from the queue and process the RMCP packets.
- 30. An apparatus for providing ASF timers the apparatus comprising:
a plurality of hardware timers; at least one embedded processor, which loads the timers with a count; at least one embedded processor, which and starts the timers counting; a register for receiving an indication of timer expiration on expiration of the count for each timer; and at least one embedded processor, which examines the indication of timer expiration of at least one of the timers.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority on the basis of the following U.S. Provisional Patent Application, the entire contents of which is herein incorporated by reference as though set forth in full: Ser. No. 60/286,320, filed Apr. 24, 2001, and entitled “INTEGRATED GIGABIT ETHERNET PCI-X CONTROLLER.” The present application also is related to co-pending U.S. patent application Ser. No. 09/865,844, filed May 25, 2001, and entitled “MULTIPROTOCOL COMPUTER BUS INTERFACE ADAPTER AND METHOD,” the entire contents of which is incorporated herein by reference as though set forth in full. The present application also is related to co-pending U.S. patent application entitled “POWER MANAGEMENT SYSTEM AND METHOD,” with named inventors Steven B. Lindsay, Andrew SeungHo Hwang, Andrew M. Naylor, Scott Sterling McDonald and Habib Anthony Abouhossien filed on Apr. 24, 2002, the entire contents of which is incorporated herein by reference as though set forth in full. The present application also is related to co-pending United States Patent Application entitled “ASF MEMORY LOADING AND HANDLING SYSTEM,” with named inventors Steven B. Lindsay, Andrew SeungHo Hwang and Andrew M. Naylor filed on Apr. 24, 2002, the entire contents of which is incorporated herein by reference as though set forth in full. The present application also is related to co-pending U.S. patent application entitled “INTEGRATED GIGABIT ETHERNET PCI-X CONTROLLER,” with named inventors Steven B. Lindsay, Andrew SeungHo Hwang, Andrew M. Naylor, Michael Asker, Jennifer Chaio, Myles Wakayama and Gary Alvstad filed on Apr. 24, 2002, the entire contents of which is incorporated herein by reference as though set forth in full.
Provisional Applications (1)
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Number |
Date |
Country |
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60286320 |
Apr 2001 |
US |