Claims
- 1. A controller for an anti-lock brake system, the controller comprising:a microprocessor adapted to operate the anti-lock brake system, said microprocessor including a status port adapted to be connected to a four wheel drive transfer case; and a verification algorithm for said microprocessor, said algorithm being responsive to a condition at said status port to cause said microprocessor to disable the anti-lock brake system.
- 2. The controller according to claim 1 wherein said algorithm indexes a counter by a predetermined amount upon each successive occurrence of said condition at said status port and further wherein said algorithm is responsive to prevent said microprocessor from operating the anti-lock brake system when the total count of said occurrences exceeds a predetermined threshold.
- 3. The controller according to claim 2 wherein said algorithm is further responsive to said condition at said status port to cause said microprocessor to generate an alarm signal.
- 4. The controller according to claim 2 wherein said counter is indexed when a constant non-zero voltage is applied to said status port.
- 5. The controller according to claim 2 wherein said counter is indexed when said status port voltage is zero.
- 6. The controller according to claim 2 wherein said counter is indexed when a time varying status signal is applied to said status port.
- 7. The controller according to claim 6 wherein said status signal has a frequency and said counter is indexed when said status signal frequency is outside of a predetermined frequency range.
- 8. The controller according to claim 7 wherein said counter is reset when said status signal frequency is within said predetermined frequency range.
- 9. The controller according to claim 6 wherein said status signal has a frequency and said counter is indexed when said status signal frequency is outside of one of a plurality of predetermined frequency ranges.
- 10. The controller according to claim 9 wherein said counter is reset when said status signal includes a frequency which is within one of said frequency ranges.
- 11. A controller for an anti-lock brake system, the controller comprising:a microprocessor adapted to operate the anti-lock brake system, said microprocessor including a status port adapted to be connected to a source of a predetermined voltage; and a verification algorithm for said microprocessor, said algorithm being responsive to a condition at said status port to cause said microprocessor to disable the anti-lock brake system.
- 12. The controller according to claim 11 wherein said algorithm indexes a counter by a predetermined amount upon each successive occurrence of said condition at said status port and further wherein said algorithm is responsive to prevent said microprocessor from operating the anti-lock brake system upon the total count of said occurrences exceeds a predetermined threshold.
- 13. The controller according to claim 12 wherein said counter is decremented by a predetermined amount upon a non-occurrence of said condition.
- 14. The controller according to claim 13 wherein said algorithm is further responsive to said condition at said status port to cause said microprocessor to generate an alarm signal.
- 15. The controller according is claim 13 wherein said predetermined status port voltage is zero and said counter is indexed when there is a non-zero voltage at said status port.
- 16. The controller according to claim 15 wherein said non-zero voltage has a predetermined frequency.
- 17. The controller according to claim 13 wherein said predetermined status port voltage is a non-zero voltage and said counter is indexed when there is a zero voltage at said status port.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/048,859, filed Jun. 6, 1997.
US Referenced Citations (7)
Provisional Applications (1)
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Number |
Date |
Country |
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60/048859 |
Jun 1997 |
US |