Claims
- 1. A method of preparing a VCSEL comprising patterning mesas in a substrate, depositing GaInP on said mesas so as to form a lattice mismatch, growing an active layer of successive layers of GaAs and InGaP; andgrowing a p-type layer of GaInP/GaAs as a DBR.
- 2. The method of claim 1, including patterning the mesas in a 16×16 μm size or a 400×400 μm size.
- 3. The method of claim 1, wherein the step of growing said active layer includes growing successive layers of 69 nm GaAs and 76 nm GaInP in a superlattice structure.
- 4. A method of preparing a VCSEL comprising the steps of:a) preparing a layer of GaAs; b) patterning said GaAs layer with photoresist; c) etching said patterned photo resist to form discrete spaced mesas; d) depositing a layer of GaInP on each of said mesas; e) forming a superlattice of GaAs/GaInP on said GaInP layer on each of said mesas; and f) forming a p-type distributed bragg reflector on said superlattice structure.
- 5. The method of claim 4 wherein each of said mesas are formed to be from about 16 μm×16 μm to about 400 μm×400 μm.
- 6. The method of claim 4 wherein said p-type distributed bragg reflector is formed of GaInP/GaAs.
- 7. The method of claim 4 further including the step of doping said p-type distributed bragg reflector with a p-type dopant selected from the group consisting of Zn, Be, Cd, Mg and mixtures thereof.
Parent Case Info
This application is a divisional of U.S. patent application Ser. No. 09/550,665 on Apr. 17, 2000, now U.S. Pat. No. 4,480,520.
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