AMBA modular memory controller

Abstract

A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.

Description

FIELD OF THE INVENTION

[0002] The present invention relates to multiport devices generally and, more particularly, to a peripheral controller for a multiport bus architecture slave device.

BACKGROUND OF THE INVENTION

[0003] Multiport slave peripheral circuit designs are commonly a single monolithic block within an application specific integrated circuit (ASIC). The monolithic block approach creates difficulties in reusing all or portions of the design since the design is customized for the original ASIC application. Where portions of the design are reused, maintenance becomes difficult where the reused blocks are modified in order to be fully integrated with other blocks in the new application.

[0004] Another limitation of the monolithic block approach is encountered where bus traffic at a particular port varies among and/or within applications. For example, a multiport Advanced High-performance Bus (AHB) application may use a bus A to support very bursty but short traffic requests while a bus B may use 64-bit, long linear requests. A monolithic block optimized for bus A will not perform as well with bus B. What is desired is a reusable multiport slave peripheral architecture where a peripheral control function can be adapted to meet a wide number of bus interfaces types, arbitration schemes, and peripheral resources.

SUMMARY OF THE INVENTION

[0005] The present invention concerns a circuit generally comprising a command buffer and a read buffer. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.

[0006] The objects, features and advantages of the present invention include providing a peripheral controller for a multiport slave device that may (i) allow for compile-time determination of an internal and/or external memory interface data width, (ii) support double data rate memory device, (iii) support four to thirty-two banks of memory circuits, (iv) address high density memory circuits, (v) monitor read/write performance, and/or (vi) accommodate different latency options that may allow use of both registered and non-registered SSTL2 output buffers for primary rate DDR signals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:

[0008] FIG. 1 is a block diagram of an example system in accordance with a preferred embodiment of the present invention;

[0009] FIG. 2 is a block diagram of a portion of a second example system;

[0010] FIG. 3 is a block diagram of a peripheral controller circuit;

[0011] FIG. 4 is a detailed block diagram of the peripheral controller circuit;

[0012] FIG. 5 is a timing diagram for writing and reading to and from control registers;

[0013] FIG. 6 is a block diagram of a first embodiment of the peripheral controller circuit;

[0014] FIG. 7 is a block diagram of a second embodiment of the peripheral controller circuit;

[0015] FIG. 8 is a block diagram of a third embodiment of the peripheral controller circuit;

[0016] FIG. 9 is a block diagram of a fourth embodiment of the peripheral controller circuit;

[0017] FIG. 10 is a block diagram of a fifth embodiment of the peripheral controller circuit;

[0018] FIG. 11 is a timing diagram of an example two burst read from the peripheral controller circuit;

[0019] FIG. 12 is a timing diagram of an example four burst read from the peripheral controller circuit;

[0020] FIG. 13 is a timing diagram of an example two burst write to the peripheral controller circuit;

[0021] FIG. 14 is a timing diagram of an example four burst write to the peripheral controller circuit; and

[0022] FIG. 15 is a timing diagram of an example read from a double data rate (DDR) memory circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Referring to FIG. 1, a block diagram of an example system 100 is shown in accordance with a preferred embodiment of the present invention. The system 100 generally comprises multiple line buffer circuits or blocks 102a-d, a configuration port circuit or block 104, an arbiter circuit or block 106, a multiplexer circuit or block 108, a peripheral controller circuit or block 110, an optional internal physical interface circuit or block 112, and an optional external physical interface circuit or block 114. Each line buffer circuit 102a-d may have an interface 116a-d configured to couple to a bus 118a-d external to the system 100. The configuration port circuit 104 may have an interface 117 configured to couple to a configuration bus 119 external to the system 100. The external physical interface block 114 may have an interface 122 connectable to a peripheral circuit or block 120 external to the system 100. Multiple register interface busses or internal busses 123 may link the configuration port circuit 104 to the line buffer circuits 102a-d, the arbiter circuit 106, the peripheral controller circuit 110, and/or the internal physical interface circuit 112.

[0024] The system 100 may provide interfaces between multiple AHB masters (not shown) and the peripheral controller circuit 110 for data transfers. The system 100 generally uses a line buffer architecture as opposed to a first-in-first-out (FIFO) based architecture. The line buffer circuits 102a-d may handle an AHB slave protocol then translate AHB requests into requests to the arbiter circuit 106 and the peripheral controller circuit 110. The transactions (e.g., reads and writes) to the peripheral controller circuit 110 may be handled as single line requests. Each line request may involve moving multiple words of data (e.g., 64 or 128 bits) in multiple beats or transfers (e.g., two or four). Because the requests may be handled on a line basis, line registers or buffers in the system 100 generally use a same line size (e.g., 128 bits or 256 bits). The line size may also be in relationship to a width of the external data path to the peripheral circuit 120 and a number of beats used to transfer the data. For example, the data path width (e.g., in bits) times the number of beats (e.g., four or eight) generally equals the width of the line buffers.

[0025] The arbiter circuit 106 generally chooses which request from which line buffer circuit 102a-d may be serviced by the peripheral controller circuit 110. The arbiter circuit 106 may also translate some of the line buffer requests into a proper protocol for the peripheral controller circuit 110. The multiplexer circuit 108 (part of the arbiter circuit 106) may route the request to the peripheral controller circuit 110, one at a time.

[0026] The peripheral controller circuit 110 generally translates commands into actual interface signal levels used to control the external peripheral circuit 120. The peripheral controller circuit 110 may be programed to provide specific interface signals/timing for each type of peripheral circuit 120. The peripheral controller circuit 110 may be programed via the configuration port circuit 104. The external physical interface circuit 114 generally contains special input/output cells for communicating with the peripheral circuit 120. The internal physical interface circuit 112 generally provides programming access to the external physical interface circuit 114 through the configuration port circuit 104. Programming may include, but is not limited to, delay value and bypass control signals.

[0027] In one embodiment, the peripheral controller circuit 110 and the external physical interface circuit 114 may be designed to interface to a double data rate (DDR) memory type of peripheral circuit 120. In other embodiments, the peripheral controller circuit 110 may be configured as a random access memory (RAM) controller, a read-only memory (ROM) controller, a mass memory drive controller, an input/output device controller, a communications link controller, or the like. The external physical interface circuit 114 may be omitted where the peripheral controller circuit 110 may interface directly to the peripheral circuit 120 or where the peripheral resource may be contained within the peripheral controller circuit 110.

[0028] Each bus 118a-d may be implemented as an Advanced High-Performance Bus (AHB) defined in an “Advanced Microcontroller Bus Architecture (AMBA) Specification”, revision 2.0, 1999, published by ARM Limited, Cambridge, England and hereby incorporated by reference in its entirety. A number of the line buffer circuits 102a-b may be varied to match a number of the AHB busses 118a-d. The line buffer circuits 102a-d may also be configured to interface to other types of busses and various configurations of the AHB bus to meet the criteria of the particular application. The variations may include bus width, bus speed, endianness and/or allowed transfer types.

[0029] The configuration bus 119 may be configured as an AHB bus. In one embodiment, the configuration bus 119 may be configured as an Advanced Peripheral Bus (APB) as defined by the AMBA specification. Other busses may be used as the configuration bus 119 to meet a design criteria of a particular application.

[0030] The line buffer circuits 102a-d may provide configurable data width translations and a number of data beats between the AHB busses 118a-d and the peripheral controller circuit 110. Generally, each transfer of data between the line buffer circuits 102a-d and the peripheral controller circuit 110 (e.g., READ_DATA and WRITE_DATA) may be as wide or wider than transfers between the line buffer circuits 102a-d and the AHB busses 118a-d. Each transfer of data between the line buffer circuits 102a-d and the peripheral controller circuit 110 may be implemented as two or more (e.g., two or four) data beats.

[0031] The line buffer circuits 102a-d may provide endian translations between the AHB busses 118a-d and the peripheral controller circuit 110, as appropriate. For example, the peripheral controller circuit 110 and the AHB bus 118a may treat data as big endian while the AHB busses 118b-d may treat data as little endian. Other combinations of big and little endianness may be provided to meet a criteria of a particular application.

[0032] Address information (e.g., ADDRESS) may be transferred from the AHB busses 118a-d to the peripheral controller circuit 110 with or without modification depending upon configuration bits set within the line buffer circuits 102a-d through the configuration port circuit 104. Command information (e.g., COMMAND) may be generated by each line buffer circuit 102a-d for accessing the peripheral controller circuit 110. A set of signals (e.g., SNOOP_PATH) may be tapped from outputs of the multiplexer circuit 108 and provided to the line buffer circuits 102a-d to handle cases where a first line buffer circuit 102a-d may be preparing to read from an address that a second line buffer circuit 102a-d may be preparing to write.

[0033] Each line buffer circuit 102a-d may be configured as an AHB slave device that buffers requests to the peripheral controller circuit 110. Data may be written and/or read from the peripheral controller circuit 110 in multi-bit lines (e.g., 256-bits or 128-bits). Read data from the peripheral controller circuit 110 may be transmitted to each line buffer circuit 102a-d simultaneously. Information identifying which line buffer circuit 102a-d the data is intended for may also be transmitted by the peripheral controller circuit 110. The write data presented through the line buffer circuits 102a-d may be routed to the peripheral controller circuit 110 through the multiplexer circuit 108. Using only 256-bit or 128-bit requests to the peripheral controller circuit 110 may simplify control logic (e.g., FIG. 6) of the peripheral controller circuit 110 compared with designs accepting 256, 128, 64, 32 and 16-bit requests.

[0034] The peripheral controller circuit 110 generally receives several (e.g., three) clocks. A clock signal (e.g., CLK1), or sub-multiple thereof, may provide basic clocking for the peripheral controller circuit 110 and the line buffer circuits 102a-d. The clock signal CLK1 may have a frequency equal to a highest frequency an AHB clock (e.g., HCLK) operated with the system 100. The frequency of the clock signal CLK1 may also be a primary rate frequency of the external peripheral circuit 120. The clock signal CLK1 generally has a 50/50 duty cycle. The clock signal CLK1 may be used by the line buffer circuits 102a-d as the AMBA defined clock signal HCLK would be used. If the clock signal HCLK is a sub-multiple of the clock signal CLK1, an enable signal (e.g., HCLKEN) may be used to indicate active edges of the clock signal CLK1. In one embodiment, the clock signal CLK1 may have a maximum frequency of approximately 133 megahertz (MHz) and a minimum frequency of approximately 50 MHz. The minimum frequency may dependent on a minimum frequency of the peripheral circuit 120.

[0035] Another clock signal (e.g., CLK2) may be implemented as a double rate clock having rising edge coinciding with the edges of the clock signal CLK1. The clock signal CLK2 may have a duty cycle less rigorous than 50/50. An enable signal (e.g., CLKPHASE) may be a delayed version of the clock signal CLK1 and is generally used as an enable for the double rate clock signal CLK2 to discern the phases. The read data transfers from the peripheral controller circuit 110 may occur at a clock signal CLK1 rate. Write transfers to the peripheral controller circuit 110 may occur at a rate of the clock signal CLK2.

[0036] A third clock signal (e.g., HCLKCFG) may be used in place of the AMBA clock signal HCLK for the configuration port circuit 104. The configuration port circuit 104 generally does not use the enable signal HCLKEN associated with the port directly. The configuration port circuit 104 generally expects the clock signal HCLKCFG to have the proper frequency divisions when a sub-multiple frequency is used.

[0037] A reset scheme used in the system 100 may be completely synchronous. Individual line buffer circuits 102a-d may be reset by a reset signal (e.g., HRESETn) provided from the associated AHB bus 118a-d to the particular line buffer circuits 102a-d. A reset state is generally accomplished after a single cycle of the clock signal CLK1. The system 100 may be designed so that a reset on one of the line buffer circuits 102a-d may not affect other AHB transactions going on through the other line buffer circuits 102a-d nor affect ongoing read/write requests to the peripheral controller circuit 110.

[0038] The arbiter circuit 106, peripheral controller circuit 110 and internal busses 123 may be reset by the configuration bus 119 reset signal HRESETn. Any ongoing read/write requests to the peripheral controller circuit 110 may be disrupted and an entire state of the peripheral controller circuit 110 may need to be reconfigured. In addition, because a refresh operation may be disrupted as part of the reset operation, a memory type peripheral device 120 may need to be reinitialized. As with the reset of the line buffer circuits 102a-d, the configuration port reset signal HRESETCFGn should be asserted for at least a cycle of the clock signal CLK1.

[0039] Referring to FIG. 2, a block diagram of a portion of a second example system 100a is shown. The system 100a may be implemented using multiple arbiter circuits 106a-b and/or multiple peripheral controller circuits 110x-z. Several multiplexers 125a-b, 127a-b, 129a-b, 131a-b and 133a-b may be included in the system 10a to allow the line buffer circuits 102a-b to control access selection among the arbiter circuits 106a-b and the peripheral controller circuits 110x-z. The multiplexers 125a-b, 127a-b, 129a-b, 131a-b and 133a-b may be implemented as part of the line buffer circuits 102a-b or as separate modules.

[0040] A signal (e.g., LBM0-LBM1) may be generated by each of the line buffer circuits 102a-b to control the multiplexers 125a-b, 127a-b, 129a-b, 131a-b and 133a-b, respectively. Each line buffer circuit 102a-b may use a requested address received from the AHB busses 118a-b to determine which arbiter circuit 106a-b controls access to a particular peripheral controller circuit 110x-z mapped to the requested address. Therefore, multiple line buffer circuits 102a-b may request arbitration and receive a grant from multiple arbiter circuits 106a-b substantially simultaneously. For example, the first line buffer circuit 102a may request access to the first peripheral controller circuit 110x from the first arbiter circuit 106a while the second line buffer circuit 102b may concurrently request access to the third peripheral controller circuit 110z from the second arbiter circuit 106b.

[0041] A multiplexer 108a may provide access to the first peripheral controller circuit 110x by the line buffer circuits 102a-b. A signal (e.g., ARM1) may be generated by the first arbiter circuit 106a to address the multiplexer 108a. A multiplexer 108b may provide access to the second and the third peripheral controller circuits 110y-z by the line buffer circuits 102a-b. A signal (e.g., ARM2) may be generated by the second arbiter circuit 106b to address the multiplexer 108b. Another multiplexer 135 may provide access selection between the second peripheral circuit 110y and the third peripheral circuit 110z. A signal (e.g., ARM3) may be generated by the second arbiter circuit 106b to address the multiplexer 135. The signal ARM3 may also address a multiplexer 137 that routes the read data from the second peripheral control circuit 110y or the third peripheral control circuit 110z back to the line buffer circuits 102a-b (via the multiplexers 133a-b). In one embodiment, the third peripheral controller circuit 110z, the multiplexer 135 and the multiplexer 137 may be eliminated such that the second arbiter circuit 106b arbitrates for access only to the second peripheral controller circuit 110y.

[0042] Referring to FIG. 3, a block diagram of a peripheral controller circuit 110 is shown. The input and output signals for the peripheral controller circuit 110 may be grouped together based upon signal sources and destinations. The groupings may include, but may not be limited to clock signals, line buffer signals, arbiter signals, and control register interface signals. External physical interface circuit signals and peripheral circuit signals may be included where appropriate to interface with the external physical interface circuit 114 and/or directly to the peripheral circuit 120.

[0043] Referring to FIG. 4, a detailed block diagram of the peripheral controller circuit 110 is shown. The peripheral controller circuit 110 generally comprises a circuit or block 124, a circuit or block 126 and one or more registers or blocks 128. The circuit 124 may be implemented as a port interface circuit. The port interface circuit 124 generally communicates with the AHB busses 118a-d through the line buffer circuit 102a-d and the multiplexer circuit 108. The port interface circuit 124 may establish a standard interface to the rest of the system 100 for most or all implementations of the peripheral controller circuit 110.

[0044] The circuit 126 may be implemented as a resource circuit. The resource circuit 126 may be implementation dependent. In some implementations, the resource circuit 126 may provide a storage resource requested through the AHB busses 118a-d. For example, the resource circuit 126 may provide memory, semaphore, and/or mailbox functionality. In other implementations, the resource circuit 126 may provide an interface to a resource 130 external to the peripheral controller circuit 110 through an interface 132. For example, the resource 130 may be a memory and/or communication capability. In one embodiment, the resource 130 may be a double data rate (DDR) memory capability incorporating the external interface circuit 114 and the peripheral circuit 120. The control registers 128 may provide a capability to program the port interface circuit 124 and/or the resource circuit 126 through the configuration port circuit 104.

[0045] The port interface circuit 124 generally comprises a circuit or block 134, a circuit or block 136, a circuit or block 138 and a circuit or block 140. The circuit 134 may be implemented as an address decoder. The address decoder may be configured to provide address translations between an address domain of the AHB busses 118a-d and another address domain of the resource circuit 126. The address decoder circuit 134 may receive the address signal ADDRESS and/or an address signal (e.g., CBC_ADD) and then generate another address signal (e.g., PIC_ADD).

[0046] The circuit 136 may be implemented as a command buffers and control circuit. The command buffer and control circuit 136 generally provides buffering of various command signals COMMAND from the arbiter circuit 106. The command buffer and control circuit 136 may also provide translations of the various command signals COMMAND being buffered into one or more command signals (e.g., PIC_CMD) understood by the resource circuit 126 and/or the resource 130. The command buffer and control circuit 136 may also generate the address signal CBC_ADD based upon a current command for use by the address decoder circuit 134.

[0047] The circuit 138 may be implemented as a write queue circuit. The write queue circuit 138 may be configured to queue or buffer data signals WRITE_DATA in a sequence as requested by the line buffer circuits 102a-d. Each data signal WRITE_DATA in the write queue circuit 138 may have one or more corresponding write commands in the command buffer and control circuit 134. The data signals WRITE_DATA may be transferred to the resource circuit 126 as a data signal (e.g., PIC_WDATA).

[0048] The circuit 140 may be implemented as a read buffer circuit. The read buffer 140 may store data signals (e.g., RC_RDATA) in a sequence as requested by the line buffer circuits 102a-d. Each read data signal RC_RDATA in the read buffer circuit 140 may have one or more associated read commands in the command buffer and control circuit 134. The read data signals RC_RDATA may be transferred to the line buffer circuits 102a-d as the data signal READ_DATA.

[0049] Referring to FIG. 5, a timing diagram for writing and reading to and from the control registers 128 is shown. During a read operation, an address signal (e.g., INT_R_ADDR), a control signal (e.g., INT_R_WRITE) and an enable signal (e.g., INT_R_ENABLE_MC) may be driven to the peripheral controller circuit 110. The peripheral controller circuit 110 may steer a data signal (e.g., MC_R_RDATA) back to the configuration port circuit 104. The data signal MC_R_RDATA may be registered by the clock HCLK within the configuration port circuit 104 and driven out onto the AHB Bus 119. During a write operation, the address signal INT_R_ADDR, the control signal INT_R_WRITE, the enable signal INT_R_ENABLE_MC and a data signal (e.g., INT_R_WRDATA) may be driven to the peripheral controller circuit 110 from the configuration port circuit 104 and clocked by the rising edge of INT_R_CLK. The signals shown in FIG. 5 may provide a simple interface that may be dedicated as a sideband control/status interface to the peripheral controller circuit 110. Similar interfaces to the other programmable elements, such as the line buffer circuit 102a-d, arbiter circuit 106 and/or the internal physical interface circuit 112 may also be implemented. In one embodiment, the signals shown in FIG. 5 may provide an alternate interface to the external peripheral circuit 120.

[0050] Referring to FIG. 6, a block diagram of a first embodiment of the peripheral controller circuit 110 is shown. The peripheral controller circuit 110 may be implemented as the DDR memory controller circuit 110a. The external physical interface circuit 114 may be implemented as a DDR physical interface circuit 114a. The peripheral circuit 120 may be implemented as one or more DDR memory circuits or banks 120a. The port interface circuit 124 within the DDR memory controller circuit 120a may be configured as described above. The resource circuit 126 may be configured as a DDR resource circuit 126a to provide control and timing for the DDR memory circuits 120a.

[0051] The DDR memory controller circuit 110a generally enables the use of multiple on-chip AHB buses 118a-d which may allow concurrency of AHB transactions while at the same time providing for a common or centralized memory area between the AHB subsystems. Each of the AHB busses 118a-d may have a separate multiple-bit (e.g.; 32-bit) addressable memory region. The physical DDR memory circuit 120a may be mapped anywhere within the independent addressable regions. The multiport configuration may have an advantage over a multilayer bus implementation in that the DDR memory controller circuit 110a itself may prioritize requests (possibly under user control) and overlap operations to the external DDR memory circuit 120a in order to optimize both bandwidth and latency. The optimizations generally include such capabilities as read and write buffering, coherency detection, improved arbitration, and look ahead on DDR access requests while considering current DDR memory bank state. A read and write buffering within the line buffer circuits 102a-d may help reduce the access latency to the DDR memory circuit 120a and may also increase a utilization of the available bandwidth at the interface 122. The modular design of the system 100 may allow the architecture to be optimized for an expected AHB bus traffic profile.

[0052] The DDR resource circuit 126a generally comprises a circuit or block 142, a circuit or block 144 and an optional circuit or block 146. The circuit 142 may be configured as a state machine. The state machine 142 may provide signal sequencing for controlling the DDR memory circuits 120a. The circuit 144 may be implemented as a programmable physical timing circuit. The programmable physical timing circuit 144 may regulate timing of commands and data to and from the DDR memory circuits 120a based upon the sequences generated by the state machine circuit 142. The circuit 146 may be implemented as a performance monitor circuit. The performance monitor circuit 146 generally monitors multiple factors within the DDR memory controller that may aid in adjusting the programmable settings to maximize performance.

[0053] Configuration of the DDR memory controller circuit 110a may support a wide variety of compile-time options, strappable options, and/or programming of the control registers 128. Additional configuration may be generated to meet a design criteria of a particular application. The programmable options may affect such things as line buffer circuit operation, arbitration priority scheme, DDR device support and modes, and a number of beats (e.g., 8) per DDR memory burst. Other options may be implemented to meet the criteria of a particular implementation. Table I lists compile-time options that may be supported by the DDR memory controller circuit 120a:

TABLE I
Compile-Time Options Option Description
DDR bank support     Supports 4-32 banks. Bank
                     state machines may be in
                     groups of 4 (e.g., 4, 8,
                     12, etc.). DDR bank support
                     effectively selects a
                     number of DDR SDRAM stacks
                     that may be supported
                     (e.g., depth of memory).
Number of AHB ports  2-8 ports.
DDR external data    External DDR width of 16,
path width/line      32, 64 or 72 bits. Line
buffer size          buffer size of 128 or 256
                     bits. External DDR width,
                     number of DDR burst beats,
                     and line buffer size are
                     generally closely related.
                     Line buffer size may be
                     optimized to match a DDR
                     burst block size.
Compile option for   Included or not included.
inclusion of
performance monitor
registers in the DDR
memory controller
circuit.

[0054] Each strappable option may be set using a strap pin or bonding pad (not shown). The strap pin may be connected to power or ground to determine the option. The strappable options may be described in Table II as follows:

TABLE II
Strap Option Name       Option Description
Endianness              Big or little endian
                        (per port).
AHB port width          32 or 64-bit (per port)
DDR primary rate signal Controls primary rate
latency                 DDR signal bypass
                        multiplexer. Allows use
                        of either registered or
                        non-registered SSTL2
                        input/output buffers.

[0055] Programmer visible objects within a multiport DDR memory type system 100 may be summarized below. High level guidelines for complex peripheral (e.g., memory) controller circuits 110 may use an address space as follows:

// Configuration Register Block Base Addr [15:0]
// Arbiter:        0000h --> 7FFFh
// DDR Controller: 8000h --> 9FFFh
// DDR Physical:   A000h --> BFFFh
//
// Line Buffer 0:  C000h --> C3FFh
// Line Buffer 1:  C400h --> CVFFh
// Line Buffer 2:  C800h --> CBFFh
// Line Buffer 3:  CC00h --> CFFFh
//
// Line Buffer 4:  D000h --> D3FFh
// Line Buffer 5:  D400h --> D7FFh
// Line Buffer 6:  D800h --> DBFFh
// Line Buffer 7:  DC00h --> DFFFh
//
// Line Buffer 8:  E000h --> E3FFh
// Line Buffer 9:  E400h --> E7FFh
// Line Buffer 10: E800h --> EBFFh
// Line Buffer 11: EC00h --> EFFFh
//
// Line Buffer 12: F000h --> F3FFh
// Line Buffer 13: F400h --> F7FFh
// Line Buffer 14: F800h --> FBFFh
// Line Buffer 15: FC00h --> FFFFh
//

[0056] The control registers 128 of a DDR memory controller circuit 110a and the external physical interface circuit 114 may be given in Table III and Table IV, respectively, as follows:

TABLE III
Address (hex)              Register Name
Periph_Base + 8000         Reserved for future reset
Periph_Base + 8004 to 8010 Reserved for interrupts
Periph_Base + 8014         Mode register
Periph_Base + 8018         Extended mode register
Periph_Base + 801C         Memory configuration
Periph_Base + 8020         Backdoor control 1
Periph_Base + 8024         Backdoor control 2
Periph_Base + 8028         Backdoor read data 1
Periph_Base + 802C         Backdoor read data 2
Periph_Base + 8030         Backdoor read data 3
Periph_Base + 8034         Backdoor write data 1
Periph_Base + 8038         Backdoor write data 2
Periph_Base + 803C         Backdoor write data 3
Periph_Base + 8040         Backdoor control 3
Periph_Base + 8044 to 804C Reserved
Periph_Base + 8050         Bank configuration 1
Periph_Base + 8054         Bank configuration 2
Periph_Base + 8058         Reserved
Periph_Base + 805C         Reserved
Periph_Base + 8060         Performance monitor control
Periph_Base + 8064         Performance monitor preload
Periph_Base + 8068 to 8070 Reserved
Periph_Base + 8074         Time Active to Precharge min.
Periph_Base + 8078         Time Active to Precharge max.
Periph_Base + 807C         Time Active to Active/Auto
                           Refresh
Periph_Base + 8080         Time Active to Read/Write
                           Delay
Periph_Base + 8084         Time Average Refresh Interval
Periph_Base + 8088         Time Refresh Command Period
Periph_Base + 808C         Time Precharge Command Period
Periph_Base + 8090         Time Active Bank A to Active
                           Bank B Period
Periph_Base + 8094         Time Write Recovery to
                           Precharge Same Bank
Periph_Base + 8098         Time Write to Read Delay
Periph_Base + 809C         Time Exit Self Refresh to
                           non-Read Command
Periph_Base + 80A0         Time Exit Self Refresh to Read
                           Command
Periph_Base + 80A4         Time Auto Precharge Write
                           Recovery plus Precharge
Periph_Base + 80A8         Back-to-back read/write
Periph_Base + 80AC         Back-to-back reads
Periph_Base + 80B0         Back-to-back write/read
Periph_Base + 80B4         Back-to-back writes
Periph_Base + 80B8         Reserved
Periph_Base + 80BC         Time Active to Read
                           Autoprecharge
Periph_Base + 80C0         Write Recovery Autoprecharge
Periph_Base + 80C4 to 80DC Reserved
Periph_Base + 80E0         Miscellaneous command timing
                           register
Periph_Base + 80E4         Reserved
Periph_Base + 80E8         Miscellaneous command latency
Periph_Base + 80EC         End of command timing register
Periph_Base + 80F0 to 810C Reserved
Periph_Base + 8110         Read timing register
Periph_Base + 8114         Read timing loop register
Periph_Base + 8118         Read latency
Periph_Base + 811C         Reserved
Periph_Base + 8120         Read gate timing register
Periph_Base + 8124         Read gate timing loop register
Periph_Base + 8128         Read gate latency
Periph_Base + 812C         Reserved
Periph_Base + 8130         Load even bank timing register
Periph_Base + 8134         Load even bank timing loop
                           register
Periph_Base + 8138         Load even bank latency
Periph_Base + 813C         Reserved
Periph_Base + 8140         Load odd bank timing register
Periph_Base + 8144         Load odd bank timing loop
                           register
Periph_Base + 8148         Load odd bank latency
Periph_Base + 814C         Reserved
Periph_Base + 8150         Read allow timing register
Periph_Base + 8154         Read allow timing loop
                           register
Periph_Base + 8158         End of read timing register
Periph_Base + 815C         End of read timing loop
                           register
Periph_Base + 8160 to 817C Reserved
Periph_Base + 8180         Data bus data mask timing
                           register
Periph_Base + 8184         Data bus data mask timing loop
                           register
Periph_Base + 8188         Data bus data mask latency
Periph_Base + 818C         Reserved
Periph_Base + 8190         Data bus output enable timing
                           register
Periph_Base + 8194         Data bus output enable timing
                           loop register
Periph_Base + 8198         Data bus output enable latency
Periph_Base + 819C         Reserved
Periph_Base + 81A0         Data strobe timing register
Periph_Base + 81A4         Data strobe timing loop
                           register
Periph_Base + 81A8         Data strobe latency
Periph_Base + 81AC         Reserved
Periph_Base + 81B0         Data strobe output enable
                           timing loop register
Periph_Base + 81B4         Data strobe output enable
                           timing loop register
Periph_Base + 81B8         Data strobe output enable
                           latency
Periph_Base + 81BC         Reserved
Periph_Base + 81C0         Write allow timing register
Periph_Base + 81C4         Write allow timing loop
                           register
Periph_Base + 81C8         End of write timing register
Periph_Base + 81CC         End of write timing loop
                           register
Periph_Base + 81D0 to 81EC Reserved
Periph_Base + 81F0         Inactive register
Periph_Base + 81F4 to 81FC Reserved
Periph_Base + 8200         Interval timer LSB
Periph_Base + 8204         Interval timer MSB
Periph_Base + 8208         Request counter LSB
Periph_Base + 820C         Request counter MSB
Periph_Base + 8210         Read bursts counter LSB
Periph_Base + 8214         Read bursts counter MSB
Periph_Base + 8218         Write bursts counter LSB
Periph_Base + 821C         Write bursts counter MSB
Periph_Base + 8220         Bank miss counter LSB
Periph_Base + 8224         Bank miss counter MSB
Periph_Base + 8228         Refresh counter LSB
Periph_Base + 822C         Refresh counter MSB
Periph_Base + 8230         Priority 3 request control LSB
Periph_Base + 8234         Priority 3 request control MSB
Periph_Base + 8238         Priority 2 request control LSB
Periph_Base + 823C         Priority 2 request control MSB
Periph_Base + 8240         Priority 1 request control LSB
Periph_Base + 8244         Priority 1 request control MSB
Periph_Base + 8248         Priority 0 request control LSB
Periph_Base + 824C         Priority 0 request control MSB
Periph_Base + 8250 to 83FC Reserved
Periph_Base + 8300 to 83FC Reserved for bank state
                           machine vectors (for tests)
Periph_Base + 8400 to 8FFF Reserved

[0057]

TABLE IV
Address (hex)	Register Name	Reset State
Periph_Base + A000	Physical bypass control	0x0000_0000
Periph_Base + A004	Physical master delay	0x0000_0000
	data
Periph_Base + A008	Physical slave delay data	0x0000_0000
Periph_Base + A00C	Physical observable slave	0x0000_0000
	delay
Periph_Base + A010	Physical observable	0x0000_0000
	master delay and lock
Periph_Base + A014	Physical slave update	0x0000_0000
	strobe
Periph_Base + A018	Reserved
to BFFF

[0058] Both the DDR memory controller circuit 110a and the external DDR memory circuit 120a (e.g., SDRAM devices) generally use specific initialization sequences to be performed before the peripheral resource may be used. There may be several (e.g., five) separate initialization sequences which should be performed as follows:

[0059] 1) DDR memory controller circuit initialization (e.g., timing registers, modes, etc.).

[0060] 2) Arbiter circuit initialization (e.g., Slot assignment, priorities, etc.).

[0061] 3) Line buffer circuit initialization (e.g., modes).

[0062] 4) DDR external physical interface circuit initialization.

[0063] 5) External DDR memory circuit configuration.

[0064] The interface signals for the DDR memory controller circuit 110a may be grouped by function as listed below. Clock Signals:

[0065] Primary Rate Clock (e.g., CLK1)—In

[0066] The clock signal CLK1 may be the primary rate DDR clock for the DDR memory controller circuit. The clock signal CLK1 may also be used by a DDR physical core-ware and within the DDR memory controller circuit in both the data path and control section of the controller. The rising edge of clock signal CLK1 should be coincident with the rising edge of clock signal CLK2.

[0067] Double Rate Clock (e.g., CLK2)—In

[0068] The clock signal CLK2 may be the double data rate clock for the DDR memory controller circuit. The clock signal CLK2 may also be used by the DDR physical core-ware and within the DDR memory controller circuit in both the data path and control section of the controller. The rising edge of clock signal CLK2 should be coincident with the rising edge of clock signal CLK1.

[0069] Phase Selector (e.g., CLKPHASE)—In

[0070] The signal CLKPHASE may be a delayed version of clock signal CLK1, used as an enable for registers clocked by the clock signal CLK2 to differentiate the two edges of the clock signal CLK2.

[0071] AHB Data Port Signals (e.g., Address/Data/Control). The AHB busses 118a-d generally act as high-performance system backbone busses. Each AHB bus 118a-d may support an efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions. The AHB data port signals:

[0072] AHB Bus Clock (e.g., HCLK)—In

[0073] The main clock signal for all AHB bus transfers. All signal timing may be related to a rising edge of the clock signal HCLK.

[0074] AHB Bus Clock Enable (e.g., HCLKEN)—In

[0075] The enable may be used to synchronize the clock signal CLK1 to the AHB's clock HCLK domain. If the clock signal CLK1 is a higher rate than the clock signal HCLK, the signal HCLKEN may be used to sync the two domains.

[0076] AHB Reset (e.g., HRESETn)—In

[0077] The bus reset signal may be active LOW and may be used to reset the system and the bus. The signal HRESETn may be the only active LOW signal.

[0078] AHB Address Bus (e.g., HADDR[31:0])—In

[0079] A 32-bit system address bus.

[0080] AHB Transfer Type (e.g., HTRANS[1:0])—In

[0081] Indicates the type of the current transfer generally comprising Sequential, Non-Sequential, Idle and Busy.

[0082] AHB Transfer Direction (e.g., HWRITE)—In

[0083] When HIGH the signal HWRITE may indicate a write transfer and when LOW a read transfer.

[0084] AHB Transfer Size (e.g., HSIZE[2:0])—In Indicates the size of the transfer which is typically a byte (8-bit), halfword (16-bit) or word (32-bit). The protocol generally allows for larger transfer sizes up to a maximum of 1024 bits.

[0085] AHB Burst Type (e.g., HBURST[2:0])—In

[0086] Indicates if the transfer forms part of a burst. Four, eight and sixteen beat bursts may be supported and the burst may be either incrementing or wrapping.

[0087] AHB Protection Control (e.g., HPROT[3:0])—In

[0088] The protection control signals generally provide additional information about a bus access and may be primarily intended for use by any module that implements some level of protection. The signal HPROT[3:0] may indicate if the transfer is an opcode fetch or data access, as well as if the transfer may be a supervisor mode access or user mode access. For bus masters with a memory management unit the signal HPROT[3:0] may also indicate whether the current access is cacheable or bufferable.

[0089] AHB Write Data Bus (e.g., HWDATA[63/(31):0])—In

[0090] A write data bus that may be used to transfer data from the master to the bus slaves during write operations. The data bus width may be controlled by a signal HPORTSIZE[x].

[0091] AHB Slave Select (e.g., HSELx)—In

[0092] Each AHB slave may have an independent slave select signal and the signal may indicate that the current transfer is intended for the selected slave. The signal HSELx may be a combinational decode of the address bus.

[0093] AHB Read Data Bus (e.g., HRDATA[63/(31):0])—Out

[0094] A read data bus that may be used to transfer data from bus slaves to the bus master during read operations. The data bus width may be controlled by the signal HPORTSIZE[x].

[0095] AHB Transfer Done (e.g., HREADY)—In

[0096] When HIGH the signal HREADY may indicate that a transfer has finished on the bus. The signal may be driven LOW to extend a transfer. Slaves on the bus may use the signal HREADY as both an input and an output signal.

[0097] AHB Transfer Done (e.g., HREADYOUT)—Out

[0098] When HIGH the signal HREADY may indicate that a transfer has finished on the bus. The signal may be driven LOW to extend a transfer. Slaves on the bus may use the signal HREADY as both an input and an output signal.

[0099] AHB Transfer Responses (e.g., HRESP[1:0])—Out

[0100] The transfer response generally provides additional information on the status of a transfer. The responses generally comprise OKAY, ERROR, RETRY and SPLIT.

[0101] AHB Request Locked Transfers (e.g., HMASTLOCK)—In

[0102] When HIGH the signal may indicate that the master requests locked access to the bus and no other master should be granted the bus until the signal is LOW.

[0103] AHB Port Size (e.g., HPORTSIZE)—In

[0104] The signal generally controls the data path width for the AHB port for the appropriate data port (e.g., 0=32 bit data path and 1=64 bit data path).

[0105] AHB Port Endianness (e.g., BIGENDIAN)—In

[0106] The signal may control the data path endianness for the AHB port for the appropriate data port (e.g., 0=little endian and 1=big endian).

[0107] The configuration port circuit 104 may use the following signals:

[0108] Bus Clock (e.g., HCLKCFG)—In

[0109] The clock times all configuration bus transfers. All signal timings may be related to rising edge of signal HCLKCFG

[0110] Reset (e.g., HRESETnCFG)—In

[0111] The configuration bus reset signal may be active LOW and may be used to reset the system and the configuration bus.

[0112] Address Bus (e.g., HADDRCFG[31:0])—In

[0113] A 32-bit system address bus.

[0114] Transfer Type (e.g., HTRANSCFG[1:0])—In

[0115] Indicates the type of the current transfer generally comprising Sequential, Non-Sequential, Idle and Busy.

[0116] Transfer Direction (e.g., HWRITECFG)—In

[0117] When HIGH the signal may indicate a write transfer and when LOW a read transfer.

[0118] Transfer Size (e.g., HSIZECFG[2:0])—In

[0119] Indicates the size of the transfer which is typically byte (8-bit), halfword (16-bit) or word (32-bit). The configuration port circuit may respond with an error for any signal HSIZECFG not equal to 32 bits.

[0120] Write Data Bus (e.g., HWDATACFG[31:0])—In

[0121] A write data bus that may be used to transfer data from the master to the bus slaves during write operations.

[0122] Slave Select (e.g., HSELCFG)—In

[0123] Each configuration bus slave may have an independent slave select signal and the signal may indicate that the current transfer is intended for the selected slave. The signal may be a combinational decode of the address bus.

[0124] Read Data Bus (e.g., HRDATACFG[31:0])—Out

[0125] A read data bus that may be used to transfer data from bus slaves to the bus master during read operations.

[0126] Transfer Done (e.g., HREADYCFG)—In

[0127] When HIGH the signal HREADYCFG may indicate that a transfer has finished on the configuration bus. The signal may be driven LOW to extend a transfer. Slaves on the configuration bus may use the signal HREADYCFG as both an input and an output signal.

[0128] Transfer Done (e.g., HREADYOUTCFG)—Out

[0129] When HIGH the signal HREADYOUTCFG may indicate that a transfer has finished on the configuration bus. The signal may be driven LOW to extend a transfer. Slaves on the configuration bus may use the signal HREADYOUTCFG as both an input and an output signal.

[0130] Transfer Responses (e.g., HRESPCFG[1:0])—Out

[0131] The transfer response generally provides additional information on the status of a transfer. The responses generally comprise OKAY, ERROR, RETRY and SPLIT. The configuration port circuit may only respond with an OKAY or ERROR.

[0132] The peripheral controller circuit 110 may use the following signals:

[0133] Memory Controller Read Data (e.g., MC_READ_DATA[127|63|31:0])]—Out

[0134] Multiplexed read data from the peripheral controller circuit to the line buffer circuit. Depending on the line buffer circuit configuration identified, MC_READ_DATA may be 128, 64 or 32 bits.

[0135] Memory Controller Read Valid (e.g., MC-READ_VALID[3:0])—Out

[0136] Active high signal that may indicate the data on the read data inputs may be valid. Bit 0 may indicate a least significant quarter of the read line may be present, while bit 3 may indicate a most significant quarter may be present. For a 2-beat internal (4-beat external) transfer, two of the valid bits may be set per read from the peripheral controller circuit to locate the data. For a 4-beat internal (8-beat external) transfer, a valid bit may be set per read from the peripheral controller circuit to locate the data.

[0137] Memory Controller Read Tag (e.g., MC_READ_TAG[4:0])—Out

[0138] A five bit request tag returned by the peripheral controller circuit that may recognize a particular read request made by the line buffer circuit. In many cases, MC_READ_TAG may be simply reroute back a signal (e.g., LB_REQUEST_TAG) sent during the request by the line buffer circuit. Bit 4 may be the even/odd line flag that identifies a particular line buffer circuit for which the data may be targeted for.

[0139] Request Address (e.g., ARB_ADDRESS[31:2])—In

[0140] An address of the arbiter circuit request to the peripheral controller circuit. Driven on the rising edge of clock CLK1.

[0141] Transaction Request (e.g., ARB_REQUEST)—In

[0142] An active high signal to the peripheral controller circuit that a memory request may happen. The signal may be asserted on the rising edge of CLK1 and held asserted for a clock cycle. Driven on the rising edge of CLK1.

[0143] Request Tag (e.g., ARB_REQUEST_TAG[7:0])—In

[0144] An eight bit quantity generally used to recognize a particular request. The arbiter circuit may append a three bit AHB bus interface circuit address to a line buffer request value and send to the peripheral controller circuit. The peripheral controller circuit merely passes on the value until the read results may be returned to the line buffer circuits. Driven on the rising edge of CLK1.

[0145] Request Type (e.g., ARB_REQUEST_TYPE[3:0])—In

[0146] May indicate a read or write request. For some arbiter circuit/peripheral controller circuit combinations (e.g., a DDR memory controller) more requests types may be defined (e.g., precharge, activate, refresh, etc.). The line buffer circuit may support several read and write types (e.g., 0=No-op, 1 Refresh, 2=Precharge, 3=Active, 4=Write, 5=Read, and 6-F=No-op). Driven on the rising edge of CLK1.

[0147] Write Data (e.g., ARB_WRITE_DATA[X:0])—In

[0148] Multiplexed write data from the line buffer circuits to the peripheral controller circuit via the arbiter data path multiplexer circuit 108. The bus width may be 32, 64, 128, or 144 bits and may be set as a compile time option. Driven on the rising edge of CLK2.

[0149] Byte Write Enable (e.g., ARB_WRITE_ENABLE[X:0])—In

[0150] An active high write enable for each byte of write data. The width of the byte write enable may depend on the data width from the line buffer circuits and may be set as a compile time option. The peripheral controller circuit may use the enable bits to extract the valid write data from the transfers. Driven on the rising edge of CLK2.

[0151] Register Bus Read Data (e.g., MC_R_RDATA[X:0])—Out

[0152] The peripheral controller circuit may place the register data corresponding to INT_R_ADDR on a register bus. The read data bus may be up to 32-bits wide. The signal may be derived from combinational logic and may be valid on the rising edge of INT_R_CLK.

[0153] Register Bus Address (e.g., INT_R_ADDR[10:2])—In

[0154] An address bus that may be nine bits to allow decoding of the control registers in the peripheral controller circuit. Bits 0 and 1 may not be included because the AHB may use word addressing. Driven on the rising edge of INT_R_CLK.

[0155] Register Bus Clock (e.g, INT_R_CLK)—In

[0156] A rising edge of INT_R_CLK may be used to time transfers on the register bus.

[0157] Register Bus Enable (e.g., INT_R_ENABLE_ARB)—In

[0158] Generally indicates that the transfer on the register bus may be intended for the peripheral controller circuit. Driven on the rising edge of INT_R_CLK.

[0159] Register Bus Reset (e.g., INT_R_RESETn)—In May be active LOW and may be synchronous with respect to INT_R_CLK.

[0160] Register Bus Write Data (e.g., INT_R_WRDATA[31:0])—In

[0161] May contain write data for write transfers. The write data bus may be up to 32-bits wide. Driven on the rising edge of INT_R_CLK.

[0162] Register Bus Write (e.g., INT_R_WRITE)—In

[0163] A logical HIGH may indicate a write access and a logical LOW may indicate a read access. Driven on the rising edge of INT_R_CLK.

[0164] The DDR memory circuit 120a may use the following signals:

[0165] Clock (e.g., DDRCK)—N/A

[0166] The signal DDRCK along with a signal DDRCKn may be differential clock outputs. All address and control input signals may be sampled on the crossing of the positive edge of DDRCK and negative edge of DDRCKn. (The signals DDRCK and DDRCKn may not have an actual interface to the DDR memory controller circuit but may be included here for completeness.)

[0167] Clock Inverted (e.g., DDRCKn)—N/A

[0168] See the description for the signal DDRCK. (The signals DDRCK and DDRCKn may not have an actual interface to the DDR memory controller circuit but may be included here for completeness.)

[0169] Clock Enable (e.g., DDRCKE)—Out

[0170] Clock Enable high may activate and clock enable low deactivate internal clock signals, device input buffers, and output drivers within the memory chip. Taking clock enable low provides a Self Refresh operation. The enable may be synchronous for all cases. The enable may be maintained high throughout all read and write accesses. Memory chip input buffers, excluding CKE may be disabled during a Self Refresh.

[0171] DDR Chip Select (e.g., DDRCSn[7:0])—Out

[0172] All commands to the memory chip may be masked when the chip select signal is high. The signal may be considered part of a command code along with signals DDRRASn, DDRCASn, and DDRWEn.

[0173] Row Address Select (e.g., DDRRASn)—Out

[0174] The signal DDRRASn may be part of a command input signal. The signals DDRRASn, DDRCASn, DDRWEn, and DDRCSn generally define the command being sent to the memory chips.

[0175] Column Address Select (e.g., DDRCASn)—Out

[0176] The signal DDRCASn may be part of a command input signal. The signals DDRRASn, DDRCASn, DDRWEn, and DDRCSn generally define the command being sent to the memory chips.

[0177] Write Enable (e.g., DDRWEn)—Out

[0178] The signal DDRWEn may be part of a command input signals. The signals DDRRASn, DDRCASn, DDRWEn, and DDRCSn generally define the command being sent to the memory chips.

[0179] Bank Address [1:0] (e.g., DDRBA)—Out

[0180] The bank address signals may define to which one of the several banks, within the memory chip, an Active, Read, Write or Precharge command is being applied.

[0181] Address Bus [12:0] (e.g., DDRADRS)—Out

[0182] The address signals may provide to the memory chips the row address for Active commands, and column address and Auto Precharge bit for read/write commands, to select one location out of the memory array in the respective bank. Bit 10 may be sampled during a Precharge command to determine whether the Precharge applies to one bank (e.g., bit 10 low) or all banks (e.g., bit 10 high). If only one bank is to be precharged, the bank may be selected by the DDRBA bits. The address input may also provide the opcode during a Mode Register Set command with DDRBA determining which register may be loaded.

[0183] Data Input/Output Bus [X:0] (e.g., DDRDQ)—In/Out

[0184] A bidirectional data bus for the memories.

[0185] Data Strobe [X:0] (e.g., DDRDQS)—In/Out

[0186] Bidirectional bus for the data strobes. The memory chip may drive the strobes, edge-aligned with the data for reads. The DDR controller should drive the strobes, centered in the data for writes. One strobe per byte may be provided.

[0187] Data Mask [3:0] (e.g., DDRDM)—Out

[0188] Write data may be masked (not written) when the signal DM is sampled high along with the write data (e.g., DQ bus). The signal DM may be sampled on both edges of the signal DDRDQS. One mask per byte may be provided.

[0189] Voltage Reference (e.g., DDRVREF)—In

[0190] Provides the SSTL2 reference voltage. The signal DDRVREF should not be buffered.

[0191] DDR Flip-Flop in I/O (e.g., DDRFFINIO)—In

[0192] When the single clock rate signals (e.g., DDRCKE, DDRCSn, DDRRASn, DDRCASn, DDRWEn, DDRBA, and DDRADRS) to the DDR memories use a SSTL2 I/O buffer that includes a flip-flop, the signal DDRFFINIO may be tied high. When a standard SSTL2 I/O cell is used for the signals (without a flip-flop), the signal DDRFFINIO may be tied low. The DDR memory controller circuit may use the level of the signal to modify the length of a pipeline registers to compensate for the existence of absence of a flip-flop in the I/O buffers.

[0193] Referring to FIG. 7, a block diagram of a second embodiment of the peripheral controller circuit 110 is shown. The peripheral controller circuit 110 may be implemented as an off-chip memory controller circuit 110b. In the case of single data rate (SDR) or DDR SDRAMs, the peripheral circuit 120 may be implemented off-chip as a discrete memory device or circuit 120b. The external peripheral interface circuit 114 may be absent in the instant implementation. The port interface circuit 124 within the off-chip memory controller circuit 120b may be configured as described earlier. The resource circuit 126 may be configured as a synchronous dynamic random access memory (SDRAM) controller circuit or block 148 and a flash memory controller circuit or block 149. The peripheral circuit 120b may be configured as a dynamic random access memory (DRAM) circuit or block 150 and a flash memory circuit or block 151. Other memory technologies and corresponding controllers may be implemented to meet a criteria of a particular application.

[0194] Referring to FIG. 8, a block diagram of a third embodiment of the peripheral controller circuit 110 is shown. The peripheral controller circuit 110 may be implemented as a semaphore/mailbox controller circuit 110c. The semaphore/mailbox controller circuit 110c generally comprises the port interface circuit 124, a semaphore block or circuit 152 and a mailbox block or circuit 154. The semaphore block 152 and the mailbox block 154 generally support inter-processor communications and semaphore functions. The mailbox block 154 may include a simple set of control and status registers that may be used to communicate simple control and/or status functions between processors. The semaphore block 152 and the mailbox block 154 may be separate functions. However, since mailbox function may be used in multiprocessor environments the same as semaphore functions, both blocks 152 and 154 may be likely used together.

[0195] Referring to FIG. 9, a block diagram of a fourth embodiment of the peripheral controller circuit 110 is shown. The peripheral controller circuit 110 may be implemented as an on-chip memory controller circuit 110d. The on-chip memory controller circuit 110d generally comprises the port interface circuit 124, a memory controller circuit or block 156 and a memory circuit or block 158. In the instant embodiment, the external physical interface circuit 114 and the peripheral circuit 120 may be omitted. All memory storage functionality may be allocated to the on-chip memory controller circuit 110d itself.

[0196] Referring to FIG. 10, a block diagram of a fifth embodiment of the peripheral controller circuit 110 is shown. The peripheral controller circuit 110 may be implemented as a data transport circuit 110e. The data transport circuit 110e generally comprises the port interface circuit 124 and a transport layer block or circuit 160. The peripheral circuit 120 may be implemented as a physical layer block or circuit 120e. The physical layer block 120e may be implemented as a transceiver circuit within a communications channel 164. The transport layer block 160 generally provides framing and de-framing capabilities to the system 100 to allow transfers of data via the communications channel 164.

[0197] Referring to FIG. 11, a timing diagram of an example two burst read from the peripheral controller circuit 110 is shown. A line buffer circuit (e.g., 102a) may generate a set of read request signals 166 that may be provided to the multiplexer circuit 108. The multiplexer circuit 108 may route the read request signals 168 to the peripheral controller circuit 110. The peripheral controller circuit 110 may service the read request by providing data in two bursts 170 for each request back to the requesting line buffer circuit 102a.

[0198] Referring to FIG. 12, a timing diagram of an example four burst read from the peripheral controller circuit 110 is shown. A line buffer circuit (e.g., 102a) may request data at several address (e.g., A-D) and provide an associated 5-bit tag value (e.g., 1-TAG). The arbiter circuit 106 may generate an 8-bit tag for the address A read request. The peripheral controller circuit 110 may respond to the read request by transferring data for addresses A, B, C and D along with the tag value 1_TAG to the line buffer circuits 102a-d in a burst of four consecutive transfers 172.

[0199] Referring to FIG. 13, a timing diagram of an example two burst write to the peripheral controller circuit 110 is shown. A line buffer circuit (e.g., 102a) may request 174 writing data to two addresses (e.g., addresses A and B). When the peripheral controller circuit 110 is ready (e.g., MC_REQ_ACK=high), the arbiter circuit 106 may first write two data values (e.g., A1 and A2) to the peripheral controller circuit 110 at address A in a two burst transfer 174. When the peripheral controller circuit 110 may be ready for the data at the address B, the arbiter circuit 106 may write two additional data values (e.g., B1 and B2) to the peripheral controller circuit 110 at the address B in another two burst transfer 174.

[0200] Referring to FIG. 14, a timing diagram of an example four burst write to the peripheral controller circuit 110 is shown. The arbiter circuit 106 may transfer data values (e.g., A1-A4) to the peripheral controller circuit 110 in four consecutive transfers 178 under a tag value (e.g., TAG_A). Four additional transfers 178 of data values (e.g., B1-B4) under another tag value (e.g., TAG_B) may happen immediately after the data value A4 has been written.

[0201] Referring to FIG. 15, a timing diagram of an example read from the DDR memory circuit 120a (FIG. 6) is shown. The command buffer and control circuit 136 may receive a read request 180 at an address (e.g., address 10). The state machine 142 and the programmable physical timing circuit 144 may generate a set of DDR command signals 182 to the DDR memory circuit 120a to service the read request. The DDR memory circuit 120a may respond to the DDR commands by transferring 184 data from the addresses 10-1C (hexadecimal) to the read buffer circuit 140. The DDR memory controller circuit 110a may then transfer the requested data, and additional data, to the line buffer circuits 102a-d in two burst transfers 186.

[0202] The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation. Additionally, inverters may be added to change a particular polarity of the signals. As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration.

[0203] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims

1. A circuit comprising: a command buffer configured to (i) buffer a plurality of read commands received by said circuit, wherein each said read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from said circuit in response to servicing a particular read command of said read commands, said tag signal having a particular port value of said port values and a particular identification value of said identification values as determined by said particular read command; and a read buffer configured to transmit a read signal within a plurality of first transfers from said circuit in response to servicing said particular read command.

2. The circuit according to claim 1, further comprising a controller circuit configured to control at least one of a memory circuit, a semaphore block and a mailbox block for reading said read signal.

3. The circuit according to claim 2, wherein said controller circuit is couplable to a communication channel configured to generate said read signal.

4. The circuit according to claim 1, further comprising a write queue configured to receive a write signal within a plurality of second transfers.

5. The circuit according to claim 4, further comprising a controller circuit configured to control at least one block of a memory block, a semaphore block and a mailbox block for writing said write signal.

6. The circuit according to claim 4, wherein said controller circuit is further configured to transmit said write signal from said circuit within a plurality of third transfers.

7. The circuit according to claim 1, further comprising a state machine configured to control reads and writes to a memory circuit storing said read signal.

8. The circuit according to claim 7, further comprising a timing circuit configured to control timing of a plurality of control signals to said memory circuit.

9. The circuit according to claim 8, further comprising an address decoder configured to transfer an address signal to said state machine in response to said each said read command.

10. The circuit according to claim 9, further comprising a plurality of registers configured to store protocol information for communicating with said memory circuit.

11. A method of operating a circuit, comprising the steps of: (A) buffering a plurality of read commands received by said circuit, wherein each said read command has one of a plurality of port values and one of a plurality of identification values; (B) transmitting a tag signal from said circuit in response to servicing a particular read command of said read commands, said tag signal having a particular port value of said port values and a particular identification value of said identification values as determined by said particular read command; and (C) transmitting a read signal within a plurality of first transfers from said circuit in response to servicing said particular read command.

12. The method according to claim 11, further comprising the step of buffering said read signal received by said circuit within a plurality of second transfers prior to transmitting said read signal within said first transfers.

13. The method according to claim 11, further comprising the step of storing said read signal in said circuit prior to transmitting said read signal within said first transfers.

14. The method according to claim 11, further comprising the step of transmitting a valid signal from said circuit in response to servicing said particular read command, said valid signal locating said read signal within said plurality of transfers.

15. The method according to claim 11, further comprising the step of transmitting an acknowledge signal from said circuit when ready to buffer a new read command to said read commands in response to receiving a request signal.

16. The method according to claim 11, further comprising the step of queuing a write signal received by said circuit within a plurality of second transfers.

17. The method according to claim 16, further comprising the step of extracting said write signal from said second transfers in response to a valid signal locating said write signal within said second transfers.

18. The method according to claim 16, further comprising the step of storing said write signal in said circuit after queuing said write signal.

19. The method-according to claim 16, further comprising the step of transmitting said write signal from said circuit within a plurality of third transfers.

20. A circuit comprising, means for buffering a plurality of read commands received by said circuit, wherein each said read command has one of a plurality of port values and one of a plurality of identification values; means for transmitting a tag signal from said circuit in response to servicing a particular read command of said read commands, said tag signal having a particular port value of said port values and a particular identification value of said identification values as determined by said particular read command; and means for transmitting a read signal within a plurality of first transfers from said circuit in response to servicing said particular read command.

21. A system comprising: a plurality of controller circuits each configured to store data; a plurality of line buffer circuits each configured to transfer said data between an accessed one of said controller circuits and one of a plurality of first busses; and a first arbiter circuit configured to control access to said controller circuits by said line buffer circuits.

22. The system according to claim 21, further comprising a second arbiter circuit configured to control access at least one of said controller circuits by said line buffer circuits.

23. The system according to claim 22, wherein at least two of said line buffer circuits access at least two of said controller circuits substantially simultaneously.

24. The system according to claim 21, further comprising a circuit configured to transfer configuration data between a second bus and (i) said line buffer circuits, (ii) said first arbiter circuit and (iii) said controller circuits.

25. A system comprising: a plurality of controller circuits each configured to store data; a plurality of line buffer circuits each configured to transfer said data between an accessed one of said controller circuits and one of a plurality of first busses; and a plurality of arbiter circuits each configured to control access to at least one of said controller circuits by said line buffer circuits.

26. The system according to claim 25, wherein at least two of said line buffer circuits access at least two of said controller circuits substantially simultaneously.

27. The system according to claim 25, wherein access to at least two of said controller circuits is arbitrated by one of said arbiter circuits.

28. The system according to claim 25, further comprising a circuit configured to transfer configuration data between a second bus and (i) said line buffer circuits, (ii) arbiter circuits and (iii) said controller circuits.