Amorphous silicon TFT

Abstract

An amorphous silicon thin-film transistor as a switching element for a thin-film transistor liquid crystal display, having improved characteristics by making better an ohmic contact layer and an active layer, and a method of fabricating the same are provided. A wide energy-band gap .mu.c-Si(:Cl) fabricated using a mixed gas including SiH.sub.2 Cl.sub.2 is used as the ohmic contact layer, so that yield and productivity can be improved. The active layer is formed of .mu.c-Si:H(:Cl) with low hydrogen content and high stability. Off-current during illumination is sharply decreased, to thereby remarkably reduce leakage current when illumination is performed by backlighting.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a thin-film transistor (TFT), and more particularly, to an amorphous silicon TFT wherein an ohmic contact layer and active layer are improved and to a fabricating method thereof.

Thin-film transistors generally include an active layer of amorphous silicon, polysilicon or cadmium-selenium and have been widely employed as the pixel-driving elements of a liquid crystal display device. Particularly, a hydrogenated amorphous silicon (a-Si:H) TFT is advantageous to the production of large-screen displays and facilitates mass production. When employing the a-Si:H layer, the main concerns are enhancing field-effect mobility while maintaining a low off-current characteristic. Here, it should be noted that the high photo-conductivity properties of hydrogenated amorphous silicon generate high levels of leakage current under backlight illumination, and if a high-intensity backlight is adopted, as in the case of projection-type displays, the leakage current becomes a serious problem. Thus, reducing the photo leakage-current of an a-Si:H TFT is an essential task to obtain a high quality TFT-LCD. Though the leakage current can be lowered by reducing the thickness of an undoped a-Si:H layer, unfortunately, this also decreases field-effect mobility.

Recently, however, an n.sup.+ -type microcrystalline silicon (n.sup.+ .mu.c-Si) having a wide energy-band gap has been developed using SiH.sub.2 Cl.sub.2 gas and applied to fabricate an a-Si:H TFT having low leakage current. In contrast to n.sup.+ a-Si:H, n.sup.+ microcrystalline silicon has a relatively low sheet resistance and high conductivity, so that hole current is effectively blocked during an off-operation of the TFT and on-current is increased.

Meanwhile, the structure of the amorphous silicon TFT can be roughly classified into staggered and coplanar types according to the location of a patterned active layer. In the case of the staggered type, a gate electrode and source/drain electrode are separated by an interposed semiconductor layer, differently from the coplanar type in which the electrodes are all formed in the same side of a semiconductor layer. Here, the most widely used amorphous silicon TFT is the inverse-staggered type.

FIG. 1 is a cross-sectional view of a conventional inverse-staggered type amorphous silicon TFT.

As shown in FIG. 1, gate 11 consisting of a metal pattern of chromium or aluminum is formed on insulating substrate 10, and gate insulating layer 12 made of nitride is formed on the whole surface of the resultant. On gate insulating layer 12, the channel of the TFT is formed of a patterned layer of hydrogenated amorphous silicon, as active layer 13, and source/drain 15 is formed on both sides of the active layer. Then, to improve ohmic characteristics, ohmic contact layer 14 doped with a high concentration of n-type impurities is formed between active layer 13 and source/drain electrode 15. Here, the n.sup.+ .mu.c-Si used as ohmic contact layer 14 is formed by depositing H.sub.2 /SiH.sub.4 gas (mixed with a ratio of 10:1) or SiF.sub.4 /H.sub.2 /SiH.sub.4 gas using a plasma-enhanced chemical vapor deposition (PECVD) method.

However, if H.sub.2 /SiH.sub.4 gas is used for depositing the conventional n.sup.+ .mu.c-Si layer, the deposition rate is remarkably decreased and particles are generated, due to the etching effect of hydrogen. On the other hand, if SiF.sub.4 gas is used in the deposition, the previously deposited a-Si:H layer (active layer 13) is damaged by ions which are accelerated by SiF.sub.4 decomposed at a high RF power.

SUMMARY OF THE INVENTION

To solve the above problems, it is an object of the present invention to provide an amorphous silicon TFT in which an ohmic contact layer doped with a high concentration of impurities is formed of chlorine-containing microcrystalline silicon (.mu.c-Si(:Cl)), to increase the deposition rate and prevent damage to the active layer and the generation of particles during the deposition process, and a fabricating method thereof.

It is another object of the present invention to provide an amorphous silicon TFT in which an active layer of the amorphous silicon TFT is formed of chlorine-containing hydrogenated amorphous silicon (a-Si:H(:Cl)) with low hydrogen content and high stability, to increase the quality of an amorphous silicon TFT and a fabricating method thereof.

To achieve the above first object, there is provided an amorphous silicon TFT comprising: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; an active layer made of hydrogenated amorphous silicon formed on the gate insulating layer; a source/drain electrode formed on either side of the gate electrode; and an ohmic contact layer made of of chlorine-containing microcrystalline silicon (.mu.c-Si(:Cl)) interposed between the active layer and the source/drain electrode.

To achieve another aspect of the first object, there is provided a method of fabricating an amorphous silicon TFT in which a gate electrode is formed on an insulating substrate, comprising the step of forming an ohmic contact layer of .mu.c-Si(:Cl) by a plasma-enhanced chemical vapor deposition method using a SiH.sub.4 /H.sub.2 /PH.sub.3 gas mixture including SiH.sub.2 Cl.sub.2.

To achieve the above second object, there is provided an amorphous silicon TFT comprising: an insulating substrate; a gate electrode formed on the insulating substrate; a source/drain electrode formed on either side of the gate electrode; an active layer made of chlorine-containing hydrogenated amorphous silicon (a-Si:H(:Cl)) having a chlorine content of 0.1.noteq.10.sup.6 ppm; and an ohmic contact layer interposed between the channel layer and the source/drain electrode.

To achieve another aspect of the second object, there is provided a method of fabricating an amorphous silicon TFT comprising the step of forming an active layer of a-Si:H(:Cl) by a plasma-enhanced chemical vapor deposition method using a chlorine-containing gas mixture.

According to the first preferred embodiment of the present invention, the ohmic contact layer of the amorphous silicon TFT is formed of .mu.c-Si(:Cl) using a mixed gas including SiH.sub.2 Cl.sub.2, thereby increasing the deposition rate and the quality of a-Si TFT with low RF power. Thus, in fabrication of TFT-LCD, the yield of the TFT and productivity can be increased.

According to the second preferred embodiment of the present invention, the active layer of the amorphous silicon TFT is formed of a-Si:H(:Cl) with low hydrogen content and high stability, thereby lowering off-current to about 1/10 of the conventional TFT. Particularly, the off-current decreases to about 1/100 of the conventional TFT during the light illumination, so that the leakage current experienced during backlight illumination can be remarkably reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a cross-sectional view of a conventional inverse-staggered type amorphous silicon TFT;

FIG. 2 is a cross-sectional view of an inverse-staggered type amorphous silicon TFT fabricated according to the first preferred embodiment of the present invention;

FIG. 3 is a graph showing the conductivity-vs-temperature characteristics of a n.sup.+ .mu.c-Si(:Cl) in the TFT fabricated according to the first preferred embodiment of the present invention;

FIG. 4 is a graph showing the current-vs-voltage characteristics of the TFT according to the first preferred embodiment of the present invention;

FIG. 5 is a graph showing the field effect mobility of the TFT according to the first preferred embodiment of the present invention;

FIG. 6 is a graph showing the output characteristics of the TFT according to the first preferred embodiment of the present invention;

FIG. 7 is a cross-sectional view of an inverse-staggered type amorphous silicon TFT according to the second preferred embodiment of the present invention;

FIGS. 8A and 8B are graphs comparing the current-vs-voltage characteristics of a TFT fabricated according to the second preferred embodiment of the present invention and the conventional TFT;

FIG. 9 is a graph showing the field effect mobility of the TFT according to the second preferred embodiment of the present invention;

FIG. 10 is a graph showing the output characteristics of the TFT according to the second preferred embodiment of the present invention;

FIG. 11 is a graph showing the chlorine concentration in the active layer of the TFT according to the second preferred embodiment of the present invention;

FIG. 12 is a graph showing the photo- and dark-conductivity of the active layer in the TFT according to the second preferred embodiment of the present invention;

FIG. 13 is a graph showing the photo-conductivity degradation characteristics in the active layer of the TFT according to the second preferred embodiment of the present invention; and

FIGS. 14A and 14B are graphs comparing current-vs-voltage characteristics of a TFT fabricated according to the second preferred embodiment of the present invention and the conventional TFT, under the dark and illuminating conditions.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1

In FIG. 2, which is a cross-sectional view of an inverse-staggered type amorphous silicon TFT according to a preferred embodiment of the present invention, the same reference numerals as those of FIG. 1 represent corresponding portions thereof, and thus their description will be omitted.

As shown in FIG. 2, SiN.sub.x layer 12 having a thickness of about 0.3 .mu.m and undoped a-Si:H layer 13 having a thickness of about 0.15 .mu.m are deposited on glass substrate 10 on which gate 11 made of a metal pattern, such as chromium, is formed using the PECVD method. The a-Si:H layer 13 to be channel is deposited at 220.degree. C. using a SiH.sub.4 /H.sub.2 gas, and SiN.sub.x layer 12 as a gate insulating layer is deposited at 330.degree. C. using SiH.sub.4 /NH.sub.3 gas. Here, gate insulating layer 12 adopts a stacked structure such a SiO.sub.2 /SiN or Al.sub.2 O.sub.3 /SiN layer, which provides good insulating characteristics, instead of a monolayer.

Also, n.sup.+ .mu.c-Si(:Cl) layer 24 as an ohmic contact layer with about 0.05 .mu.m thickness is interposed between Si:H layer 13 and a source/drain electrode 15. The ohmic contact layer 24 and the part of a-Si:H layer 13 within the channel region is etched using CF.sub.4 plasma. Here, n.sup.30 .mu.c-Si(:Cl) layer 24 is deposited using the PECVD method with SiH.sub.4 /H.sub.2 /PH.sub.3 gas including SiH.sub.2 Cl.sub.2.

FIG. 3 is a graph showing the conductivity-vs-temperature characteristics of an n.sup.+ .mu.c-Si(:Cl) layer fabricated through the above steps, in which it can be seen that the conductivity at room temperature is about 1.5 S/cm, and the conductivity activation energy is about 29 meV.

FIGS. 4-6 show various electrical characteristics of an amorphous silicon TFT adopting n.sup.+ .mu.c-Si(:Cl) layer 24, which is fabricated as an ohmic contact layer using SiH.sub.2 Cl.sub.2 /SiH.sub.4 gas, according to the first preferred embodiment. FIG. 4 shows the current-vs-voltage characteristics. Here, the subthreshold slope is about 0.48V per decade and the on/off current ratio is greater than 10.sup.6. From FIG. 5, which shows the field effect mobility of the above TFT, it can be seen that the threshold voltage is about 2.1 V and field effect mobility is 0.58 cm.sup.2 /Vs. FIG. 6 shows TFT output characteristics, with the drain current being nearly saturated at 2.2 .mu.A given a gate voltage of 20 V. The n.sup.+ .mu.c-Si(:Cl) TFT fabricated using SiH.sub.2 Cl.sub.2 /SiH.sub.4 gas provides good characteristics as the ohmic layer of a-Si:H TFT.

As described above, according to the first preferred embodiment, the wide band gap n.sup.+ .mu.c-Si is fabricated as the ohmic contact layer using SiH.sub.2 Cl.sub.2 SiH.sub.4 gas, which has less hydrogen gas than the conventional n.sup.+ .mu.c-Si. As a result, the deposition rate and the yield both increase, and the particle generation rate can be remarkably reduced compared with the conventional n.sup.+ .mu.c-Si. Also, differently from SiF.sub.4 which damages the channel region by being decomposed at higher RF power, SiH.sub.2 Cl.sub.2 can prevent such channel damage.

Embodiment 2

The second preferred embodiment relates to a TFT adopting a-Si:H(:Cl) as an active layer of the amorphous silicon TFT.

FIG. 7 shows the cross-sectional view of an inverse-staggered type amorphous silicon TFT fabricated according to the second preferred embodiment of the present invention. Here, as in the first embodiment, a metal layer such as chromium or aluminum is deposited and patterned as gate electrode 11 atop insulating substrate 10, and then a silicon nitride as gate insulating layer 12 and a-Si:H(:Cl) as active layer 23 are deposited by a plasma enhanced chemical vapor deposition. Thereafter, ohmic contact layer 14 is formed of n.sup.+ Si or n.sup.+ .mu.c-Si and then a source/drain 15 is formed using aluminum or chromium.

Also, the TFT may be fabricated with an etching stopper type structure using an etching stopper 25 so as to thin a-Si:H(:Cl) layer 23. Also, to increase the yield in mass production, a stacked structure such as SiO.sub.2,/SiN or Al.sub.2 O.sub.3 /SiN may be adopted instead of the single gate insulating layer 12.

Generally, since amorphous silicon is used as active layer 23 in the amorphous silicon TFT, the amorphous silicon influences the characteristics of the TFT. Here, the amorphous silicon is deposited using SiH.sub.4 or SiH.sub.4 /H.sub.2 gas which is decomposed via a glow discharging process with PECVD equipment.

According to the second preferred embodiment, when a gas including chlorine, such as SiH.sub.2 Cl.sub.2, SiCl.sub.4 or SiHCl.sub.3, is used for fabricating the amorphous silicon, Si--H and a Si--Si with weak bond energies are removed during the deposition process by the etching effect of the chlorine incorporated into the plasma, thereby providing high-quality amorphous silicon to improve the electrical characteristics of the TFT.

FIGS. 8A and 8B compare the current-vs-voltage characteristics of the TFT fabricated according to the second preferred embodiment of the present invention, with those of the conventional TFT, wherein the former (FIG. 8A) comprises an active layer including chlorine and the latter (FIG. 8B) comprises an active layer without chlorine. From the transfer curves shown in FIGS. 8A and 8B, it can be seen that the off-current of the amorphous silicon TFT according to the present invention decreases to about 1/10 that of the conventional amorphous silicon TFT, since the incorporated chlorine lowers the conductivity of the amorphous silicon. Also, the subthreshold slope of the a-Si:H(:Cl) TFT is about 0.36V per decade and the on/off current ratio is greater than 10.sup.6. Here, the drain voltage is 5V.

FIG. 9 is a graph showing the field effect mobility of the above TFT. The threshold voltage (V.sub.TH) and field effect mobility (.mu..sub.FE) calculated from .sqroot.I.sub.D =�.sup..mu..sub.FE (W/L)C.sub.i (V.sub.G -V.sub.TH)V.sub.D !.sup.1/2 are about 1.8 V and 0.72 cm.sub.2 Ns, respectively, while, the field effect mobility of the TFT fabricated with the amorphous silicon without chlorine according to the same process is 0.70 cm.sup.2 /Vs. That is, field effect mobility is not influenced by the incorporated chlorine.

FIG. 10 shows the output characteristics of an a-Si:H(:Cl) TFT in which chlorine of about 7.times.10.sup.18 cm.sup.-3 is incorporated into an active layer which is fabricated using a mixed gas including SiH.sub.2 Cl.sub.2. As shown in FIG. 10, the drain current is saturated at 2.8 .mu.A given a gate voltage of 20V, with the width-to-length (W/L) ratio of the TFT being 60 .mu.m/30 .mu.m.

FIG. 11 is a graph showing the chlorine concentration in the active layer of the TFT fabricated using SiH.sub.2 Cl.sub.2 /SiH.sub.4 gas according to the second preferred embodiment of the present invention, measured using a secondary ion mass spectrometer. Here, a solid line, a dot-and-dash line, and a dotted line represent the chlorine concentration when the ratio of SiH.sub.2 Cl.sub.2 to SiH.sub.4 is 0.2 (i.e., 4.times.10.sup.19 cm.sup.-3)0.1 (i.e., 7.times.10.sup.18 cm.sup.31 3) and zero, respectively. Thus, it is shown that the chlorine concentration in a-Si:H(:Cl) of the TFT increases together with the increase of the SiH.sub.2 Cl.sub.2 -to-SiH.sub.4 ratio. Also, it can be seen that chlorine is still detected even when the ratio is zero. This is because chlorine is getting removed from a chamber wall during the deposition process.

FIG. 12 shows the photo- and dark-conductivity of the a-Si:H(:Cl) active layer in the TFT fabricated according to the second preferred embodiment of the present invention, in accordance with the ratio of SiH.sub.2 Cl.sub.2 to SiH.sub.4. Here, the photo-conductivity is measured under the condition of 100 mW/cm.sup.2, that is, air mass 1.0. As shown in FIG. 12, the photo- and dark-conductivity decreases as the ratio of SiH.sub.2 Cl.sub.2 to SiH.sub.4 increases. This is because chlorine included in the amorphous silicon shifts a Fermi level toward a valance band E.sub.v, thereby lowering the photo- and dark-conductivity.

FIG. 13 shows the photo-conductivity degradation characteristics in the amorphous silicon fabricated according to the ratio of SiH.sub.2 Cl.sub.2 to SiH.sub.4 when light is continuously applied thereto. Here, the plots designated by (a), (b), (c), (d) and (e) represent the photo-conductivity degradation characteristics when the SiH.sub.2 Cl.sub.2 -to-SiH.sub.4 ratio is zero, 0.07, 0.1, 0.4 and 1.0, respectively. As shown in FIG. 13, a degradation characteristic determining constant .gamma. is the least for plot (c). Here, .gamma. is calculated according to .sigma..sub.ph .varies.t.sup.-.gamma. where .sigma..sub.ph represents photo-conductivity and t represents exposure time, i.e., .gamma.=0.045. Thus, the amorphous silicon including chlorine shows very stable photo-conductivity under light illumination.

FIGS. 14A and 14B compare the transfer characteristics during the photo- and dark-illumination in the amorphous silicon TFTs with 7.times.10.sup.18 cm.sup.-3 Cl and without chlorine. Here, the source/drain/channel is illuminated with 10 klx of light. As shown in the comparison, when light is applied to the amorphous silicon TFT fabricated according to the second preferred embodiment, the off-current is about 1/100 of the conventional amorphous silicon TFT. Here, too, the drain voltage is 5V.

Therefore, the amorphous silicon TFT of the preferred embodiment decreases the leakage current without decreasing the threshold voltage. Therefore, by applying the above-described TFT to a liquid crystal display as a switching element, screen quality can be improved due to the reduction in leakage current.

As described above, according to the second preferred embodiment of the present invention, the active layer of the amorphous silicon TFT is formed of a-Si:H(:Cl) with low hydrogen content and high stability, thereby decreasing the off-current to about 1/10 of the conventional TFT. Particularly, since the off-current during the light illumination is about 1/100 of the conventional TFT, leakage current is remarkably reduced even when illumination is performed by backlighting.

Claims

1. An amorphous silicon TFT comprising:

an insulating substrate;

a gate electrode formed on said insulating substrate;

a gate insulating layer formed on said gate electrode;

an active layer made of hydrogenated amorphous silicon and not containing chlorine formed on said insulating layer;

a source/drain electrode formed over either side of said gate electrode; and

an ohmic contact layer made of chlorine-containing microcrystalline silicon interposed between said active layer and said source/drain electrode.

2. An amorphous silicon TFT comprising:

an insulating substrate;

a gate electrode formed on said insulating substrate;

a gate insulating laver formed on said gate electrode;

a source/drain electrode formed over either side of said gate electrode;

an active layer made of chlorine-containing hydrogenated amorphous silicon (a-Si:H(:Cl)) having a chlorine content of over 0.1 ppm formed on said gate insulating layer; and

an ohmic contact layer interposed between said active layer and said source/drain electrode.

3. An amorphous silicon TFT as claimed in claim 1, wherein said gate insulating layer is made of a silicon nitride layer.

4. An amorphous silicon TFT as claimed in claim 1, wherein said ohmic contact layer is doped with N-type impurities.

5. An amorphous silicon TFT as claimed in claim 2, wherein said gate insulating layer is made of a silicon nitride layer.

6. An amorphous silicon TFT as claimed in claim 2, wherein said ohmic contact layer is doped with N-type impurities.

7. An amorphous silicon TFT as claimed in claim 2, wherein the field effect mobility of said active layer is 0.4-0.6 cm.sup.2 N-sec.

8. An amorphous silicon TFT as claimed in claim 7, wherein the field effect mobility of said active layer is not substantially influenced by the chlorine content of said active layer.

9. An amorphous TFT comprising:

an insulating substrate;

a gate electrode formed on said insulating substrate;

a gate insulating layer formed on said gate electrode;

an active layer including a means for reducing off-current and conductivity, said means for reducing being made of chlorine-containing hydrogenated amorphous silicon (a-Si:H(:Cl)) having a chlorine content of over 0.1 ppm formed on said gate insulating layer;

a source/drain electrode formed over either side of said gate electrode; and

an ohmic contact layer interposed between said active layer and said source/drain electrode.

10. An amorphous silicon TFT as claimed in claim 2, wherein said amorphous silicon is non-crystallized.