Patent Application
20250219604
The present application claims priority under 35 U.S.C. ยง 119(a) to Korean Patent Application No. 10-2024-0000354, filed on Jan. 2, 2024, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
Various embodiments generally relate to an integrated circuit technology, and more particularly, to an amplification circuit, and a receiver circuit and a semiconductor apparatus using the amplification circuit.
An electronic device includes many electronic components. Among the electronic components, a computer system may include many semiconductor apparatuses manufactured by using semiconductor devices. The semiconductor apparatuses that constitute the computer system may communicate with each other by transmitting and receiving clocks and data. The semiconductor apparatuses may each include a receiver circuit and receive a signal from an external apparatus or receive a signal between circuits within the semiconductor apparatus. In general, the receiver circuit may include an amplifier that receives a pair of differential signals or a single-ended signal by performing a differential amplification operation. The amplifier may receive a signal by differentially amplifying a differential signal, and may receive a signal by differentially amplifying a single-ended signal and a reference voltage. As a semiconductor manufacturing process becomes fine, a parasitic capacitor may be formed between semiconductor devices that constitute the amplifier of the receiver circuit. The parasitic capacitors may generate kickback noise in nodes of the amplifier based on a change in the voltage level of an input signal of the amplifier, and may hinder the amplifier from performing an accurate sensing amplification operation by reducing a sensing margin of the amplifier.
In an embodiment, an amplification circuit may include a prechage control circuit and an amplifier. The precharge control circuit may be configured to generate a precharge control signal based on a voltage level of a reference voltage. The amplifier may be configured to differentially amplify an input signal and the reference voltage to change voltage levels of a positive output node and a negative output node when a clock signal has a first logic level, to precharge the positive output node and the negative output node when the clock signal has a second logic level, and to adjust a current driving force that precharges the positive output node and the negative output node based on the precharge control signal.
In an embodiment, an amplification circuit may include an enable circuit, an input circuit, and a precharge circuit. The enable circuit may be configured to apply a first voltage to a common node when a clock signal has a first logic level. The input circuit may be coupled between the common node, and a positive output node and a negative output node. The input circuit may be configured to change voltage levels of the positive output node and the negative output node based on an input signal and a reference voltage. The precharge circuit may be configured to precharge the positive output node and the negative output node to a voltage level of a second voltage when the clock signal has a second logic level and to adjust a current current driving force that precharges the positive output node and the negative output node based on a voltage level of the reference voltage.
In an embodiment, a receiver circuit may include a first amplifier and a second amplifier. The first amplifier may be configured to differentially amplify an input signal and a reference voltage to generate a first amplification signal when a clock signal has a first logic level, to precharge the first amplification signal when the clock signal has a second logic level, and to adjust a current driving force that precharges the first amplification signal based on a voltage level of the reference voltage. The second amplifier may be configured to differentially amplify the input signal and the reference voltage to generate a second amplification signal when the clock signal has the second logic level, to precharge the second amplification signal when the clock signal has the first logic level, and to adjust a current driving force that precharges the second amplification signal based on the voltage level of the reference voltage.
The amplification circuit 100 may include an amplifier 110 and a precharge control circuit 120. In an embodiment, the amplifier 110 may include a precharge driver 113, a differential circuit 112, and an enable circuit 111. The amplifier 110 may receive the first clock signal CLKB, the input signal IN, and the reference voltage VREF. The amplifier 110 may generate the amplification signal AOUT by differentially amplifying the input signal IN and the reference voltage VREF based on the logic level of the first clock signal CLKB. When the first clock signal CLKB has a first logic level, the amplifier 110 may generate the amplification signal AOUT by differentially amplifying the input signal IN and the reference voltage VREF. The amplifier 110 may generate the amplification signal AOUT and the complementary amplification signal AOUTB by changing the voltage levels of a positive output node OP11 and a negative output node ON11 based on the input signal IN and the reference voltage VREF. The amplification signal AOUT may be output from the positive output node OP11. The complementary amplification signal AOUTB may be output from the negative output node ON11. When the first clock signal CLKB has a second logic level, the amplifier 110 may precharge the amplification signal AOUT without differentially amplifying the input signal IN and the reference voltage VREF. When the first clock signal CLKB has the second logic level, the amplifier 110 may precharge the positive output node OP11 and the negative output node ON11. The amplifier 110 may adjust a current driving force that precharges the amplification signal AOUT and the complementary amplification signal AOUTB and/or the positive output node OP11 and the negative output node ON11, based on the voltage level of the reference voltage VREF. For example, the amplifier 110 may be a P type amplifier. In an embodiment a P type amplifier may include a differential circuit including PMOS transistors. For example, the amplifier 110 may include a differential circuit 112 including PMOS (p-channel metal-oxide semiconductor (pMOS)) transistors T12 and T13. When the reference voltage VREF has a higher voltage level than a threshold value, the amplifier 110 may increase a current driving force that precharges the positive output node OP11 and the negative output node ON11. In an embodiment, when the reference voltage VREF has a higher voltage level than the threshold value, an amount of current flowing from the positive output node OP11 and the negative output node ON11 may be increased. When the reference voltage VREF has a lower voltage level than the threshold value, the amplifier 110 may decrease the current driving force that precharges the positive output node OP11 and the negative output node ON11. In an embodiment, when the reference voltage VREF has a lower voltage level than the threshold value, an amount of current flowing from the positive output node OP11 and the negative output node ON11 may be decreased. The amplifier 110 may adjust the current driving force that precharges the positive output node OP11 and the negative output node ON11 by receiving a precharge control signal KBC.
The precharge control circuit 120 may generate the precharge control signal KBC by sensing the voltage level of the reference voltage VREF. The precharge control circuit 120 may generate the precharge control signal KBC by sensing the voltage level of the reference voltage VREF in various ways. The precharge control circuit 120 may receive a reference voltage setting signal RS<0:n>, and may generate the precharge control signal KBC by sensing the logic value of the reference voltage setting signal RS<0:n>. In this case, n may be an integer equal to or greater than 1. The reference voltage setting signal RS<0:n> may be a signal having information with regard to the voltage level of the reference voltage VREF. A semiconductor apparatus including the amplification circuit 100 may include a reference voltage generation circuit that generates the reference voltage VREF. The reference voltage generation circuit may generate a reference voltage having a voltage level corresponding to the logic value of the reference voltage setting signal RS<0:n>. The reference voltage setting signal RS<0:n> may be a signal that is provided by an external apparatus of the semiconductor apparatus, and may be information that has been stored in a register within the semiconductor apparatus. The precharge control circuit 120 may compare the logic value of the reference voltage setting signal RS<0:n> and a threshold value. For example, as the logic value of the reference voltage setting signal RS<0:n> is increased, the reference voltage VREF may have a higher voltage level. When the logic value of the reference voltage setting signal RS<0:n> is greater than the threshold value (i.e., when the reference voltage VREF has a higher voltage level than the threshold value), the precharge control circuit 120 may enable the precharge control signal KBC. When the logic value of the reference voltage setting signal RS<0:n> is smaller than the threshold value (i.e., when the reference voltage VREF has a lower voltage level than the threshold value), the precharge control circuit 120 may disable the precharge control signal KBC. In an embodiment, the precharge control circuit 120 may receive the reference voltage VREF, and may be modified to generate the precharge control signal KBC by sensing the voltage level itself of the reference voltage VREF. The precharge control circuit 120 may generate the precharge control signal KBC by directly comparing the voltage level of the reference voltage VREF and the threshold value.
The amplifier 110 may include an enable circuit 111, a differential circuit 112, and a precharge driver 113. The enable circuit 111 may be coupled between a terminal to which the first voltage VH is supplied and a common node CN. The enable circuit 111 may receive the first clock signal CLKB, and may apply the first voltage VH to the common node CN based on the first clock signal CLKB. When the first clock signal CLKB has a first logic level, the enable circuit 111 may apply the first voltage VH to the common node CN. When the first clock signal CLKB has a second logic level, the enable circuit 111 might not apply the first voltage VH to the common node CN. For example, the first logic level may be a logic low level, and the second logic level may be a logic high level.
The differential circuit 112 may be coupled between the common node CN, and the positive output node OP11 and the negative output node ON11. The differential circuit 112 may receive the input signal IN and the reference voltage VREF, and may change the voltage levels of the positive output node OP11 and the negative output node ON11 based on the input signal IN and the reference voltage VREF. The differential circuit 112 may change the voltage level of the negative output node ON11 based on the input signal IN, and may change the voltage level of the positive output node OP11 based on the reference voltage VREF. For example, when the input signal IN has a higher voltage level than the reference voltage VREF, the differential circuit 112 may raise the voltage level of the positive output node OP11 by increasing the amount of current that flows from the common node CN to the positive output node OP11. As the voltage level of the positive output node OP11 rises, the amplification signal AOUT having a logic high level may be output through the positive output node OP11, and the complementary amplification signal AOUTB having a logic low level may be output through the negative output node ON11. When the input signal IN has a lower voltage level than the reference voltage VREF, the differential circuit 112 may raise the voltage level of the negative output node ON11 by increasing the amount of current that flows from the common node CN to the negative output node ON11.
As the voltage level of the negative output node ON11 rises, the amplification signal AOUT having a logic low level may be output through the positive output node OP11, and the complementary amplification signal AOUTB having a logic high level may be output through the negative output node ON11.
The precharge driver 113 may be coupled between the positive output node OP11 and the negative output node ON11, and a terminal to which the second voltage VL is supplied. The precharge driver 113 may receive the first clock signal CLKB and the precharge control signal KBC, and may precharge the positive output node OP11 and the negative output node ON11 to the voltage level of the second voltage VL based on the first clock signal CLKB and the precharge control signal KBC. The precharge driver 113 may precharge the positive output node OP11 and the negative output node ON11 to the voltage level of the second voltage VL based on the first clock signal CLKB, and may adjust a current driving force that precharges the amplification signal AOUT and the complementary amplification signal AOUTB and/or a current driving force that drives the positive output node OP11 and the negative output node ON11 to the voltage level of the second voltage VL based on the precharge control signal KBC. When the precharge control signal KBC is enabled, the precharge driver 113 may increase the current driving force that drives the amplification signal AOUT and the complementary amplification signal AOUTB and/or the current driving force that precharges the positive output node OP11 and the negative output node ON11 to the voltage level of the second voltage VL. When the precharge control signal KBC is disabled, the precharge driver 113 may decrease the current driving force that precharges the amplification signal AOUT and the complementary amplification signal AOUTB and/or the current driving force that drives the positive output node OP11 and the negative output node ON11 to the voltage level of the second voltage VL. In an embodiment, the precharge driver 113, together with the precharge control circuit 120, may constitute a precharge circuit. The amplification circuit 100 may consist of the enable circuit 111, the differential circuit 112, and the precharge circuit.
The precharge driver 113 may include a first driver 113-1 and a second driver 113-2. In an embodiment, the part of the precharge driver 113 including the first driver 113-1 is identified as 113/113-1 in
The enable circuit 111 may include a first transistor T11. The first transistor T11 may be a P channel metal-oxide semiconductor (MOS) transistor. The first transistor T11 may receive the first clock signal CLKB through a gate thereof. A source of the first transistor T11 may be coupled to the terminal to which the first voltage VH is supplied. A drain of the first transistor T11 may be coupled to the common node CN.
The differential circuit 112 may include a second transistor T12 and a third transistor T13. The second and third transistors T12 and T13 may each be a P channel MOS transistor. The second transistor T12 may receive the input signal IN through a gate thereof. A source of the second transistor T12 may be coupled to the common node CN. A drain of the second transistor T12 may be coupled to the negative output node ON11. The third transistor T13 may receive the reference voltage VREF through a gate thereof. A source of the third transistor T13 may be coupled to the common node CN. A drain of the third transistor T13 may be coupled to the positive output node OP11.
The first driver 113-1 may include a fourth transistor T14 and a fifth transistor T15. The fourth and fifth transistors T14 and T15 may each be an N channel MOS transistor. The fourth transistor T14 may receive the first clock signal CLKB through a gate thereof. A drain of the fourth transistor T14 may be coupled to the negative output node ON11. A source of the fourth transistor T14 may be coupled to the terminal to which the second voltage VL is supplied. The fifth transistor T15 may receive the first clock signal CLKB through a gate thereof. A drain of the fifth transistor T15 may be coupled to the positive output node OP11. A source of the fifth transistor T15 may be coupled to the terminal to which the second voltage VL is supplied.
The second driver 113-2 may include a sixth transistor T16, a seventh transistor T17, an eighth transistor T18, and a ninth transistor T19. The sixth to ninth transistors T16, T17, T18, and T19 may each be an N channel MOS transistor. The sixth transistor T16 may receive the first clock signal CLKB through a gate thereof. A source of the sixth transistor T16 may be coupled to the terminal to which the second voltage VL is supplied. The seventh transistor T17 may receive the first clock signal CLKB through a gate thereof. A source of the seventh transistor T17 may be coupled to the terminal to which the second voltage VL is supplied. The eighth transistor T18 may receive the precharge control signal KBC through a gate thereof. A drain of the eighth transistor T18 may be coupled to the negative output node ON11. A source of the eighth transistor T18 may be coupled to a drain of the sixth transistor T16. The ninth transistor T19 may receive the precharge control signal KBC through a gate thereof. A drain of the ninth transistor T19 may be coupled to the positive output node OP11. A source of the ninth transistor T19 may be coupled to a drain of the seventh transistor T17.
The latch circuit 130 may include a first transistor T21, a second transistor T22, a third transistor T23, a fourth transistor T24, a fifth transistor T25, a sixth transistor T26, a seventh transistor T27, and an eighth transistor T28. The latch circuit 130 may be an N type latch circuit in which transistors that receive the amplification signal AOUT and the complementary amplification signal AOUTB are N channel MOS transistors, respectively. The first, second, fifth, and sixth transistors T21, T22, T25, and T26 may each be a P channel MOS transistor. The third, fourth, seventh, and eighth transistors T23, T24, T27, and T28 may each be an N channel MOS transistor. The first transistor T21 may receive the second clock signal CLK through a gate thereof. A source of the first transistor T21 may be coupled to the terminal to which the first voltage VH is supplied. A drain of the first transistor T21 may be coupled to a negative output node ON12. The second transistor T22 may receive the second clock signal CLK through a gate thereof. A source of the second transistor T22 may be coupled to the terminal to which the first voltage VH is supplied. A drain of the second transistor T22 may be coupled to a positive output node OP12. The output signal OUT may be output from the positive output node OP12. The complementary output signal OUTB may be output from the negative output node ON12.
The third transistor T23 may receive the amplification signal AOUT through a gate thereof. A source of the third transistor
T23 may be coupled to the terminal to which the second voltage VL is supplied. The fourth transistor T24 may receive the complementary amplification signal AOUTB through a gate thereof. A source of the fourth transistor T24 may be coupled to the terminal to which the second voltage VL is supplied. A gate of the fifth transistor T25 may be coupled to the positive output node OP12. A source of the fifth transistor T25 may be coupled to the terminal to which the first voltage VH is supplied. A drain of the fifth transistor T25 may be coupled to the negative output node ON12. A gate of the sixth transistor T26 may be coupled to the negative output node ON12. A source of the sixth transistor T26 may be coupled to the terminal to which the first voltage VH is supplied. A drain of the sixth transistor T26 may be coupled to the positive output node OP12. A gate of the seventh transistor T27 may be coupled to the positive output node OP12. A drain of the seventh transistor T27 may be coupled to the negative output node ON12. A source of the seventh transistor T27 may be coupled to a drain of the third transistor T23. A gate of the eighth transistor T28 may be coupled to the negative output node ON12. A drain of the eighth transistor T28 may be coupled to the positive output node OP12. A source of the eighth transistor T28 may be coupled to a drain of the fourth transistor T24.
When the second clock signal CLK has a logic low level, the first and second transistors T21 and T22 may be turned on, and the first and second transistors T21 and T22 may precharge the positive output node OP12 and the negative output node ON12 to the voltage level of the first voltage VH. When the second clock signal CLK has a logic high level, the first and second transistors T21 and T22 may be turned off, and the latch circuit 130 may change the voltage levels of the positive output node OP12 and the negative output node ON12 based on the voltage levels of the amplification signal AOUT and the complementary amplification signal AOUTB. When the amplification signal AOUT has a higher voltage level than the complementary amplification signal AOUTB, the voltage level of the negative output node ON12 may be lower than the voltage level of the positive output node OP12 because the amount of current that flows through the seventh transistor T27 is greater than the amount of current that flows through the eighth transistor T28. Accordingly, the positive output node OP12 and/or the output signal OUT may be driven to a logic high level and the negative output node ON12 and/or the complementary output signal OUTB may be driven to a logic low level because the sixth and seventh transistors T26 and T27 maintain a turn-on state. When the amplification signal AOUT has a lower voltage level than the complementary amplification signal AOUTB, the voltage level of the negative output node ON12 may be higher than the voltage level of the positive output node OP12 because the amount of current that flows through the seventh transistor T27 is smaller than the amount of current that flows through the eighth transistor T28. Accordingly, the positive output node OP12 and/or the output signal OUT may be driven to a logic low level and the negative output node ON12 and/or the complementary output signal OUTB may be driven to a logic high level because the fifth and eighth transistors T25 and T28 maintain a turn-on state. The latch circuit 130 may maintain the voltage levels of the positive output node OP12 and the negative output node ON12 until the logic level of the second clock signal CLK is changed to a logic low level.
The threshold value Vth may be variously changed between the highest voltage level VREFmax and the lowest voltage level VREFmin. Referring to
Referring to
The precharge control circuit 320 may receive a reference voltage setting signal RS<0:n>, and may generate the precharge control signal KBC based on the reference voltage setting signal RS<0:n>. The precharge control circuit 320 may be substantially the same as the precharge control circuit 120 illustrated in
The amplifier 310 may include an enable circuit 311, a differential circuit 312, and a precharge driver 313. The enable circuit 311 may be coupled between a terminal to which a second voltage VL is supplied and a common node CN. The enable circuit 311 may receive the second clock signal CLK, and may apply the second voltage VL to the common node CN based on the clock signal CLK. When the second clock signal CLK has a first logic level, the enable circuit 311 may apply the second voltage VL to the common node CN. When the second clock signal CLK has a second logic level, the enable circuit 311 might not apply the second voltage VL to the common node CN. For example, the first logic level may be a logic high level, and the second logic level may be a logic low level.
The differential circuit 312 may be coupled between the common node CN, and the positive output node OP21 and the negative output node ON21. The differential circuit 312 may receive the input signal IN and the reference voltage VREF, and may change the voltage levels of the positive output node OP21 and the negative output node ON21 based on the input signal IN and the reference voltage VREF. The amplification signal AOUT may be output from the positive output node OP21. The complementary amplification signal AOUTB may be output from the negative output node ON21. The differential circuit 312 may change the voltage level of the negative output node ON21 based on the input signal IN, and may change the voltage level of the positive output node OP21 based on the reference voltage VREF. For example, when the input signal IN has a higher voltage level than the reference voltage VREF, the differential circuit 312 may drop the voltage level of the negative output node ON21 by increasing the amount of current that flows from the negative output node ON21 to the common node CN. As the voltage level of the negative output node ON21 drops, the amplification signal AOUT having a logic high level may be output through the positive output node OP21, and the complementary amplification signal AOUTB having a logic low level may be output through the negative output node ON21. When the input signal IN has a lower voltage level than the reference voltage VREF, the differential circuit 312 may drop the voltage level of the positive output node OP21 by increasing the amount of current that flows from the positive output node OP21 to the common node CN. As the voltage level of the positive output node OP21 drops, the amplification signal AOUT having a logic low level may be output through the positive output node OP21, and the complementary amplification signal AOUTB having a logic high level may be output through the negative output node ON21.
The precharge driver 313 may be coupled between the positive output node OP21 and the negative output node ON21, and a terminal to which a first voltage VH is supplied. The precharge driver 313 may receive the second clock signal CLK and the precharge control signal KBC, and may precharge the positive output node OP21 and the negative output node ON21 to the voltage level of the first voltage VH based on the second clock signal CLK and the precharge control signal KBC. The first voltage VH may have a higher voltage level than the second voltage VL. The precharge driver 313 may precharge the positive output node OP21 and the negative output node ON21 to the voltage level of the first voltage VH based on the second clock signal CLK, and may adjust a current driving force that precharges the amplification signal AOUT and the complementary amplification signal AOUTB and/or a current driving force that drives the positive output node OP21 and the negative output node ON21 to the voltage level of the first voltage VH based on the precharge control signal KBC. When the precharge control signal KBC is enabled, the precharge driver 313 may increase the current driving force that precharges the amplification signal AOUT and the complementary amplification signal AOUTB and/or the current driving force that drives the positive output node OP21 and the negative output node ON21 to the voltage level of the first voltage VH. When the precharge control signal KBC is disabled, the precharge driver 313 may decrease the current driving force that precharges the amplification signal AOUT and the complementary amplification signal AOUTB and/or the current driving force that drives the positive output node OP21 and the negative output node ON21 to the voltage level of the first voltage VH.
The precharge driver 313 may include a first driver 313-1 (i.e., identified as 313/313-1) and a second driver 313-2 (i.e., identified as 313/313-2). The first driver 313-1 may be coupled between the positive output node OP21 and the negative output node ON21, and a terminal to which the first voltage VH is supplied. The first driver 313-1 may receive the second clock signal CLK, and may drive and/or precharge the positive output node OP21 and the negative output node ON21 to the voltage level of the first voltage VH based on the second clock signal CLK. The second driver 313-2 may be coupled between the positive output node OP21 and the negative output node ON21, and the terminal to which the first voltage VH is supplied. The second driver 313-2 may receive the second clock signal CLK and the precharge control signal KBC, and may drive and/or precharge the positive output node OP21 and the negative output node ON21 to the voltage level of the first voltage VH based on the second clock signal CLK and the precharge control signal KBC.
The enable circuit 311 may include a first transistor T31. The first transistor T31 may be an N channel MOS transistor. The first transistor T31 may receive the second clock signal CLK through a gate thereof. A drain of the first transistor T31 may be coupled to the common node CN. A source of the first transistor T31 may be coupled to a terminal to which the second voltage VL is supplied.
The differential circuit 312 may include a second transistor T32 and a third transistor T33. The second and third transistors T32 and T33 may each be an N channel MOS transistor. The second transistor T32 may receive the input signal IN through a gate thereof. A drain of the second transistor T32 may be coupled to the negative output node ON21. A source of the second transistor T32 may be coupled to the common node CN. The third transistor T33 may receive the reference voltage VREF through a gate thereof. A drain of the third transistor T33 may be coupled to the positive output node OP21. A source of the third transistor 323 may be coupled to the common node CN.
The first driver 313-1 may include a fourth transistor T34 and a fifth transistor T35. The fourth and fifth transistors T34 and T35 may each be a P channel MOS transistor. The fourth transistor T34 may receive the second clock signal CLK through a gate thereof. A source of the fourth transistor T34 may be coupled to the terminal to which the second voltage VH is supplied. A drain of the fourth transistor T34 may be coupled to the negative output node ON21. The fifth transistor T35 may receive the second clock signal CLK through a gate thereof. A source of the fifth transistor T35 may be coupled to the terminal to which the second voltage VH is supplied. A drain of the fifth transistor T35 may be coupled to the positive output node OP21.
The second driver 313-2 may include a sixth transistor T36, a seventh transistor T37, an eighth transistor T38, and a ninth transistor T39. The sixth to ninth transistors T36, T37, T38, and T39 may each be a P channel MOS transistor. The sixth transistor T36 may receive the second clock signal CLK through a gate thereof. A source of the sixth transistor T36 may be coupled to the terminal to which the second voltage VH is supplied. The seventh transistor T37 may receive the second clock signal CLK through a gate thereof. A source of the seventh transistor T37 may be coupled to the terminal to which the second voltage VH is supplied. The eighth transistor T38 may receive the precharge control signal KBC through a gate thereof. A source of the eighth transistor T38 may be coupled to a drain of the sixth transistor T36. A drain of the eighth transistor T38 may be coupled to the negative output node ON21. The ninth transistor T39 may receive the precharge control signal KBC through a gate thereof. A source of the ninth transistor T39 may be coupled to a drain of the seventh transistor T37. A drain of the ninth transistor T39 may be coupled to the positive output node OP21.
The latch circuit 330 may include a first transistor T41, a second transistor T42, a third transistor T43, a fourth transistor T44, a fifth transistor T45, a sixth transistor T46, a seventh transistor T47, and an eighth transistor T48. The latch circuit 330 may be a P type latch circuit in which transistors that receive the amplification signal AOUT and the complementary amplification signal AOUTB are P channel MOS transistors, respectively. The first, second, fifth, and sixth transistors T41, T42, T45, and T46 may each be an N channel MOS transistor. The third, fourth, seventh, and eighth transistors T43, T44, T47, and T48 may each be a P channel MOS transistor. The first transistor T41 may receive the first clock signal CLKB through a gate thereof. A drain of the first transistor T41 may be coupled to a negative output node ON22. A source of the first transistor T41 may be coupled to the terminal to which the second voltage VL is supplied. The second transistor T42 may receive the first clock signal CLKB through a gate thereof. A drain of the second transistor T42 may be coupled to a positive output node OP22. A source of the second transistor T42 may be coupled to the terminal to which the second voltage VL is supplied. The output signal OUT may be output from the positive output node OP22. The complementary output signal OUTB may be output from the negative output node ON22.
The third transistor T43 may receive the amplification signal AOUT through a gate thereof. A source of the third transistor T43 may be coupled to the terminal to which the first voltage VH is supplied. The fourth transistor T44 may receive the complementary amplification signal AOUTB through a gate thereof. A source of the fourth transistor T44 may be coupled to the terminal to which the first voltage VH is supplied. A gate of the fifth transistor T45 may be coupled to the positive output node OP22. A drain of the fifth transistor T45 may be coupled to the negative output node ON22. A source of the fifth transistor T45 may be coupled to the terminal to which the second voltage VL is supplied. A gate of the sixth transistor T46 may be coupled to the negative output node ON22. A drain of the sixth transistor T46 may be coupled to the positive output node OP22. A source of the sixth transistor T46 may be coupled to the terminal to which the second voltage VL is supplied. A gate of the seventh transistor T47 may be coupled to the positive output node OP22. A source of the seventh transistor T47 may be coupled to a drain of the third transistor T43. A drain of the seventh transistor T47 may be coupled to the negative output node ON22. A gate of the eighth transistor T48 may be coupled to the negative output node ON22. A source of the eighth transistor T48 may be coupled to a drain of the fourth transistor T44. A drain of the eighth transistor T48 may be coupled to the positive output node OP22.
When the first clock signal CLKB has a logic high level, the first and second transistors T41 and T42 may be turned on, and the first and second transistors T41 and T42 may precharge the positive output node OP22 and the negative output node ON22 to the voltage level of the second voltage VL. When the first clock signal CLKB has a logic low level, the first and second transistors T41 and T42 may be turned off, and the latch circuit 330 may change the voltage levels of the positive output node OP22 and the negative output node ON22 based on the voltage levels of the amplification signal AOUT and the complementary amplification signal AOUTB. When the amplification signal AOUT has a higher voltage level than the complementary amplification signal AOUTB, the voltage level of the negative output node ON22 may be lower than the voltage level of the positive output node OP22 because the amount of current that flows through the seventh transistor T47 is smaller than the amount of current that flows through the eighth transistor T48. Accordingly, the positive output node OP22 and/or the output signal OUT may be driven to a logic high level and the negative output node ON22 and/or the complementary output signal OUTB may be driven to a logic low level because the fifth and eighth transistors T45 and T48 maintain a turn-on state. When the amplification signal AOUT has a lower voltage level than the complementary amplification signal AOUTB, the voltage level of the negative output node ON22 may be higher than the voltage level of the positive output node OP22 because the amount of current that flows through the seventh transistor T47 is greater than the amount of current that flows through the eighth transistor T48. Accordingly, the positive output node OP22 and/or the output signal OUT may be driven to a logic low level and the negative output node ON22 and/or the complementary output signal OUTB may be driven to a logic high level because the sixth and seventh transistors T46 and T47 maintain a turn-on state. The latch circuit 330 may maintain the voltage levels of the positive output node OP22 and the negative output node ON22 until the logic level of the first clock signal CLKB is changed to a logic low level.
The first amplifier 410 may generate a first amplification signal AOUT1, based on the second clock signal CLK, the input signal IN, and the reference voltage VREF. The first amplifier 410 may generate a first complementary amplification signal AOUT1B along with the first amplification signal AOUT1. When the second clock signal CLK has a first logic level, the first amplifier 410 may generate the first amplification signal AOUT1 and the first complementary amplification signal AOUT1B by differentially amplifying the input signal IN and the reference voltage VREF. When the second clock signal CLK has a second logic level, the first amplifier 410 may precharge the first amplification signal AOUT1 and the first complementary amplification signal AOUT1B. The first amplifier 410 may adjust a current driving force that precharges the first amplification signal AOUT1 and the first complementary amplification signal AOUT1B based on the voltage level of the reference voltage VREF. The first amplifier 410 may include one of the amplifiers 100 and 300 illustrated in
The second amplifier 420 may generate a second amplification signal AOUT2, based on the first clock signal CLKB, the input signal IN, and the reference voltage VREF. The second amplifier 420 may generate a second complementary amplification signal AOUT2B along with the second amplification signal AOUT2. When the first clock signal CLKB has a first logic level, the second amplifier 420 may generate the second amplification signal AOUT2 and the second complementary amplification signal AOUT2B by differentially amplifying the input signal IN and the reference voltage VREF. When the first clock signal CLKB has a second logic level, the second amplifier 420 may precharge the second amplification signal AOUT2 and the second complementary amplification signal AOUT2B. The second amplifier 420 may adjust a current driving force that precharges the second amplification signal AOUT2 and the second complementary amplification signal AOUT2B based on the voltage level of the reference voltage VREF. The second amplifier 420 may include one of the amplifiers 110 and 310 illustrated in
The receiver circuit 400 may further include a precharge control circuit 430. The precharge control circuit 430 may generate a precharge control signal KBC by receiving a reference voltage setting signal RS<0:n>. The precharge control circuit 430 may be substantially the same as the precharge control circuit 120 illustrated in
The receiver circuit 400 may further include a first latch circuit 440 and a second latch circuit 450. The first latch circuit 440 may be coupled to the first amplifier 410, and may receive the first amplification signal AOUT1 and the first complementary amplification signal AOUT1B from the first amplifier 410. The first latch circuit 440 may generate the first output signal OUT1 by amplifying and latching the first amplification signal AOUT1 and the first complementary amplification signal AOUT1B. The first latch circuit 440 may generate a first complementary output signal OUT1B along with the first output signal OUT1. The first latch circuit 440 may receive the first clock signal CLKB and operate in synchronization with the first clock signal CLKB. When the first clock signal CLKB has a second logic level, the first latch circuit 440 may precharge the first output signal OUT1 and the first complementary output signal OUT1B. When the first clock signal CLKB has a first logic level, the first latch circuit 440 may generate the first output signal OUT1 and the first complementary output signal OUT1B based on the voltage levels of the first amplification signal AOUT1 and the first complementary amplification signal AOUT1B. The first latch circuit 440 may include one of the latch circuits 130 and 330 illustrated in
The second latch circuit 450 may be coupled to the second amplifier 420, and may receive the second amplification signal AOUT2 and the second complementary amplification signal AOUT2B from the second amplifier 420. The second latch circuit 450 may generate the second output signal OUT2 by amplifying and latching the second amplification signal AOUT2 and the second complementary amplification signal AOUT2B. The second latch circuit 450 may generate a second complementary output signal OUT2B along with the second output signal OUT2. The second latch circuit 450 may receive the second clock signal CLK and operate in synchronization with the second clock signal CLK. When the second clock signal CLK has a second logic level, the second latch circuit 450 may precharge the second output signal OUT2 and the second complementary output signal OUT2B. When the second clock signal CLK has a first logic level, the second latch circuit 450 may generate the second output signal OUT2 and the second complementary output signal OUT2B based on the voltage levels of the second amplification signal AOUT2 and the second complementary amplification signal AOUT2B. The second latch circuit 450 may include one of the latch circuits 130 and 330 illustrated in
The receiver circuit 400 may further include a third latch circuit 460 and a fourth latch circuit 470. The third latch circuit 460 may be coupled to the first latch circuit 440, and may receive the first output signal OUT1 from the first latch circuit 440. The third latch circuit 460 may generate a first internal signal IS0 based on the first output signal OUT1. The third latch circuit 460 may generate the first internal signal IS0 by latching the voltage level of the first output signal OUT1. The fourth latch circuit 470 may be coupled to the second latch circuit 450, and may receive the second output signal OUT2 from the second latch circuit 450. The fourth latch circuit 470 may generate a second internal signal IS180 based on the second output signal OUT2. The fourth latch circuit 470 may generate the second internal signal IS180 by latching the voltage level of the second output signal OUT2. The third and fourth latch circuits 460 and 470 may each be implemented by using various latch circuits, such as, for example but not limited to, an SR latch circuit.
When the second clock signal CLK has a logic low level, a first transistor T51 of the first amplifier 410 may be turned on, fourth to seventh transistors T54, T55, T56, and T57 of the first amplifier 410 may be turned off, and thus the first amplifier 410 may perform a differential amplification operation. The first transistor T51 may apply a first voltage VH to a first common node CN1. A second transistor T52 may change the voltage level of a first negative output node ON1 based on the voltage level of the input signal IN. A third transistor T53 may change the voltage level of a first positive output node OP1 based on the voltage level of the reference voltage VREF. The first amplification signal AOUT1 may be output from the first positive output node OP1. The first complementary amplification signal AOUT1B may be output from the first negative output node ON1. When the second clock signal CLK has a logic low level, a first transistor T61 of the second amplifier 420 may be turned off, fourth to seventh transistors T64, T65, T66, and T67 of the second amplifier 420 may be turned on, and thus the second amplifier 420 may perform a precharge operation. Eighth and ninth transistors T68 and T69 of the second amplifier 420 may be selectively turned on based on the logic level of the precharge control signal KBC. The second amplifier 420 may precharge a second negative output node ON2 and a second positive output node OP2 by driving the second negative output node ON2 and the second positive output node OP2 to the voltage level of the second voltage VL.
When the second clock signal CLK has a logic high level, the first transistor T51 may be turned off, the fourth to seventh transistors T54, T55, T56, and T57 may be turned on, and thus the first amplifier 410 may perform a precharge operation. Eighth and ninth transistors T58 and T59 of the first amplifier 410 may be selectively turned on based on the logic level of the precharge control signal KBC. The first amplifier 410 may precharge the first negative output node ON1 and the first positive output node OP1 by driving the first negative output node ON1 and the first positive output node OP1 to the voltage level of the second voltage VL. When the second clock signal CLK has a logic high level, the first transistor T61 may be turned on, the fourth to seventh transistors T64, T65, T66, and T67 may be turned off, and thus the second amplifier 420 may perform a differential amplification operation. The first transistor T61 may apply the first voltage VH to a second common node CN2. A second transistor T62 may change the voltage level of the second negative output node ON2 based on the voltage level of the input signal IN. A third transistor T63 may change the voltage level of the second positive output node OP2 based on the voltage level of the reference voltage VREF. The second amplification signal AOUT2 may be output from the second positive output node OP2. The second complementary amplification signal AOUT2B may be output from the second negative output node ON2.
A parasitic capacitor 511 may be formed between the line through which the input signal IN is transmitted and the first common node CN1. A parasitic capacitor 512 may also be formed between the line through which the input signal IN is transmitted and the first negative output node ON1. A parasitic capacitor 513 may be formed between the line through which the reference voltage VREF is transmitted and the first common node CN1. A parasitic capacitor 514 may also be formed between the line through which the reference voltage VREF is transmitted and the first positive output node OP2. Likewise, a parasitic capacitor 521 may be formed between the line through which the input signal IN is transmitted and the second common node CN2. A parasitic capacitor 522 may also be formed between the line through which the input signal IN is transmitted and the second negative output node ON2. A parasitic capacitor 523 may be formed between the line through which the reference voltage VREF is transmitted and the second common node CN2. A parasitic capacitor 524 may also be formed between the line through which the reference voltage VREF is transmitted and the second positive output node OP2. The parasitic capacitors 511, 512, 513, and 514 that have been formed in the first amplifier 410 may generate kickback noise in the voltage levels of the input signal IN and the reference voltage VREF, when the logic levels of the second clock signal CLK and the input signal IN transition and thus the voltage levels of the first common node CN1, the first positive output node OP1, and the first negative output node ON1 are changed. The parasitic capacitors 521, 522, 523, and 524 that have been formed in the second amplifier 420 may generate kickback noise in the voltage levels of the input signal IN and the reference voltage VREF, when the logic levels of the first clock signal CLKB and the input signal IN transition and thus the voltage levels of the second common node CN2, the second positive output node OP2, and the second negative output node ON2 are changed. In an embodiment, the kickback noise may reduce a difference between the voltage levels of the input signal IN and the reference voltage VREF by changing the voltage levels of the input signal IN and the reference voltage VREF in an unwanted direction, and may reverse the voltage levels of the input signal IN and the reference voltage VREF in the worst case.
7B, when the reference voltage VREF has a relatively low voltage level, the precharge control circuit 430 may disable the precharge control signal KBC. When the precharge control signal KBC is disabled, the second amplifier 420 may decrease a current driving force that precharges the second amplification signal AOUT2. When the precharge control signal KBC is disabled, both the eighth and ninth transistors T68 and T69 may be turned off, and only the fourth and fifth transistors T64 and T65 may precharge the second negative output node ON2 and the second positive output node OP2 to the voltage level of the second voltage VL. In an embodiment, when the second positive output node OP2 and the second negative output node ON2 are less driven by the fourth and fifth transistors T64 and T65, kickback noise attributable to the parasitic capacitors 522 and 524 might not fully offset kickback noise attributable to the parasitic capacitors 511, 512, 513, and 514, and the voltage levels of the reference voltage VREF and the input signal IN may rise. Accordingly, in an embodiment, at timing at which the kickback noise occurs, the voltage levels of the input signal IN and the reference voltage VREF may rise, a difference between the voltage levels of the input signal IN and the reference voltage VREF may be increased, and a sensing margin of the first amplifier 410 may be secured. In an embodiment, the first amplifier 410 may generate the first amplification signal AOUT1 having a logic level corresponding to the input signal IN because the first amplifier 410 differentially amplifies the input signal IN and the reference voltage VREF having the secured sensing margin.
The second semiconductor apparatus 620 may be coupled to the first semiconductor apparatus 610 through a plurality of buses. The plurality of buses may each be a signal transmission path, a link, or a channel for transmitting a signal. The plurality of buses may include a clock bus 601 and a data bus 602. The clock bus 601 may be a unidirectional bus from the first semiconductor apparatus 610 to the second semiconductor apparatus 620. The data bus 602 may be a bi-directional bus. Although not illustrated, the semiconductor system 600 may further include a command bus and an address bus for transmitting a command signal and an address signal from the first semiconductor apparatus 610 to the second semiconductor apparatus 620. The second semiconductor apparatus 620 may be coupled to the first semiconductor apparatus 610 through the clock bus 601, and may receive a system clock signal SCK from the first semiconductor apparatus 610 through the clock bus 601. The system clock signal SCK may be transmitted as a single-ended signal, and may be transmitted as a differential signal along with the complementary system clock signal SCKB. The second semiconductor apparatus 620 may be coupled to the first semiconductor apparatus 610 through the data bus 602, and may receive data DQ from the first semiconductor apparatus 610 or transmit data DQ to the first semiconductor apparatus 610 through the data bus 602.
The first semiconductor apparatus 610 may include a system clock generation circuit 611, a data transmission circuit 612, and a data receiver circuit 613. The system clock generation circuit 611 may generate the system clock signal SCK. The system clock generation circuit 611 may provide the system clock signal SCK to the second semiconductor apparatus 620 through the clock bus 601. The system clock generation circuit 611 may transmit the complementary system clock signal SCKB along with the system clock signal SCK. The system clock generation circuit 611 may include a clock generation circuit, such as an oscillator, a delay-locked loop circuit, or a phase-locked loop circuit. The system clock generation circuit 611 may provide the system clock signal SCK to the data transmission circuit 612 and the data receiver circuit 613. In an embodiment, the system clock generation circuit 611 may delay the system clock signal SCK by a required delay time, and may provide the delayed clock signal to the data transmission circuit 612 and the data receiver circuit 613.
The data transmission circuit 612 may receive internal data signal IND1 of the first semiconductor apparatus 610, and may receive the system clock signal SCK from the system clock generation circuit 611. The data transmission circuit 612 may generate the data DQ from the internal data signal IND1 in synchronization with the system clock signal SCK. The data transmission circuit 612 may transmit the data DQ through the data bus 602 by driving the data bus 602 based on the logic level of the internal data signal IND1 in synchronization with the system clock signal SCK. The data receiver circuit 613 may receive the data DQ through the data bus 602, and may receive the system clock signal SCK from the system clock generation circuit 611. The data receiver circuit 613 may receive a first reference voltage VREF1. The data receiver circuit 613 may generate the internal data signal IND1 by differentially amplifying the data signal DQ and the first reference voltage VREF1 in synchronization with the system clock signal SCK. When the system clock signal SCK has a first logic level, the data receiver circuit 613 may generate an odd-numbered bit of the internal data signal IND1 by differentially amplifying the data signal DQ and the first reference voltage VREF1. When the system clock signal SCK has a second logic level, the data receiver circuit 613 may generate an even-numbered bit of the internal data signal IND1 by differentially amplifying the data signal DQ and the first reference voltage VREF1. The receiver circuit 400 illustrated in
The second semiconductor apparatus 620 may include an internal clock generation circuit 621, a data transmission circuit 622, and a data receiver circuit 623. The internal clock generation circuit 621 may be coupled to the clock bus 601, and may receive the system clock signal SCK and the complementary system clock signal SCKB that are transmitted through the clock bus 601. The internal clock generation circuit 621 may generate a reference clock signal by buffering the system clock signal SCK and the complementary system clock signal CKB, and may generate a plurality of internal clock signals by dividing the frequency of the reference clock signal. The plurality of internal clock signals may include a transmission clock signal TCK and a reception clock signal RCK. Both the transmission clock signal TCK and the reception clock signal RCK may be synchronized with the reference clock signal. The transmission clock signal TCK and the reception clock signal RCK may have the same phase or may have different phases. In an embodiment, the internal clock generation circuit 621 may include a delay-locked loop circuit, and may generate the transmission clock signal TCK and the reception clock signal RCK by performing a delay-locked operation on the reference clock signal. The internal clock generation circuit 621 may provide the transmission clock signal TCK to the data transmission circuit 622 and provide the reception clock signal RCK to the data receiver circuit 623.
The data transmission circuit 622 may receive an internal data signal IND2 of the second semiconductor apparatus 620, and may receive the transmission clock signal TCK from the internal clock generation circuit 621. The data transmission circuit 622 may generate the data DQ from the internal data signal IND2 in synchronization with the transmission clock signal TCK. The data transmission circuit 622 may transmit the data DQ through the data bus 602 by driving the data bus 602 based on the logic level of the internal data signal IND2 in synchronization with the transmission clock signal TCK. The data receiver circuit 623 may receive the data DQ through the data bus 602 and receive the reception clock signal RCK from the internal clock generation circuit 621. The data receiver circuit 623 may receive a second reference voltage VREF2. The second reference voltage VREF2 may have substantially the same voltage level as the first reference voltage VREF1 or may have a voltage level different from the voltage level of the first reference voltage VREF1. The data receiver circuit 623 may generate the internal data signal IND2 by differentially amplifying the data signal DQ and the second reference voltage VREF2 in synchronization with the reception clock signal RCK. When the reception clock signal RCK has a first logic level, the data receiver circuit 623 may generate an odd-numbered bit of the internal data signal IND2 by differentially amplifying the data signal DQ and the second reference voltage VREF2. When the reception clock signal RCK has a second logic level, the data receiver circuit 623 may generate an even-numbered bit of the internal data signal IND2 by differentially amplifying the data signal DQ and the second reference voltage VREF2. The receiver circuit 400 illustrated in
Those skilled in the art to which the present technology pertains may understand that the present technology may be implemented in various other forms without departing from the technical spirit or essential characteristics of the present technology. Accordingly, it is to be understood that the aforementioned embodiments are illustrative from all aspects not being limitative. The scope of the present technology is defined by the appended claims rather than by the detailed description, and all modifications or variations derived from the meanings and scope of the claims and equivalents thereof should be understood as being included in the scope of the present technology.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2024-0000354 | Jan 2024 | KR | national |
