Patent Application
20080012718
The accompanying drawings, which are incorporated in and constitute a part of this specification illustrate an embodiment of the invention and, together with the description, serve to explain the objects, advantages and principles of the invention.
In the drawings,
A detailed description of preferred embodiments of an amplifier of the present invention will now be given referring to accompanying
The detection circuit 2 receives the output signal from the output terminal OUT of the variable gain amplifier 3 and outputs an alarm signal ALM and a control signal CTL to the amplifier 3. The detection circuit 2 is provided with a first signal level V1 and a second signal level V2.
An output voltage level VOUT at the output terminal OUT is compared with the first signal level V1 and the second signal level V2. As a result of the comparison, when the output voltage level VOUT is lower than the first signal level V1, the detection circuit 2 outputs the alarm signal ALM and simultaneously the control signal CTL to command the variable gain amplifier 3 to stop the operation thereof.
When the output voltage level VOUT is higher than the second signal level V2, the detection circuit 2 outputs a control signal CTL to command the variable gain amplifier 3 to perform an amplifying operation at a first gain G1.
In the case where the output level VOUT is the first signal level V1 or higher and the second signal level V2 or lower, the detection circuit 2 outputs a control signal CTL to cause the variable gain amplifier 3 to perform the amplifying operation at a second gain G2 which is larger than the first gain G1.
A bias current in the variable gain amplifier 3 is controlled in response to the control signal CTL, so that the variable gain amplifier 3 stops the amplifying operation or performs the amplifying operation at the first gain G1 or the second gain G2.
In the variable gain amplifier 3, an output potential Vout is represented by the following expression:
Vout=VCC−(IC2×RC2)
where IC2 is represented by:
IC2=Hfe/(1+Hfe)×I0/(1+exp(q/kT)×(Vin1−Vin2))
Accordingly, reducing the bias current IO of the current source IC can lower a gain. In other words, in the variable gain amplifier 3, lowering gain makes it possible to reduce the bias current. When the variable gain amplifier 3 is operated at the gain G1 which is smaller than the second gain G2, it can be operated at a smaller bias current than it is operated at the gain G2. Power consumption thereof can therefore be restrained.
When the input level falls within a first signal level range R1 which is lower than the first signal level V1, the variable gain amplifier 3 is stopped, the gain becomes zero and current consumption decreases to almost zero. In this case, the detection circuit 2 outputs the alarm signal ALM.
When the input level falls within a second signal level range R2 which is higher than the second signal level V2, the variable gain amplifier 3 is caused to amplify the sense signal at the first gain G1.
When the input level falls within a third signal level range R3 defined between the first signal level V1 and the second signal level V2, the variable gain amplifier 3 is caused to amplify the sense signal at the second gain G2. Thus, it is possible to detect with sufficient sensitivity as to whether or not the input level reaches the first signal level V1 or the second signal level V2.
In the first signal level range R1 and the second signal level range R2, power consumption can be more restrained as compared in the third signal level range R3. The amplifier 1 in the present embodiment allows operations with low current consumption while ensuring sufficient sensitivity to the sense signal.
The first detection circuit 21 receives an output signal from an output terminal OUT of the second amplifier 32 and is provided with a first signal level V1 and is connected to the latch 23 which outputs an alarm signal ALM. This alarm signal ALM is a negative logic signal which is active low. In the first detection circuit 21, an output voltage level VOUT at the output terminal OUT is compared with the first signal level V1. As a result of the comparison, when the output voltage level VOUT is lower than the first signal level V1, a signal of a low level is output. In the latch 23, its inverting set terminal XS is connected to an output terminal of the first detection circuit 21. Accordingly, once an output signal from the first detection circuit 21 changes to a low level, the alarm signal ALM is output at a low level and remains at that level. The alarm signal ALM therefore remains at the low level once it is output at the low level. Even if the output voltage level VOUT thereafter exceeds the first signal level V1, the alarm signal ALM will not change.
The second detection circuit 22 receives an output signal from a first output terminal OUT1 of the first amplifier 31 and is provided with a second signal level V2, and outputs a control signal CTL. In the second detection circuit 22, a first output voltage level VOUT1 at the first output terminal OUT1 is compared with the second signal level V2. If the first output voltage level VOUT1 exceeds the second signal level V2, the second detection circuit 22 outputs a control signal CTL of a low level to command the second amplifier 32 to stop its amplifying operation.
The first amplifier 31 is arranged to amplify a signal input at an input terminal IN connected to a sensor 4 or the like. The first amplifier 31 stops an amplifying operation in response to the alarm signal ALM of a low level and outputs a fixed-high-level signal.
Of them, the NMOS transistors N312 to N316 constitute a current mirror type amplifier which receives a differential signal at input terminals IN1 and IN2. The resistor R31 and the NMOS transistor N311 generate bias voltage to the NMOS transistor N316 serving as a current source of the above current mirror type amplifier. Further, the NMOS transistors 318 and 319 constitute an output buffer.
In response to the alarm signal ALM, the NMOS transistors N310 and N317 and the inverter INV31 control interruption of the bias current in the current mirror type amplifier. If the alarm signal ALM is at a low level, for instance, a gate terminal of the NMOS transistor N317 is set to a high level through the inverter INV31, whereas a gate terminal of the NMOS transistor N310 is set to a low level. Accordingly, the NMOS transistor N310 is brought out of conduction, while the NMOS transistor N317 is brought into conduction. This causes a bias voltage VB31 to become a low level and interrupts the bias current to the NMOS transistor N316.
On the other hand, if the alarm signal ALM is at a high level, the gate terminal of the NMOS transistor N317 is set to a low level through the inverter INV31 and the gate terminal of the NMOS transistor N310 is set to a high level. Accordingly, the NMOS transistor N310 is brought into conduction, while the NMOS transistor N317 is brought out of conduction. Thus the bias voltage VB31 becomes a potential determined depending on the resistor R31 and the NMOS transistor N311, allowing an appropriate bias current to flow in the NMOS transistor N316, thereby activating the current mirror type amplifier.
The PMOS transistor P31 is a transistor for stabilizing the output signal from the first output terminal OUT1 at a high level in response to the alarm signal ALM. Specifically, if the alarm signal ALM is at a low level, making the PMOS transistor P31 conductive, a high-level signal will be output at the first output terminal OUT1. If the alarm signal ALM is at a high level, on the other hand, making the PMOS transistor P31 nonconductive, a signal will be output from the NMOS transistors N318 and N319.
With the above configuration, when the output voltage level VOUT is lower than the first signal level V1, the alarm signal ALM is output, causing the first amplifier 31 to stop its amplifying operation and simultaneously interrupting the bias current for activating the first amplifier 31, providing zero gain. Thus, power consumption is restrained.
The second amplifier 32 is arranged to amplify a signal of the first output voltage level VOUT1 output from the first amplifier 31. At an initial stage, the control signal CTL is at a low level, and accordingly, the second amplifier 32 is caused to stop an amplifying operation and output a fixed-high-level signal. Then, when the control signal CTL transfers to a high level, the second amplifier 32 is caused to start the amplifying operation.
Of them, the NMOS transistors N322 to N326 constitute a current mirror type amplifier whose differential input having one end connected to a reference voltage e32 and the other end connected to the first output terminal OUT1 of the first amplifier 31. Further, the resistor R32 and the NMOS transistor N321 produce bias voltage to the NMOS transistor N326 serving as a current source of the above current mirror type amplifier. The NMOS transistors N328 and N329 constitute an output buffer.
The NMOS transistors N320 and N327 and the inverter INV32 correspond to a switching transistor which controls interruption of the bias current in the current mirror type amplifier in response to input of the control signal CTL. If the control signal CTL is at a low level, for instance, a gate terminal of the NMOS transistor N327 is set to a high level through the inverter INV32, whereas the gate terminal of the NMOS transistor N320 is set to a low level. Accordingly, the NMOS transistor N320 is brought out of conduction, while the NMOS transistor N327 is brought into conduction. This causes a bias voltage VB32 to become a low level and interrupts the bias current to the NMOS transistor N326, providing zero gain.
On the other hand, if the control signal CTL is at a high level, the gate terminal of the NMOS transistor N327 is set to a low level through the inverter INV32, whereas the gate terminal of the NMOS transistor N320 is set to a high level. Accordingly, the NMOS transistor N320 is brought into conduction, while the NMOS transistor N327 is brought out of conduction. Thus, the bias voltage VB32 becomes a potential determined depending on the resistor R32 and the NMOS transistor N321, allowing an appropriate bias current to flow in the NMOS transistor N326, thereby activating the current mirror type amplifier.
The PMOS transistor P32 is a transistor for stabilizing an output signal from the output terminal OUT at a high level in response to the control signal CTL. Specifically, if the control signal CTL is at a low level, making the PMOS transistor P32 conductive, the high-level signal will be output at the output terminal OUT. If the control signal CTL is at a high level, making the PMOS transistor P32 nonconductive, a signal will be output from the NMOS transistors N328 and N329.
In the second amplifier 32, the amplifying operation is enabled or stopped in response to the control signal CTL. In other words, when the first output voltage level VOUT1 is lower than the second signal level V2, the control signal CTL is output at a high level, causing the amplifying operation of the second amplifier 32 to start. When the first output voltage level VOUT1 is higher than the second signal level V2, on the other hand, the control signal CTL is output at a low level, causing the amplifying operation of the second amplifier 32 to stop. In this case, specifically, the bias current flowing in the second amplifier 32 is interrupted, providing zero gain. Thus, power consumption is restrained.
The following explanations will be made on operations of the amplifier 10, referring to
In the period (1), the first amplifier 31 operates so that its output level changes in a second signal-level range R2 in which the input level to the second detection circuit 22 is higher than the second signal level V2. This causes the second detection circuit 22 to output a low level signal, thus commanding the second amplifier 32 to stop its amplifying operation. Consequently, the second amplifier 32, in which the bias current is interrupted, providing zero gain, can operate with low current consumption than in the case where it performs the amplifying operation.
At the time (2), the output level of the first amplifier 31 falls below the second signal level V2. The second amplifier 32 will operate to output a signal of a level in a third signal-level range R3. The second detection circuit 22 is caused to output a high level signal, commanding the second amplifier 32 to start the amplifying operation. In the second amplifier 32, accordingly, changes in output to input, namely, sensitivity is increased to a sufficient degree for detection until the output voltage level VOUT of the second amplifier 32 becomes lower than the first signal level V1 in the period (3).
At the time (4), when the output level of the second amplifier 32 falls below the first signal level V1, a command to stop the amplifying operation is transmitted from the first detection circuit 21 to the first amplifier 31 via the latch 23. Thus, the amplifying operation of the first amplifier 31 is stopped and the output signal at the first output terminal OUT1 clips to a high level.
At the time (5), when the output signal at the first output terminal OUT1 of the first amplifier 31 exceeds the second signal level V2, the second detection circuit 22 transmits a command to the second amplifier 32 to perform the amplifying operation at the first gain G1 again. The second amplifier 32 will thus operate to output a signal of a level in a first signal-level range R1. Accordingly, the second amplifier 32, in which the bias current is interrupted again, will operate with low current consumption than in the case where it performs the amplifying operation. It is to be noted that the second amplifier 32 receives the output signal having clipped to a high level from the first output terminal OUT1, so that it outputs a high level signal at the output terminal OUT.
As explained above in detail, according to the amplifier 10 in the present embodiments, it is possible to achieve an amplifier which amplifies a sense signal from a sensor 4 with low electric power consumption while keeping sufficient sensitivity.
The present invention is not limited to the above embodiments and may be embodied in other specific forms without departing from the essential characteristics thereof.
In the above embodiment, for instance, the second amplifier 32 is stopped for the second signal level range R2 and the bias current thereto is interrupted. Alternatively, the present invention may also be applied to another embodiment in which the bias current in the second amplifier 32 is reduced for the second signal level range R2 to cause the second amplifier 32 to operate at a smaller gain.
Further, the present invention may also be applied to another embodiment in which the entire amplifier is caused to operate intermittently by a control signal transmitted thereto from outside. In this case, it is preferable not to cause the amplifier to intermittently operate while the alarm signal ALM is active low. This is because even though the first detection circuit 21, second detection circuit 22, first and second amplifiers 31 and 32 do not have to operate while the alarm signal ALM is active low, such intermittent operation may cause actually unnecessary current consumption.
According to the present invention, it is possible to provide an amplifier which amplifies an input signal, capable of operating with low current consumption while keeping sufficient sensitivity.
While the presently preferred embodiment of the present invention has been shown and described, it is to be understood that this disclosure is for the purpose of illustration and that various changes and modifications may be made without departing from the scope of the invention as set forth in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-179709 | Jun 2006 | JP | national |
