Patent Application
20240297625
The present disclosure relates generally to electronics, and more specifically to amplifier biasing in transceivers.
Wireless communication devices and technologies are becoming ever more prevalent, as are communication devices that operate at 5G NR Sub7 FR1 and millimeter-wave (mmW) FR2 frequencies. Wireless communication devices generally transmit and/or receive communication signals. In a radio frequency (RF) transceiver, a communication signal is typically amplified and transmitted by a transmit section and a received communication signal is amplified and processed by a receive section. A communication device may include multiple transmitters, receivers and antennas and may be capable of communicating on licensed and on unlicensed communication bands and frequencies.
Such communication devices may be configured to communicate via a wireless local-area technology, such as a Bluetooth, a Wi-Fi (IEEE 802.11), or an industrial, scientific or medical network (ISM) network. As governmental authorities generally do not allocate wireless local-area communication frequency bands to specific entities, the frequency bands associated with such technologies are commonly referred to as “unlicensed” communication spectrum, also referred to as unlicensed frequency bands. In contrast, communication spectrum and frequency bands associated with wide-area wireless communication technologies are commonly referred to as “licensed” communication spectrum, or licensed frequency bands, because they are generally allocated to specific entities by governmental authorities.
It would be desirable to share components when implementing a communication device that may communicate using both licensed (e.g., WLAN) and unlicensed (e.g., Bluetooth) frequency bands.
Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features are described herein.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
One aspect of the disclosure provides a transimpedance-based baseband filter (BBF) including a two-stage operational transconductance amplifier (OTA) having a first stage based on a folded cascode topology, the first stage electrically coupled to a second stage, the second stage having a class AB topology, the first stage having an N-type and P-type transistor pair located between a P-type transistor and an N-type transistor, the N-type and P-type transistor pair configured to provide bias signals to push-pull transistors in the second stage.
Another aspect of the disclosure provides a method for signal conversion including passively upconverting a wireless local area network (WLAN) communication signal, passively upconverting a Bluetooth (BT) communication signal, selectively amplifying the passively upconverted WLAN communication signal using a common amplifier, and selectively amplifying the passively upconverted BT communication signal using the common amplifier.
Another aspect of the disclosure provides a device including means for passively upconverting a wireless local area network (WLAN) communication signal, means for passively upconverting a Bluetooth (BT) communication signal, means for selectively amplifying the passively upconverted WLAN communication signal, and means for selectively amplifying the passively upconverted BT communication signal.
Another aspect of the disclosure provides a transmit circuit including Bluetooth (BT) communication circuitry comprising a passive BT upconverter (BT UPC) coupled to a load, wireless local area network (WLAN) communication circuitry comprising a passive WLAN upconverter (WLAN UPC) coupled to the load, and a voltage-mode baseband filter (BBF) having an operational transconductance amplifier (OTA) configured to provide a voltage input signal to the BT UPC.
In the figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as “102a” or “102b”, the letter character designations may differentiate two like parts or elements present in the same figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral encompass all parts having the same reference numeral in all figures.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
In many wireless radio transmitters, a power amplifier and matching circuitry (also referred to as a load) may be shared by multiple circuitry elements. For example, a power amplifier may be shared by a wireless local area network (WLAN) circuitry and by Bluetooth (BT) circuitry Advantages of sharing the same load by the upconverter/mixers (UPC) of both WLAN and Bluetooth transmit paths include reduced area and complexity. A Bluetooth UPC may be implemented as a Gilbert-cell based active mixer driven by a baseband filter (BBF) where the baseband filter operates in a current mode to operate the mixer. Bluetooth communication circuitry implements low bandwidth (BW) (e.g., DC to 5 Mhz max) with high gain resolution (to provide fine tuning of output power) from the baseband filter. In contrast, certain implementations of WLAN communication circuitry may use a passive UPC, which is driven by a voltage mode baseband filter. The input of the mixer is voltage and is typically implemented a transimpedance (TIA)-based filter. The TIA-based filter provides lower power consumption and high UPC linearity for WLAN communication. However, a TIA-based BBF imposes some challenges when the load (matching circuit and power amplifier) is shared by both WLAN circuitry (WLAN UPC for example) and by Bluetooth circuitry (BT UPC for example) because a passive UPC (for WLAN) uses a series inductive (L), capacitive (C) (LC) resonant network. In contrast, an active UPC (for BT) uses a parallel resonance LC network. Thus, a relatively large inductor is implemented by a WLAN UPC to provide the needed series LC resonance at 2.4 GHZ, resulting in the need for a small capacitor in parallel to achieve a parallel resonance in BT mode at the same frequency. This leads to a significant drawbacks in BT mode because the parallel resonance LC network becomes vulnerable to parasitics due to the high Q of the resonant network particularly at the BT bandwidth of DC to 5 MHz. In addition, the tunning becomes problematic and has a narrow adjustment range
A Bluetooth (BT) communication signal typically has a frequency bandwidth from 0 (DC) to approximately 2.5 MHz. However, certain transimpedance amplifier (TIA)-based baseband filters generally may not support such a frequency bandwidth, particularly at low frequencies close to DC Also, high linearity is also desired for a BT communication signal.
In the past, a TIA used Class AB operation and AC coupling capacitors to achieve such desired high linearity. However, large AC coupling capacitors cause a high-pass filter characteristic (e.g., a cutoff frequency of about 200 kHz even with a large capacitance), which may be challenging for BT signal upconversion
In an exemplary embodiment, a BT transmitter may use a passive upconverter (UPC) driven by a voltage mode TIA-based filter. In this arrangement, the BT upconverter can share the same LC load used by a WLAN upconverter. Such an arrangement can reduce the complexity of the shared load network including removing switches and some passive components and may improve the linearity of the WLAN upconverter and the BT upconverter.
In an exemplary embodiment, a TIA-based BBF having high resolution in gain step and the ability to process communications signals down to 0 Hz (DC) low bandwidth may be implemented with a passive BT upconverter
In an exemplary embodiment, the TIA-based baseband filter may implement a biasing methodology for biasing the second stage PMOS and NMOS transistors that does not use AC coupling capacitances between a first stage and a second stage of the TIA, thus eliminating the drawbacks of such AC coupling capacitances.
The wireless device 110 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device 110 may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a medical device, an automobile, a device configured to connect to one or more other devices (for example through the internet of things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device 110 may communicate with wireless communication system 120. Wireless device 110 may also receive signals from broadcast stations (e.g., a broadcast station 134) and/or signals from satellites (e.g., a satellite 150 in one or more global navigation satellite systems (GNSS)), etc.). Wireless device 110 may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 802.15, 5G, Sub6 5G, 6G, UWB, etc.
Wireless device 110 may support carrier aggregation, for example as described in one or more LTE or 5G standards. In some embodiments, a single stream of data is transmitted over multiple carriers using carrier aggregation, for example as opposed to separate carriers being used for respective data streams. Wireless device 110 may be able to operate in a variety of communication bands including, for example, those communication bands used by LTE, WiFi, 5G or other communication bands, over a wide range of frequencies. Wireless device 110 may also be capable of communicating directly with other wireless devices without communicating through a network.
In general, carrier aggregation (CA) may be categorized into two types-intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands.
In the example shown in
A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the example shown in
In the transmit path, the data processor 210 processes data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to the transmitter 230. In an exemplary embodiment, the data processor 210 includes digital-to-analog-converters (DAC's) 214a and 214b for converting digital signals generated by the data processor 210 into the I and Q analog output signals, e.g., I and Q output currents, for further processing. In other embodiments, the DACs 214a and 214b are included in the transceiver 220 and the data processor 210 provides data (e.g., for I and Q) to the transceiver 220 digitally.
Within the transmitter 230, lowpass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from lowpass filters 232a and 232b, respectively, and provide I and Q baseband signals. An upconverter 240 having upconversion mixers 241a and 241b upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 290 and provides an upconverted signal. A filter 242 filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 246 and transmitted via an antenna 248, or alternatively it can be sent to a separate transmit antenna different from a separate receive antenna. While examples discussed herein utilize I and Q signals, those of skill in the art will understand that components of the transceiver may be configured to utilize polar modulation.
In the receive path, antenna 248 receives communication signals and provides a received RF signal, which can be routed through duplexer or switch 246 and provided to a low noise amplifier (LNA) 252. The duplexer 246 is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. Alternatively, there may be a separate transmit antenna and separate receive antenna as mentioned above, in which case RX-to-TX isolation can be achieved through the limited coupling between the two antennas. In the case of separate RX and TX antennas, the RX antenna can be coupled directly to LNA 252. The received RF signal is amplified by LNA 252 and filtered by a filter 254 to obtain a desired RF input signal. Downconversion mixers 261a and 261b in a downconverter 260 mix the output of filter 254 with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by lowpass filters 264a and 264b to obtain I and Q analog input signals, which are provided to data processor 210. In the exemplary embodiment shown, the data processor 210 includes analog-to-digital-converters (ADC's) 216a and 216b for converting the analog input signals into digital signals to be further processed by the data processor 210. In some embodiments, the ADCs 216a and 216b are included in the transceiver 220 and provide data to the data processor 210 digitally.
In
In an exemplary embodiment, the RX PLL 282, the TX PLL 292, the RX LO signal generator 280, and the TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include common or shared LO signal generator circuitry to provide the TX LO signals and the RX LO signals. Alternatively, separate LO generator circuits may be used to generate the TX LO signals and the RX LO signals.
Wireless device 200 may support CA and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies and/or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. Those of skill in the art will understand, however, that aspects described herein may be implemented in systems, devices, and/or architectures that do not support carrier aggregation.
Certain components of the transceiver 220 are functionally illustrated in
The power amplifier 244 may comprise one or more stages comprising, for example, driver stages, power amplifier stages, or other components, that can be configured to amplify a communication signal on one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier 244 can be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and can be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.
In an exemplary embodiment in a super-heterodyne architecture, the filter 242, PA 244, LNA 252 and filter 254 may be implemented separately from other components in the transmitter 230 and receiver 250 (e.g., such a configuration may implement a millimeter wave integrated circuit (mmW-IC) or other super-heterodyne based architecture). An example super-heterodyne architecture is illustrated in
The wireless device 200a is an example of a heterodyne (or superheterodyne) architecture in which the upconverter 240 and the downconverter 260 are configured to process a communication signal between baseband and an intermediate frequency (IF). For example, the upconverter 240 may be configured to provide an IF signal to an upconverter 275. In an exemplary embodiment, the upconverter 275 may comprise upconversion mixer 276. The summing function 278 of upconverter 240 combines the I and the Q outputs and provides a combined signal to the mixer 276. The combined signal may be single ended or differential. The mixer 276 is configured to receive the IF signal from the upconverter 240 and TX RF LO signals from a TX RF LO signal generator 277, and provide an upconverted RF signal to phase shift circuitry 281. While PLL 292 is illustrated in
In an exemplary embodiment, components in the phase shift circuitry 281 may comprise one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor 210 over connection 294 and operate the adjustable or variable phased array elements based on the received control signals.
In an exemplary embodiment, the phase shift circuitry 281 comprises phase shifters 283 and phased array elements 287. Although three phase shifters 283 and three phased array elements 287 are shown for ease of illustration, the phase shift circuitry 281 may comprise more or fewer phase shifters 283 and phased array elements 287.
Each phase shifter 283 may be configured to receive the RF transmit signal from the upconverter 275, alter the phase by an amount, and provide the RF signal to a respective phased array element 287. Each phased array element 287 may comprise transmit and receive circuitry including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifters 283 may be incorporated within respective phased array elements 287.
The output of the phase shift circuitry 281 is provided to an antenna array 248. In an exemplary embodiment, the antenna array 248 comprises a number of antennas that typically correspond to the number of phase shifters 283 and phased array elements 287, for example such that each antenna element is coupled to a respective phased array element 287. In an exemplary embodiment, the phase shift circuitry 281 and the antenna array 248 may be referred to as a phased array.
In a receive direction, a receive signal may be phase shifted and an output of the phase shift circuitry 281 is provided to a downconverter 285. In an exemplary embodiment, the downconverter 285 may comprise a downconversion mixer 286. In an exemplary embodiment, the mixer 286 downconverts the receive RF signal provided by the phase shift circuitry 281 to an IF signal according to RX RF LO signals provided by an RX RF LO signal generator 279. The I/Q generation function 291 of downconverter 260 receives the IF signal from the mixer 286 and generates I and Q signals in downconverter 260, which downconverts the IF signals to baseband, as described above. While PLL 282 is illustrated in
In some embodiments, the upconverter 275, downconverter 285, and the phase shift circuitry 281 are implemented on a common IC. In some embodiments, the summing function 278 and the I/Q generation function 291 are implemented separate from the mixers 276 and 286 such that the mixers 276, 286 and the phase shift circuitry 281 are implemented on the common IC, but the summing function 278 and I/Q generation function 291 are not (e.g., the summing function 278 and I/Q generation function 291 are implemented in another IC coupled to the IC having the mixers 276, 286). In some embodiments, the LO signal generators 277, 279 are included in the common IC. In some embodiments in which phase shift circuitry is implemented on a common IC with 276, 286, 277, 278, 279, and/or 291, the common IC and the antenna array 248 are included in a module, which may be coupled to other components of the transceiver 220 via a connector. In some embodiments, the phase shift circuitry 281, for example, a chip on which the phase shift circuitry 281 is implemented, is coupled to the antenna array 248 by an interconnect. For example, components of the antenna array 248 may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuitry 281 via a flexible printed circuit or the chip may be mounted on the substrate.
In some embodiments, both the architecture illustrated in
The wireless device 200b in
In some embodiments, the upconverter 240, downconverter 260, and the phase shift circuitry 281 are implemented on a common IC. In some embodiments, the LO signal generators 280, 290 are included in the common IC. In some embodiments, the common IC and the antenna array 248 are included in a module, which may be coupled to other components of the transceiver 220 via a connector. In some embodiments, the phase shift circuitry 281, for example, a chip on which the phase shift circuitry 281 is implemented, is coupled to the antenna array 248 by an interconnect or both are mounted to a substrate. For example, components of the antenna array 248 may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuitry 281 via a flexible printed circuit or the integrated circuit may be mounted to an opposite side of the substrate. In some embodiments, multiple iterations of the upconverter 240 and downconverter 260 may be implemented to process multiple signals on different frequency bands.
In an exemplary embodiment, a baseband filter (BBF) 302 may be coupled to a WLAN upconverter 306 over differential signal connections 303 and 304. In an exemplary embodiment, the WLAN upconverter 306 is a passive upconverter. The WLAN upconverter 306 may be configured to receive a local oscillator (LO) signal (for example, from the LO signal generator 290 of
In an exemplary embodiment, a baseband filter 330 may be coupled to a BT upconverter 354 over differential signal connections 351 and 353. In an exemplary embodiment, the BT upconverter 354 is a passive upconverter. The BT upconverter 354 may be configured to receive a local oscillator (LO) signal (for example, from the LO signal generator 290 of
The baseband filter 330 may be implemented using a transimpedance amplifier (TIA)-based baseband filter having an operational transconductance amplifier (OTA) as will be described herein. The OTA may also be referred to as an operation amplifier (opamp). In an exemplary embodiment, the baseband filter 330 comprises an operational amplifier 340 configured to receive differential current input signals I+ and I− on differential signal connections 332 and 334, respectively, and to provide differential voltage output signals V+ and V− on differential signal connections 344 and 346, respectively. This arrangement is generally referred to as voltage mode.
In an exemplary embodiment, the output of the operational amplifier 340 on connections 344 and 346 is provided to attenuators 347 and 348, respectively. The output of the attenuators, Vo+ and Vo−, is provided over differential signal connections 351 and 353 to the BT upconverter 354.
In an exemplary embodiment, the baseband filter 330 also comprises a filter network 362 having a capacitance 338 and a resistance 339, and a filter network 364 having a capacitance 341 and a resistance 342.
In an exemplary embodiment, the values of the capacitances 338 (Cf) and 341 (Cf) and the values of the resistances 339 (Rf) and 342 (Rf) are chosen such that baseband filter 330 may have a cutoff frequency of Fcutoff_freq=½IIRfCf.
In an exemplary embodiment, the TIA-based baseband filter 330 may be optimized to drive the BT upconverter 354.
In an exemplary embodiment, because both the WLAN upconverter 306 and the BT upconverter 354 are passive upconverters, the output of the WLAN upconverter 306 and the output of the BT upconverter 354 may be coupled to an input of the matching network 315 without additional switching circuitry used in the area noted by reference numeral 308 (e.g., the outputs are simultaneously coupled to the load 310 during operation although the BT upconverter 354 and the WLAN upconverter 306 are not both simultaneously operating). In some aspects the output of the BT upconverter 354 is directly coupled to an input of the matching network 315 (e.g., no additional switching circuitry) and in some aspects the output of the WLAN upconverter 306 is directly coupled to an input of the matching network 315 (e.g., no additional switching circuitry).
As used herein, the term connected generally refers to electrical connection that may or may not be a direct connection. For example, the term “connected” may refer to elements being electrically coupled and may include intervening circuit elements (capacitors or otherwise) while maintaining the described functionality of the circuit.
In an exemplary embodiment, the first stage 410 generally comprises a current mirror circuit 411 connected to a gate of transistor 414 over a connection 412. A source of the transistor 414 may be connected to a system voltage, VDD, over connection 417 and a drain of the transistor 414 may be connected to a node 413 over connection 418. The node 413 may be formed by connecting the source of a transistor 415 to a source of a transistor 416. A gate of the transistor 415 may be configured to receive a differential input signal, Vin+. A gate of the transistor 416 may be configured to receive a differential input signal, Vin−. The circuit 400 generally comprises a current to voltage amplifier and as such, the operational amplifier 340 in
A drain of the transistor 415 may be connected to a node 445 and a drain of the transistor 416 may be connected to a node 444. The transistors 414, 415 and 416 may be P-type devices in an exemplary embodiment.
In an exemplary embodiment, the first stage 410 also comprises transistors 422, 423, 424 and 425. A source of each of the transistors 422, 423, 424 and 425 may be connected to the system voltage, VDD, over connection 417. A drain of the transistor 422 may be connected to a drain of the transistor 423 at a node 435. A drain of the transistor 424 may be connected to a drain of the transistor 425 at a node 438. A bias signal, Vb3, may be applied to a gate of the transistor 422 and to a gate of the transistor 425. A bias signal, Vcmfb (common-mode feedback voltage), may be applied to a gate of the transistor 423 and a gate of the transistor 424. In an exemplary embodiment, the transistors 422, 423, 424 and 425 may be P-type devices.
In an exemplary embodiment, the first stage 410 also comprises transistors 431, 432, 433 and 434. A source of the transistor 431 may be connected to a drain of the transistor 433; and a source of the transistor 432 may be connected to a drain of the transistor 434. A source of the transistor 433 may be connected to a system ground (or some other reference potential), and a source of the transistor 434 may be connected to a system ground, (or some other reference potential). In an exemplary embodiment, the transistors 431, 432, 433 and 434 may be referred to as tail transistor devices because they flow what may be referred to as a tail current. A bias signal, Vb1, may be applied to a gate of the transistor 433 and a gate of the transistor 434. A bias signal, Vb2, may be applied to a gate of the transistor 431 and a gate of the transistor 432. The circuitry that generates the bias signals Vb1, Vb2 and Vb3 is shown and described in greater detail in
A drain of the transistor 431 may be connected to a node 441 and a drain of the transistor 432 may be connected to a node 443. In an exemplary embodiment, the transistors 431, 432, 433 and 434 may be N-type devices.
In an exemplary embodiment, the transistors 415 and 416 are considered folded, and the transistors 422, 423, 424 and 425, and the transistors 431, 432, 433 and 434 form a cascode architecture, where the transistors 415 and 416, and the transistors 422, 423, 424 and 425, and the transistors 431, 432, 433 and 434 are considered a folded cascode structure.
In an exemplary embodiment, PMOS-NMOS transistor pairs (PMOS-NMOS pairs) 450 may be formed by transistors 426, 427, 428 and 429. A source of the transistor 426 may be connected to a drain of the transistor 427 at a node 446; and a drain of the transistor 426 may be connected to a source of the transistor 427 at a node 439. A source of the transistor 429 may be connected to a drain of the transistor 428 at a node 447; and a drain of the transistor 429 may be connected to a source of the transistor 428 at a node 442.
The node 446 may be connected to the node 437, which may be connected to the node 435. The node 447 may be connected to the node 436, which may be connected to the node 438. The node 439 may be connected to the node 441 and the node 442 may be connected to the node 443. In an exemplary embodiment, the node 437 and the node 436 may be referred to as “node p” having a voltage Vpab; and the node 441 and the node 443 may be referred to as “node n” having a voltage Vnab. In an exemplary embodiment, the transistors 426 and 429 may be P-type devices and the transistors 427 and 428 may be N-type devices. A bias signal Vfp may be applied to the gate of the transistor 426 and the gate of the transistor 429; and a bias signal Vfn may be applied to the gate of the transistor 427 and the gate of the transistor 428. The circuitry that generates the bias signals Vfp and Vfn will be described in
In an exemplary embodiment, the second stage 460 comprises transistors 461, 462, 475 and 476. A source of the transistor 461 and a source of the transistor 462 may be connected to the system voltage, VDD, over connection 417. A drain of the transistor 461 may be connected to a drain of the transistor 476, and a drain of the transistor 462 may be connected to a drain of the transistor 475. A gate of the transistor 461 may be connected to the drain of the transistor 461 through a capacitance 463 and a resistance 464. A gate of the transistor 462 may be connected to the drain of the transistor 462 through a capacitance 468 and a resistance 469. The drain of the transistor 461 may also be connected to a node 466 through a capacitance 465, and the drain of the transistor 462 may also be connected to the node 466 through a capacitance 467. The node 466 may be connected to a node 476. A differential output signal, Vo+, may be taken from the node 472 through a resistance 471 and a differential output signal, Vo−, may be taken from the node 474 through a resistance 473. The node 472 in
A drain of the transistor 476 may be connected to a gate of the transistor 476 through a resistance 480 and a capacitance 479. A drain of the transistor 475 may be connected to a gate of the transistor 475 through a resistance 482 and a capacitance 481. In an exemplary embodiment, the transistors 475 and 476 are N-type devices.
A bias signal, Vpab, may be applied to the gate of the transistor 461 from the node 437 over connection 449, and may be applied to the gate of the transistor 462 from the node 436 over connection 448.
A bias signal, Vnab, may be applied to the gate of the transistor 476 from the node 441 over connection 452, and may be applied to the gate of the transistor 475 from the node 443 over connection 451.
In an exemplary embodiment, the common-mode feedback circuit 490 comprises transistors 491, 492, 493, 494, 496 and 497. A source of the transistor 491 and a source of the transistor 492 are connected to the system voltage, VDD, over connection 417. A drain of the transistor 491 may be connected to a drain of the transistor 493, and a drain of the transistor 492 may be connected to a drain of the transistor 494. A source of the transistor 493 may be connected to a drain of the transistor 496 and a source of the transistor 494 may be connected to a drain of the transistor 497.
In an exemplary embodiment, the drain and gate of the transistor 491 are connected together, and the drain and gate of the transistor 492 are connected together. A bias signal, Vcmfb (common-mode feedback), is applied to the gate of the transistor 491 over connection 499.
A common mode output signal, Vcmo (common mode voltage), is applied to the gate of the transistor 493 from the node 476 over connection 498. A common mode reference signal, Vcmref, is applied to the gate of the transistor 494. The bias signal, Vb1, is applied to the gate of the transistor 496 and the gate of the transistor 497 at a connection 499. In an exemplary embodiment, the transistors 491 and 492 may be P-type devices and the transistors 493, 494, 496 and 497 may be N-type devices.
In an exemplary embodiment, the transistors 426, 427, 428 and 429 in the PMOS-NMOS pairs 450 have a channel length that is longer than a channel length of the other transistors in the first stage 410. For example, the impedance looking at the transistors 426, 427, 428 and 429 connected to nodes 437/436 (Vpab) and nodes 441/443 (Vnab) remains sufficiently high, while maintaining the transistors 431 (Mn1) and 433 (Mn2) and the transistors 432 (Mn3) and 434 (Mn4) in the saturation region, to provide sufficient gain from the first stage 410. The bias of the transistors 431/432 (Mn1/Mn3) and the transistors 433/434 (Mn2/Mn4) are configured such that the voltage at nodes 441/443 (Vnab), which is gate voltage of the second stage NMOS transistors 475 and 476, is low enough to maintain low current consumption in the NMOS devices (transistors 475 and 476) in the second stage 460, but also keeps the transistors 431 (Mn1) and 433 (Mn2) and the transistors 432 (Mn3) and 434 (Mn4) in the saturation region. For example, it is desirable to keep current in the second stage 460 low to reduce power consumption. However, the voltage at the nodes 441 and 443 (Vnab) is also the gate voltage of the second stage transistors 475 and 476, so increasing Vnab increases second stage current. In some circumstances, Vnab can increase too high. Therefore, the size of the transistors 431 and 433 (and 432 and 434) should be relatively large so that the voltage Vnab does not get too high and increase the current through the second stage 460.
In an exemplary embodiment, the transistors 426/427 (Mfp1/Mfn1) and the transistors 428/429 (Mfn2/Mfp2) act as push-pull PMOS-NMOS pairs while in class AB operation, without using any AC coupling capacitors between the first stage 410 and the second stage 460. The term push-pull refers to the arrangement where one transistor is sourcing current to a load and the other transistor is sinking current to a load. In this manner, high linearity, and good gain resolution are not tied to power consumption in the circuit 400 and are not compromised by AC coupling capacitances. The circuit arrangement shown in
The PMOS-NMOs pairs 450 in the first stage 410 has PMOS-NMOS pairs 426/427 (Mfn1/Mfp1) and PMOS-NMOS pairs 428/429 (Mfn2/Mfp2) between NMOS stages (transistors 431, 432, 433 and 434) and PMOS stages (cascode transistors 422, 423, 424 and 425) to bias the NMOS and PMOS transistors (transistors 461/462 and 476/475) in the second stage 460 in class AB mode. The channel length of the PMOS-NMOS transistor pairs (426/427 and 428/429) is sufficiently long such that the impedance looking towards nodes 441 and 443 (node n (Vnab)) and nodes 437 and 436 (node p (Vpab)) remains high so that the gain of the first stage 410 does not degrade significantly. The bias of the transistor 431 (Mn1) and 432 (Mn3) and 433 (Mn2) and 434 (Mn4) is such that Vnab should be limited to maintain low power consumption in the second stage 460 but still keep the transistor 431 (Mn1) and the transistor 433 (Mn2) in the saturation region, as described above
In an exemplary embodiment, the current consumption of the circuit 400 remains below 4 mA from a 1.2V supply in order to be comparable with a traditional current mode baseband filter. The bias voltages Vfp and Vfn can be generated from the same current mirror source as Vb3. Therefore, the bias voltages Vfp and Vfn of the PMOS-NMOS pair (426/427 and 428/429), should be such that:
Vfn≥V
b1
−V
th-Mn2
+V
dssat-Mn1
+V
gs-Mfn1; and
Vfp≤V
sdsat-Mp1
−V
sg-Mfp1.
The term Vb1 refers to the gate voltage of the transistors 433 and 434; the term Vth-Mn2 refers to the gate voltage of the transistor 433; the term Vdssat-Mn1 refers to the drain-source saturation voltage of the transistor 431; the term Vgs-Mfn1 refers to the gate-source voltage of the transistors 427 and 428; the term Vsdsat-Mp1 refers to the source-drain saturation voltage of the transistor 415; and the term Vsg-Mfp1 refers to the source-gate voltage of the transistors 426 and 429.
Another challenge in the architecture is to stabilize the common-mode feedback loop. The common-mode feedback circuit 490 attempts to regulate the output DC bias voltage which is the voltage that Vcmref sets. The voltage, Vcmref, is provided by a reference voltage generator (not shown). In an exemplary embodiment, the reference voltage, Vcmref, may be approximately VDD/2. The common-mode feedback circuit 490 may also be referred to as an error amplifier and sets the voltage Vcmfb, which controls the voltage at node p (Vpab, nodes 437 and 436). The common-mode feedback circuit 490 is designed in such a way that Vpab and Vnab provide sufficient headroom to keep all transistors in the first stage 410 in saturation. The degeneration resistor 495 (Rdeg) improves the stability of the common-mode loop but degrades the gain of the common-mode feedback circuit 490. In an exemplary embodiment, the common-mode feedback circuit 490 compares the voltage, Vcmo at node 476 with the reference voltage, Vcmref, and then adjusts the voltage, Vcmfb, accordingly. In an exemplary embodiment, the gain of the circuit 400 should remain approximately 30 dB to reduce the variation in Vcmo over temperature and process variation while keeping the amplifier phase margin at or near 45 degrees.
For example, if a disturbance such as a change in supply voltage, variation in signal input strength, etc., causes the voltage Vcmo (which is Vo++Vo−) to increase, the current through the transistor 493 decreases, which in turn causes the voltage Vcmfb, to decrease. This causes the voltage at node 437 and node 436 to increase (because the gate and drain of the transistors 422, 432, 424 and 425 are in opposite phase), which means the gate source voltage, Vgs, of the PMOS transistors 461, 462 in the second stage 460 gets lowered, and the output voltages at node 472 and node 474 are decreased. Thus, any change in the output voltage, Vo+ and Vo−, is adjusted by the common mode feedback loop. In this manner, any change in the output voltages Vo+ and Vo−, causes the common mode feedback circuit 490 to adjust the common mode feedback voltage Vcmfb in such a way that the values of Vo+ and Vo− are returned to their original value which is close to Vdd/2. Thus, the DC voltage at node 472 and node 474 remains fixed by the common-mode feedback circuit 490.
The TIA-based filter and passive UPC architecture shows comparable linearity and gain resolution compared to a current-based RC filter and active UPC. In one example, the gain resolution can be achieved by implementing the attenuators 347 and 348 (
The current source 512 (Ib2) is connected to a drain of the transistor 514. The source of the transistor 514 is connected to the drain of the transistor 516 and the source of the transistor 516 is connected to ground.
The current source 522 (Ib1) is connected to a drain of the transistor 518. The source of the transistor 518 is connected to ground.
The gate and drain of the transistors 514, 516 and 518 are connected together. The gate of the transistors 516 and 518 provide the bias voltage Vb1 on connection 526. The gate of the transistor 514 provides the bias voltage Vb2 on connection 524. The bias voltage Vb1 is applied to the gates of the transistors 433 and 434 (
In an exemplary embodiment, the width (channel length) of the transistors 514, 516 and 518 are ratioed properly with respect to the transistors 431 and 433 (
In an exemplary embodiment, the bias circuit 550 may be used to generate the bias voltages Vfn, Vfp and Vb3 in
In an exemplary embodiment, the sources of the transistors 552, 558 and 566 are connected to system voltage, VDD. The drain of the transistor 552 is connected to the drain of the transistor 554. The source of the transistor 554 is connected to the drain of the transistor 556. The source of the transistor 556 is connected to ground. The drain and gate of the transistor 554 are connected together.
The drain of the transistor 558 is connected to the source of the transistor 562. The drain of the transistor 562 is connected to the drain of the transistor 564. The source of the transistor 564 is connected to ground. The drain and gate of the transistor 562 are connected together.
The drain of the transistor 566 is connected to the current source 576 (Ib3).
The bias voltage Vfn appears at the connection 568 between the drain of the transistor 552 and the drain of the transistor 554. The bias voltage Vfp appears at the connection 572 between the drain of the transistor 562 and the drain of the transistor 564. The bias voltage Vb3 appears at the connection 574 at the drain of the transistor 566. The bias voltage Vfn is applied to the gates of the transistors 427 and 428. The bias voltage Vfp is applied to the gates of the transistors 426 and 429. The bias voltage Vb3 is applied to the gate of the transistor 414 and to the gates of the transistors 422 and 425.
In an exemplary embodiment, the currents through the three circuit branches (552/554/556; 558/562/564; and 566/576) are set by sizing the transistors that satisfies Vfn and Vfp as follows.
V
fn
≥V
b1
−V
th-Mn2
+V
dssat-Mn1
+V
gs-Mfn1
V
fp
≤V
sdsat-Mp1
−V
sg-Mfp1
The transistors 554, 556, 558 and 562 are configured as diode connected loads and are acting as active resistors. Therefore, the voltage of Vfn and Vfp can be set by proper sizing of the current source transistors 552 (P3) and 564 (N3) and the diode connected transistors 554 (N1) and 556 (N2); and 558 (P1) and 562 (P2).
In block 602, a WLAN communication signal is passively upconverted. For example, the WLAN upconverter 306 can passively upconvert a WLAN communication signal provided by the baseband filter 302.
In block 604, a BT communication signal is passively upconverted. For example, the BT upconverter 354 can passively upconvert a BT communication signal provided by the baseband filter 330.
In block 606, the passively upconverted WLAN communication signal is selectively amplified using a common amplifier. For example, the amplifier 320 may amplify the WLAN communication signal provided by the WLAN upconverter 306.
In block 608, the passively upconverted BT communication signal is selectively amplified using a common amplifier. For example, the amplifier 320 may amplify a BT communication signal provided by the BT upconverter 354.
The apparatus 700 may also comprise means 704 for passively upconverting a BT communication signal. In certain embodiments, the means 704 for passively upconverting a BT communication signal can be configured to perform one or more of the functions described in operation block 604 of method 600 (
The apparatus 700 may also comprise means 706 for selectively amplifying the passively upconverted WLAN communication signal. In certain embodiments, the means 706 for selectively amplifying the passively upconverted WLAN communication signal can be configured to perform one or more of the functions described in operation block 606 of method 600 (
The apparatus 700 may also comprise means 708 for selectively amplifying the passively upconverted BT communication signal. In certain embodiments, the means 708 for selectively amplifying the passively upconverted BT communication signal can be configured to perform one or more of the functions described in operation block 608 of method 600 (
Implementation examples are described in the following numbered clauses:
The circuit architecture described herein described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.
An apparatus implementing the circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
Although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.
