Patent Application
20240322774
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-048975, filed on Mar. 24, 2023; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to an amplifier circuit and a driver circuit.
There is a conventionally known auto-zero amplifier, as a low-offset amplifier circuit, including a main amplifier, a null amplifier (automatic correction amplifier), a first capacitor (capacitance) that holds an offset correction voltage of the null amplifier, and a second capacitor that holds an offset correction voltage of the main amplifier.
The auto-zero amplifier has an operation mode of an auto-zero phase in which the offset correction voltage of the null amplifier is acquired, and an operation mode of an amplifier phase in which an actual operation as an amplifier circuit is performed while correcting the offset voltage of the main amplifier by using the null amplifier operating as an ideal amplifier by correcting the offset correction voltage.
In the auto-zero amplifier, the charges held in the first capacitor and the second capacitor are shifted with time due to leakage current or the like. Thus, in general, the auto-zero phase and the amplifier phase are switched at certain time intervals to refresh and update the charges of the first capacitor and the second capacitor.
However, in the conventional technology, due to the generation of noise based on the switching operation at the time of switching between the auto-zero phase and the amplifier phase or the fact that the null amplifier does not actually operate as an ideal amplifier, there is a possibility that characteristic degradation occurs when the auto-zero amplifier is used for a high-precision circuit using a minute signal or the like.
In general, according to one embodiment, an amplifier circuit is an auto-zero amplifier including a main amplifier, a null amplifier, and a capacitor connected to an output terminal of the null amplifier without interposing a switch for switching an operation mode provided at the output terminal.
Exemplary embodiments of an amplifier circuit and a driver circuit will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.
The auto-zero amplifier 10 includes a main amplifier 11, a null amplifier 12, a first switch 13, a second switch 14, a third switch 15, a fourth switch 16, a first capacitor 17, a second capacitor 18, a third capacitor 19, a first input terminal Tinp, a second input terminal Tinn, and an output terminal Tout.
The main amplifier 11 has a non-inverting input terminal connected to the first input terminal Tinp, an inverting input terminal connected to the second input terminal Tinn, and an output terminal connected to the output terminal Tout.
The null amplifier 12 has a non-inverting input terminal connectable to the second input terminal Tinn via the first switch 13 and connectable to the first input terminal Tinp via the second switch 14, an inverting input terminal connected to the second input terminal Tinn, an output terminal connected to one end of the third switch 15, one end of the fourth switch 16, and one end of the third capacitor 19, and an offset correction voltage input terminal C2 connected to the other end of the third switch 15.
The first switch 13 has one end connected to the second input terminal Tinn and the other end connected to the non-inverting input terminal of the null amplifier 12. The second switch 14 has one end connected to the first input terminal Tinp and the other end connected to the non-inverting input terminal of the null amplifier 12.
The third switch 15 has one end connected to the output terminal of the null amplifier 12 and the other end connected to one end of the first capacitor 17. The fourth switch 16 has one end connected to the output terminal of the null amplifier 12 and the other end connected to one end of the second capacitor 18 and the offset correction voltage input terminal C1 of the main amplifier 11.
The first capacitor 17 has one end connected to the offset correction voltage input terminal (loop terminal) C2 of the null amplifier 12 and the other end being grounded. The second capacitor 18 has one end connected to the offset correction voltage input terminal (loop terminal) C1 of the main amplifier 11 and the other end being grounded. The third capacitor 19 has one end connected to the output terminal of the null amplifier 12 and the other end being grounded.
Here, prior to the description of a first embodiment, a comparative example will be described.
An auto-zero amplifier 10P of the comparative example of
Next, an operation of the auto-zero amplifier 10P of the comparative example will be described. The operation modes of the auto-zero amplifier 10P include an auto-zero phase mode in which each unit is connected as illustrated in
In the auto-zero phase mode, as illustrated in
As a result, the null amplifier 12 is in a buffer state, and the non-inverting input terminal and the inverting input terminal of the null amplifier 12 are short-circuited, and thus, the offset correction voltage of the null amplifier 12 itself is held in the first capacitor 17.
In this case, since the null amplifier 12 is excluded from the operation loop to the main amplifier 11, the main amplifier 11 performs offset correction using the charge (voltage) held in the second capacitor 18 and operates.
On the other hand, in the amplifier phase mode, as illustrated in
This causes the null amplifier 12 to operate using the voltage held in the first capacitor 17. Thus, the null amplifier 12 in the state corrected by the offset correction voltage confirmed in the auto-zero phase mode theoretically operates as an ideal amplifier not affected by the offset, and it operates while correcting the offset voltage of the main amplifier 11.
In the auto-zero amplifier 10P in practice, a leakage current or the like is present in the first capacitor 17 and the second capacitor 18, and the charges held by the first capacitor 17 and the second capacitor 18 holding the offset correction voltage fluctuate with time due to the leakage current or the like, and eventually, the offset correction voltage fluctuates with time.
Thus, in a typical auto-zero amplifier, the offset voltage correction is more reliably performed by switching between the auto-zero phase mode and the amplifier phase mode at certain time intervals to refresh and update the capacitive charges of the two capacitors.
In this case, the output terminal Tout of the auto-zero amplifier 10P is connected to the second input terminal Tinn to form a feedback loop, with which the auto-zero amplifier 10P serves as a buffer amplifier. Here, it is assumed that a freely-selected power supply 30 having a predetermined voltage is connected to the first input terminal Tinp and the operation is checked.
When the switch to be in the ON state is switched from one of the third switch 15 and the fourth switch 16 to the other switch, it is not possible to acquire a correct offset correction voltage with both the third switch 15 and the fourth switch 16 being in the ON state. Thus, there is a possibility that the offset correction cannot be performed correctly, the reliability of the offset correction voltage is lowered, and the characteristics of the buffer amplifier degrade.
For this reason, it is necessary to reliably provide a period during which both the third switch 15 and the fourth switch 16 are in a high-impedance state (OFF state), but there has been a possibility that the following problem is caused by lengthening the period during which both the third switch 15 and the fourth switch 16 are in the high-impedance state (OFF state).
Shifting to the period during which both the third switch 15 and the fourth switch 16 are off means that the connection of the load suddenly disappears for the null amplifier 12 (high-impedance state), and thus, the voltage itself of the output signal Aout of the null amplifier 12 also suddenly changes and greatly fluctuates.
More specifically, as illustrated in (E) of
In addition, as described above, when an auto-zero phase PH1 is switched to the amplifier phase PH2, the influence of the voltage fluctuation of the output signal Aout of the null amplifier 12 immediately before the third switch 15 completely shifts to the OFF state occurs. More specifically, for example, as indicated by broken line ellipses B11 and B12 in (D) of
When the auto-zero phase PH1 is switched to the amplifier phase PH2, the waveform fluctuation occurs in the same manner in an input signal VIN−, and for example, as illustrated by broken line ellipses A11 and A12 in (C) of
In this manner, the auto-zero amplifier 10P of the comparative example has problems, for example, noise of voltage fluctuation in VIN− is generated at the time of switching from the auto-zero phase to the amplifier phase as described above, and a difference in VIN− voltage is generated between the auto-zero phase and the amplifier phase which causes the offset voltage correction to deteriorate and not to ideally operate, and characteristic degradation occurs when the auto-zero amplifier is used in a high-precision circuit using a minute signal or the like.
Next, the operation of the auto-zero amplifier 10 according to the embodiment will be described. As described above, the auto-zero amplifier 10 of
The operation will be described below. In the auto-zero phase mode, the differential input of the null amplifier 12 is short-circuited by the first switch 13, and the output terminal of the null amplifier 12 causes the third switch 15 to enter the ON state, whereby the null amplifier 12 enters the buffer state.
Then, the offset correction voltage of the null amplifier 12 itself is held in the first capacitor 17 and the third capacitor 19, and the offset correction voltage of the null amplifier 12 itself is acquired and then corrected.
In this case, in the connection state as illustrated in
This causes the null amplifier 12 to operate using the offset correction voltage held in the first capacitor 17.
The null amplifier 12 whose offset voltage has been corrected in the auto-zero phase described above can operate as an ideal amplifier, and it operates while correcting the offset voltage of the main amplifier 11.
As described in the description of the problems of the comparative example, in the auto-zero amplifier 10 of the embodiment as well, the charges held in the first capacitor 17, the second capacitor 18, and the third capacitor 19 fluctuate with time because of leakage current or the like.
Thus, also in the present embodiment, the auto-zero phase mode and the amplifier phase mode are switched at certain time intervals, and the charges of the first capacitor 17, the second capacitor 18, and the third capacitor 19 are refreshed and updated in the same manner as in the comparative example.
In this manner, in the case of the circuit configuration of the embodiment, the third capacitor 19 is always connected to the output terminal of the null amplifier 12, and unlike the comparative example, the load of the null amplifier 12 does not suddenly disappear even when the third switch 15 and the fourth switch 16 are switched, which can stably operate the null amplifier 12.
Thus, a problem of generation of noise of voltage fluctuation in VIN− at the time of switching from the auto-zero phase to the amplifier phase is not caused, and the offset voltage correction does not deteriorate due to a difference in the VIN− voltage between the auto-zero phase and the amplifier phase. Therefore, it can be seen that this configuration realizes an ideal operation and can prevent characteristic degradation even when the auto-zero amplifier is used in a high-precision circuit that handles a minute signal or the like.
Next, the operation of the embodiment will be described more specifically.
In the comparative example, as illustrated in (C) of
In the present embodiment, even when the third switch 15 and the fourth switch 16 connected to the output terminal of the null amplifier 12 are switched at the time of switching the phases, the third capacitor 19 is always connected to the output terminal of the null amplifier 12, and thus, the voltage state in each phase mode can be held no matter whether the phase is the auto-zero phase mode or the amplifier phase mode.
That is, since the third capacitor 19 is always connected to the output terminal of the null amplifier 12 even when both the third switch 15 and the fourth switch 16 are in the OFF state, the output terminal of the null amplifier 12 does not enter the high-impedance state, and it is possible to prevent a rapid change in the load of the output terminal of the null amplifier 12.
More specifically, as illustrated in (E) of
When the auto-zero phase PH1 is switched to the amplifier phase PH2, it is possible to reduce the voltage fluctuation of the output signal Aout of the null amplifier 12 immediately before the third switch 15 completely shifts to the OFF state. Thus, as indicated by broken line ellipses B1 and B2 in (D) of
In the same manner, as illustrated in (C) of
In this manner, the auto-zero amplifier 10 according to the embodiment eliminates a problem of generation of noise of voltage fluctuation in the input signal VIN− at the time of switching from the auto-zero phase to the amplifier phase and a problem of generation of a difference in the voltage of the input signal VIN− between the auto-zero phase and the amplifier phase and deterioration of the offset voltage correction with which an ideal operation is not performed as in the comparative example.
Thus, the auto-zero amplifier can perform highly reliable processing without causing characteristic degradation when it is used in a high-precision circuit that handles a minute signal or the like. The noise generated in the input signal VIN− in a short period at the time of phase switching as illustrated in (C) of
In the configuration of the auto-zero amplifier illustrated in
In the above description, the auto-zero amplifier configuration example of
In the above description, the state in which both the third switch 15 and the fourth switch 16 are enter the OFF state when the auto-zero phase and the amplifier phase are switched has not been described in detail, but the third capacitor 19 is always connected to the output terminal of the null amplifier 12.
Thus, even when the period during which both the third switch 15 and the fourth switch 16 are in the OFF state is extended, the output voltage itself of the output terminal of the null amplifier 12 does not rapidly change. Thus, the period during which both the third switch 15 and the fourth switch 16 are in the OFF state can be easily set long, and highly reliable switching can be performed.
A unity gain frequency F, which is the frequency at which the gain of the null amplifier 12 in the auto-zero phase according to the embodiment is 1 (hereinafter, referred to as a unity gain frequency), is represented by the following equality, where gm is a transconductance of the null amplifier 12, C3 is a capacitance of the third capacitor 19 continuously connected over time to the output of the null amplifier 12 without interposing a switch or the like, and C1 is a capacitance of the first capacitor 17.
The unity gain frequency F of the null amplifier is desirably higher than the switching frequency fm between the mode of the auto-zero phase and the mode of the amplifier phase. This is because it is necessary to correctly hold the voltage to be used for the offset correction in the auto-zero phase in the first capacitor 17 and the third capacitor 19.
In the above case, the relational expression between the switching frequency fm and the unity gain frequency is as follows.
It is preferable to set the first capacitor 17 mainly in consideration of setting a capacitance value such that the charge held in the period of the amplifier phase is not shifted by a leakage current or the like to affect the offset correction.
In addition, setting the capacitance C3 of the third capacitor 19 to a value that holds the following expression can improve offset voltage correction.
The frequency characteristic of the amplifier phase mode of the auto-zero amplifier 10 of the embodiment needs to secure a predetermined phase margin so as not to oscillate, and by setting the value of the capacitance value C3 of the third capacitor 19 continuously connected over time to the output of the null amplifier 12 without interposing a switch or the like in such a manner as to be able to secure the phase margin, it is possible to preferably control voltage fluctuation and the like at the time of switching from the auto-zero phase to the amplifier phase.
In the above description, the auto-zero amplifier as the amplifier circuit has been described. However, a driver circuit can be configured using the amplifier circuit as a circuit that detects a control amount.
For example, it is possible to configure a motor driver circuit that performs feedback control of a motor acting as an external load and drives the motor by connecting the motor to the output terminal Tout of the auto-zero amplifier as an amplifier circuit and inputting a detection signal of a current detector that detects a current value flowing through the motor or a voltage detector that detects a voltage value applied to the motor directly or via a bias circuit to an input terminal (first input terminal Tinp, second input terminal Tinn) of the auto-zero amplifier.
Employing such a configuration enables the driver circuit to acquire the feedback amount with high accuracy and to perform feedback control with high accuracy.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-048975 | Mar 2023 | JP | national |
