Patent Application
20230095506
An embodiment disclosed in the present specification and the like relates to, for example, an amplifier circuit, a differential amplifier circuit, a reception circuit, and a semiconductor integrated circuit used for a continuous time linear equalizer (CTLE).
The CTLE is an input amplifier circuit of a serializer/deserializer (SerDes) reception circuit used for a high-speed interface for a network or a data center, and is used as a loss compensation circuit in a transmission path. The conventional CTLE uses a source degeneration equalizer.
Conventional techniques are described in Japanese Patent Application Laid-Open No. 9-74340, US Patent Application Publication No. 2008/24228, and U.S. Pat. No. 5,363,065.
However, the conventional CTLE using the source degeneration equalizer enables a boost gain amplification function using an inductor element (coil). Therefore, the circuit size (area) is large. In addition, the gain is nonlinear due to variations in factors such as resistance and transconductance in the circuit.
In recent years, due to the miniaturization of the CMOS technology, further reduction in power consumption of the CTLE and further reduction in area of the CTLE are required. In addition, high linearity is required due to multi-leveling of the signal amplitude level.
One of the problems to be solved by the embodiments disclosed in the present specification and the like is to provide an amplifier circuit, a differential amplifier circuit, a reception circuit, and a semiconductor integrated circuit that enable a boost gain amplification function and have a small area while maintaining linearity of a gain.
An amplifier circuit according to an embodiment includes: a first circuit including a first transistor connected between an input node through which an input current flows and a reference potential node, the first transistor having a gate electrode connected to the input node; a second circuit including a low-pass filter circuit and a second transistor connected in parallel to the first transistor between the input node and the reference potential node, the second transistor having a gate electrode connected to the gate electrode of the first transistor via the low-pass filter circuit; and a third circuit including a third transistor connected between an output node through which an output current flows and the reference potential node, the third circuit having a gate electrode connected to the gate electrode of the first transistor.
Hereinafter, an amplifier circuit, a differential amplifier circuit, a reception circuit, and a semiconductor integrated circuit according to embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited by this embodiment. In the following description, the same reference numerals are given to portions common to the drawings, and a detailed description thereof will be omitted.
As illustrated in
The input node 51 includes a wiring through which an input current II flows. The output node 61 includes a wiring through which an output current Io flows. The reference potential node 31 includes a wiring to which a reference potential Vbasis (for example, ground potential) is supplied. Note that the potential Vin of the input node 51 and the reference potential Vbasis have a relationship of Vin>Vbasis.
The first circuit 11 includes a first transistor 111. The first transistor 111 is, for example, an n-channel transistor, and is connected between the input node 51 through which the input current II flows and the reference potential node 31. The gate electrode of the first transistor 111 is connected to the input node 51. The drain electrode and source electrode of the first transistor 111 are connected to the input node 51 and the reference potential node 31, respectively. The size parameter of the first transistor 111 is a. The first transistor 111 is an example of a first transistor.
The second circuit 12 includes a second transistor 121 and a low-pass filter circuit 127. The second transistor 121 is, for example, an n-channel transistor, and is connected in parallel to the first transistor 111 between the input node 51 through which the input current II flows and the reference potential node 31. The gate electrode of the second transistor 121 is connected to the gate electrode of the first transistor 111 via the low-pass filter circuit 127. The drain electrode and source electrode of the second transistor 121 are connected to the input node 51 and the reference potential node 31, respectively. The size parameter of the second transistor 121 is b. The second transistor 121 is an example of a second transistor.
The low-pass filter circuit 127 is a low-pass filter including a capacitor 1271 and a resistor 1272. The low-pass filter circuit 127 filters a signal to the gate electrode of the second transistor 121 in a high-frequency band.
Note that the frequency band passed by the low-pass filter circuit 127, that is, the cutoff frequency ωz of the low-pass filter circuit 127 can be adjusted by the capacitance C of the capacitor 1271 and the resistance value R of the resistor 1272 (ωz=1/RC). In addition,
The third circuit 13 includes a third transistor 131. The third transistor 131 is, for example, an n-channel transistor, and is connected between the output node 61 through which the output current Io flows and the reference potential node 31. The gate electrode of the third transistor 131 is connected to the gate electrode of the first transistor 111. The size parameter of the third transistor 131 is a+b. That is, the size parameter a+b of the third transistor 131 is equal to the sum of the size parameter a of the first transistor 111 and the size parameter b of the second transistor 121. The third transistor 131 is an example of a third transistor.
The first circuit 11 and the second circuit 12 constitute a current mirror circuit together with the third circuit 13. When the input current II flows to the input node 51, a current Ia+b in a ratio corresponding to the size parameter a+b of the third transistor 131 flows through the third circuit 13 as a mirror destination.
Next, the operation of the amplifier circuit D1 will be described with reference to
In the amplifier circuit D1, the gain (peak gain) in a case where the frequency of the input current II is higher than the cutoff frequency of the low-pass filter circuit 127 is larger than the gain (DC gain) in a case where the frequency of the input current II is lower than the cutoff frequency of the low-pass filter circuit 127.
More specifically, first, a case where the frequency ω of the input current II as an input signal has a relationship of ω≤ωz=1/RC (that is, a case where the frequency is equal to or lower than the cutoff frequency ωz of the low-pass filter circuit 127) is assumed. In such a case, the input signal passes through the low-pass filter circuit 127. Therefore, when the input current II is input to the input node 51, a current Ia in a ratio corresponding to the size parameter a of the first transistor 111 flows through the first circuit 11, and a current Ib in a ratio corresponding to the size parameter b of the second transistor 121 flows through the second circuit 12.
In the third transistor 131, the first transistor 111, and the second transistor 121, the voltages between the gates and the sources are equal. Therefore, the current is converted by the same overdrive voltage Vod based on a current mirror operation, and the drain current Ia+b flows through the third transistor 131 as a mirror current. Therefore, the DC gain in a case where the input signal has a low frequency is A1=Ia+b/(Ia+Ib)=(a+b)/(a+b)=1 as illustrated in
In addition, a case where the frequency ω of the input current II as the input signal has a relationship of ω>wz=1/RC (that is, a case where the frequency is higher than the cutoff frequency ωz of the low-pass filter circuit 127) is assumed. In such a case, when the input current II is input to the input node 51, the drain current Ia+b flows as a mirror current through the third transistor 131 based on the current mirror operation. At this time, the current Ia in the ratio corresponding to the size parameter a of the first transistor 111 flows through the first circuit 11. On the other hand, the gate electrode of the second transistor 121 is connected to the gate electrode of the first transistor 111 via the low-pass filter circuit 127. As a result, since the input signal to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127, the current Ib does not flow through the second transistor 121. Therefore, as illustrated in
In the amplifier circuit D1, the difference between the gain (peak gain) in a case where the frequency of the input current II is higher than the cutoff frequency of the low-pass filter circuit 127 and the gain (DC gain) in a case where the frequency of the input current II is lower than the cutoff frequency of the low-pass filter circuit 127 can be determined according to the size parameter b of the second transistor 121.
Furthermore, the boundary point ωz=1/RC between the DC gain A1 and the boost gain A2 can be set at a desired position by adjusting the resistance value R and the capacitance C of the low-pass filter circuit 127. In addition, a straight line B is a straight line indicating the frequency characteristics of the portion where the gain decreases, and A=gm/SCTOT. Here, gm is a transconductance, s is a variable of Laplace transform, and CTOT is a value of the total capacitance of the gate terminal.
As described above, the amplifier circuit D1 according to the present embodiment includes the first circuit 11, the second circuit 12, and the third circuit 13. The first circuit 11 includes the first transistor 111 connected between the input node 51 through which the input current flows and the reference potential node 31, and having the gate electrode connected to the input node 51. The second circuit 12 includes the low-pass filter circuit 127. The second circuit 12 includes the second transistor 121 connected in parallel to the first transistor 111 between the input node 51 and the reference potential node 31, and having the gate electrode connected to the gate electrode of the first transistor 111 via the low-pass filter circuit 127. The third circuit 13 includes the third transistor 131 connected between the output node 61 through which the output current flows and the reference potential node 31, and having the gate electrode connected to the first transistor 111.
When the frequency of the input current II as the input signal is a high frequency, the input signal to be input to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127. Therefore, in the high frequency band, the current Ib can be prevented from flowing through the second transistor 121, and the amplification factor can be increased from the DC gain to the peak gain.
In addition, the amplifier circuit D1 does not require an inductor element (coil). Therefore, as compared with a conventional amplifier circuit using an inductor element (coil), a circuit area can be reduced, and power consumption can be reduced.
The amplifier circuit D1 is based on a current mirror circuit manufactured by the same process. In general, input and output variation factors (for example, parameters such as the threshold value Vth and the gain coefficient β of a transistor) in an integrated circuit vary similarly within the same process. Therefore, even if variations occur, these variation factors cancel each other due to similar changes, and an amplifier circuit with a small gain error can be finally fabricated.
Furthermore, for example, in the case of a conventional source degeneration type equalizer that varies the DC gain and the boost gain using the resistance (resistance value RS), the capacitance (capacitance CS), the parasitic resistance (resistance value Rp) of the inductor, and the load resistance (resistance value RL), the DC gain Av can be expressed as Av=(RL+Rp)/(1/gm+RS) using the transconductances gm, RS, Rp, and RL. That is, since gm is nonlinear, the DC gain Av of the conventional source degeneration type equalizer does not become linear.
On the other hand, the amplification factor Ai of the amplifier circuit D1 based on the current mirror circuit can have linearity as follows.
That is, there is a relationship of Equation (1) between the current Iin of the input signal and the overdrive voltage Vod.
I
in=(2Iin/βin1/2=Vod (1)
Here, βin is a gain coefficient of the transistor of the mirror source. The gain coefficient β of the transistor is defined by the following Equation (2).
β=μCox{W(or nfin)/L}˜{W(or nfin)/L} (2)
Note that μ represents the carrier mobility, Cox represents the capacitance of the gate oxide film, W represents the gate width of the planar transistor, L represents the gate length, and nfin represents the number of fins of the FinFET.
That is, there is a relationship of Equation (3) between the current Iout of the output signal and the overdrive voltage Vod.
I
out=(βout/2)Vod2 (3)
Here, βout is a gain coefficient of the transistor of the mirror destination.
From Equation (3) and Equation (1), the following Equation (4) is established.
Therefore, the amplification factor Ai of the amplifier circuit D1 is expressed by the following Equation (5) and is linear.
A
i=βout/βin) (5)
The third circuit 13, the first circuit 11, the second circuit 12, and the constant current source 40 operate as a current mirror circuit. When the input current II flows to the input node 51, a current Ia+b+c in a ratio corresponding to the size parameter a+b+c of the third transistor 131 flows through the third circuit 13 as a mirror destination.
First, a case where the frequency ω of the input current II as an input signal has a relationship of ω≤ωz=1/RC (that is, a case where the frequency is equal to or lower than the cutoff frequency ωz of the low-pass filter circuit 127) is assumed. In such a case, since the input signal passes through the low-pass filter circuit 127, when the input current II is input to the input node 51, a current Ia in a ratio corresponding to the size parameter a flows through the first transistor 111, and a current Ib in a ratio corresponding to the size parameter b flows through the second transistor 121. Based on the current mirror operation, a drain current Ia+b+c flows through the third transistor 131 as a current mirror destination. Therefore, the DC gain in a case where the input signal has a frequency ω≤ωz=1/RC is A4=Ia+b+c/(Ia+Ib)=(a+b+c)/(a+b) as illustrated in
In addition, a case where the frequency ω of the input current II as the input signal has a relationship of w>wz=1/RC (that is, a case where the frequency is higher than the cutoff frequency ωz of the low-pass filter circuit 127) is assumed. In such a case, when the input current II is input to the input node 51, the drain current Ia+b+c flows through the third transistor 131 as the mirror destination based on the current mirror operation. At this time, the current Ia in the ratio corresponding to the size parameter a of the first transistor 111 flows through the first circuit 11. On the other hand, since the input signal to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127, the current Ib does not flow through the second transistor 121. Therefore, as illustrated in
That is, the amplifier circuit D2 according to the second embodiment can amplify not only the boost gain but also the DC gain. In addition, the boost gain and the DC gain can be variably amplified by adjusting the current Ic output from the constant current source 40. In addition, the boost gain can be further amplified as compared with the amplifier circuit D1 according to the first embodiment.
The amplifier circuit D3 includes a first circuit 11, a second circuit 12, a third circuit 13, a fourth circuit 14, a fifth circuit 15, a sixth circuit 16, a seventh circuit 17, an eighth circuit 18, an input node 51, a reference potential node 31, and an output node 61.
The first circuit 11 and the second circuit 12 are as described in the first embodiment. A size parameter of a third transistor 131 included in the third circuit 13 is equal to the sum of the size parameter a of the first transistor 111, the size parameter b of the second transistor 121, and a size parameter c of a seventh transistor 171 included in the seventh circuit 17. That is, the size parameter of the third transistor 131 is a+b+c.
The fourth circuit 14 includes a fourth transistor 141. The fourth transistor 141 is, for example, an n-channel transistor, and is connected between an input node 32 through which the input current IIN flows and the reference potential node 31. The gate electrode of the fourth transistor 141 is connected to the input node 32. The drain electrode and source electrode of the fourth transistor 141 are connected to the input node 32 and the reference potential node 31, respectively. The size parameter of the fourth transistor 141 is a.
The fifth circuit 15 includes a fifth transistor 151 and a low-pass filter circuit 157. The fifth transistor 151 is, for example, an n-channel transistor, and is connected in parallel to the fourth transistor 141 between the input node 32 through which the input current IIN flows and the reference potential node 31. The gate electrode of the fifth transistor 151 is connected to the fourth transistor 141 via the low-pass filter circuit 157. The drain electrode and source electrode of the fifth transistor 151 are connected to the input node 32 and the reference potential node 31, respectively. The size parameter of the fifth transistor 151 is b.
The low-pass filter circuit 157 includes a capacitor 1571 and a resistor 1572. The function of the low-pass filter circuit 157 is similar to that of the low-pass filter circuit 127.
The sixth circuit 16 includes a sixth transistor 161. The sixth transistor 161 is, for example, an n-channel transistor, and is connected between an output node 63 through which an output current ION flows and the reference potential node 31. The gate electrode of the sixth transistor 161 is connected to the gate electrode of the fourth transistor 141. The drain electrode and source electrode of the sixth transistor 161 are connected to the output node 63 and the reference potential node 31, respectively. A size parameter of the sixth transistor 161 is equal to the sum of the size parameter a of the fourth transistor 141, the size parameter b of the fifth transistor 151, and a size parameter c of an eighth transistor 181 included in the eighth circuit 18. That is, the size parameter of the sixth transistor 161 is a+b+c.
The seventh circuit 17 includes the seventh transistor 171. The seventh transistor 171 is, for example, an n-channel transistor, and is connected between an input node 53 through which the input current IIN flows and the reference potential node 31. In addition, the gate electrode of the seventh transistor 171 is connected to the gate electrode of the first transistor 111. The size parameter of the seventh transistor 171 is c.
The eighth circuit 18 includes the eighth transistor 181. The eighth transistor 181 is, for example, an n-channel transistor, and is connected between the input node 51 through which the input current lip flows and the reference potential node 31. In addition, the gate electrode of the eighth transistor 181 is connected to the gate electrode of the fourth transistor 141. The size parameter of the eighth transistor 181 is c.
The first circuit 11, the second circuit 12, the third circuit 13, and the seventh circuit 17 operate as a first current mirror circuit CM1 that receives the input currents IIP and IIN from the input terminals 50 and 52 and outputs the output current IOP from the output terminal 60. The fourth circuit 14, the fifth circuit 15, the sixth circuit 16, and the eighth circuit 18 operate as a second current mirror circuit CM2 that receives the input currents IIP and IIN from the input terminals 50 and 52 and outputs the output current ION from the output terminal 62.
The first current mirror circuit CM1 and the second current mirror circuit CM2 are cross-coupled by the seventh transistor 171 of the seventh circuit 17 to which the input current IIN is input and the eighth transistor 181 of the eighth circuit 18 to which the input current IIP is input.
First, a case where the frequency ω of the input currents IIP and IIN as an input signal satisfies w ωz=1/RC in the first current mirror circuit CM1 (that is, the frequency is equal to or lower than the cutoff frequency ωz of the low-pass filter circuit 127) is assumed. In such a case, the input signal passes through the low-pass filter circuit 127. Therefore, when the input current IIP is input to the input node 51, a current Ia in a ratio corresponding to the size parameter a of the first transistor 111 flows through the first circuit 11, and a current Ib in a ratio corresponding to the size parameter b of the second transistor 121 flows through the second circuit 12.
In addition, when the input current IIN is input to the input node 53, the polarity of the input current IIN is inverted from the polarity of the input current IIP, and thus, a current −Ic in a ratio corresponding to the size parameter c of the seventh transistor 171 flows through the seventh circuit 17.
In the third transistor 131, the first transistor 111, the second transistor 121, and the seventh transistor 171, the voltages between the gates and the sources are equal. Therefore, a drain current Ia+b+c flows through the third transistor 131.
The operation of the second current mirror circuit CM2 is also substantially the same except that the input currents IIP and IIN whose polarities are inverted are input.
Therefore, the DC gain in a case where the input signal has a low frequency is A10=Ia+b+c/(Ia+Ib−Ic)=(a+b+c)/(a+b−c) as illustrated in
In addition, a case where the frequency ω of the input currents IIP and IIN as the input signal has a relationship of w>ωz=1/RC (that is, a case where the frequency is higher than the cutoff frequency ωz of the low-pass filter circuit 127) is assumed. In such a case, when the input current IIP is input to the input node 51, the drain current Ia+b+c flows through the third transistor 131 as a mirror destination based on a current mirror operation. At this time, the current Ia in the ratio corresponding to the size parameter a of the first transistor 111 flows through the first circuit 11. The current −Ic in the ratio corresponding to the size parameter c of the seventh transistor 171 flows through the seventh circuit 17.
On the other hand, the gate electrode of the second transistor 121 is connected to the gate electrode of the first transistor 111 via the low-pass filter circuit 127. As a result, since the input signal to the gate electrode of the second transistor 121 is filtered by the low-pass filter circuit 127, the current Ib does not flow through the second transistor 121.
The operation of the second current mirror circuit CM2 is also substantially the same except that the input currents IIP and IIN whose polarities are inverted are input.
Therefore, as illustrated in
As described above, the amplifier circuit D3 according to the present embodiment includes the first circuit 11, the second circuit 12, the third circuit 13, the fourth circuit 14, the fifth circuit 15, the sixth circuit 16, the seventh circuit 17, and the eighth circuit 18. The first circuit 11 includes the first transistor 111 connected between the input node 51 through which the input current IIP flows and the reference potential node 31, and having the gate electrode connected to the input node 51. The second circuit 12 includes the low-pass filter circuit 127. The second circuit 12 includes the second transistor 121 connected in parallel to the first transistor 111 between the input node 51 and the reference potential node 31, and having the gate electrode connected to the gate electrode of the first transistor 111 via the low-pass filter circuit 127. The third circuit 13 includes the third transistor 131 connected between the output node 61 through which the output current flows and the reference potential node 31, and having the gate electrode connected to the first transistor 111.
The fourth circuit 14 includes the fourth transistor 141 connected between the input node 53 through which the input current IIN flows and the reference potential node 31, and having the gate electrode connected to the input node 53. The fifth circuit 15 includes the low-pass filter circuit 157. The fifth circuit 15 includes the fifth transistor 151 connected in parallel to the fourth transistor 141 between the input node 53 and the reference potential node 31, and having the gate electrode connected to the gate electrode of the fourth transistor 141 via the low-pass filter circuit 157. The sixth circuit 16 includes the sixth transistor 161 connected between the output node 63 through which the output current flows and the reference potential node 31, and having the gate electrode connected to the fourth transistor 141.
The seventh circuit 17 includes the seventh transistor 171 connected between the input node 53 through which the input current IIN flows and the reference potential node 31, and having the gate electrode connected to the gate electrode of the first transistor 111. The eighth circuit 18 includes the eighth transistor 181 connected between the input node 51 through which the input current IIP flows and the reference potential node 31, and having the gate electrode connected to the gate electrode of the fourth transistor 141.
The first circuit 11, the second circuit 12, the third circuit 13, and the seventh circuit 17 operate as the first current mirror circuit CM1, and the fourth circuit 14, the fifth circuit 15, the sixth circuit 16, and the eighth circuit 18 operate as the second current mirror circuit CM2. The first current mirror circuit CM1 and the second current mirror circuit CM2 are cross-coupled by the seventh transistor 171 of the seventh circuit 17 and the eighth transistor 181 of the eighth circuit 18.
The input current IIN is cross-coupled with the input current IIP in the first current mirror circuit CM1 and the second current mirror circuit 17 and the eight transistor 181 of the eight circuit 18. As a result, the amplifier circuit D3 can have a function of amplifying the DC gain in addition to the boost gain amplification function described in the first embodiment.
As a result, the amplifier circuit D4 according to the fourth embodiment can further amplify the DC gain as compared with the amplifier circuit D3, similarly to the case of the amplifier circuit D2 according to the second embodiment. In addition, the boost gain and the DC gain can be variably amplified by adjusting currents Id output from the constant current sources 40 and 41.
As illustrated in
The amplifier circuit D5 includes A first circuits 11 connected in parallel (hereinafter, referred to as a “first circuit group”).
The amplifier circuit D5 includes B second circuits 12 connected in parallel to each other (hereinafter, referred to as a “second circuit group”).
The amplifier circuit D5 includes C seventh circuits 17 connected in parallel to each other (hereinafter, referred to as a “seventh circuit group”).
The amplifier circuit D5 includes A+B+C third circuits 13 connected in parallel to each other (hereinafter, referred to as a “third circuit group”). The number of third circuits 13 included in the third circuit group is equal to the sum of the number of first circuits 11 included in the first circuit group, the number of second circuits 12 included in the second circuit group, and the number of seventh circuits 17 included in the seventh circuit group. Here, A, B and C are integers indicating the number of pieces with regard to corresponding circuits, respectively.
The amplifier circuit D5 includes A fourth circuits 14 connected in parallel to each other (hereinafter, referred to as a “fourth circuit group”).
The amplifier circuit D5 includes B fifth circuits 15 connected in parallel to each other (hereinafter, referred to as a “fifth circuit group”).
The amplifier circuit D5 includes C eighth circuits 18 connected in parallel to each other (hereinafter, referred to as an “eighth circuit group”).
The amplifier circuit D5 includes A+B+C sixth circuits 16 connected in parallel to each other (hereinafter, referred to as a “sixth circuit group”). The number of sixth circuits included in the sixth circuit group is equal to the sum of the number of fourth circuits 14 included in the fourth circuit group, the number of fifth circuits 15 included in the fifth circuit group, and the number of eighth circuits 18 included in the eighth circuit group.
The first circuit group, the second circuit group, and the seventh circuit group constitute a first current mirror circuit CM1 with the third circuit group. The fourth circuit group, the fifth circuit group, and the sixth circuit group constitute a second current mirror circuit CM2 with the eighth circuit group. The amplifier circuit D5 includes a controller 25.
Each of the first circuits 11 includes a ninth transistor 112 connected in series to the first transistor 111. The ninth transistor 112 is, for example, an n-channel transistor, and the drain electrode of the ninth transistor 112 is connected to the source electrode of the first transistor 111. The source electrode of the ninth transistor 112 is connected to the reference potential node 31. The gate electrode of the ninth transistor 112 is connected to a predetermined fixed potential node, for example, a power supply potential node. The size parameter of the first transistor 111 is “1”. The A first transistors 111 connected in parallel in the first circuit group constitute a part of a group of transistors that cause a current Ia in a ratio corresponding to the size parameter a to flow.
Each of the second circuits 12 includes, in addition to the second transistor 121 and the low-pass filter circuit 127, a tenth transistor 122 for on/off control, an eleventh transistor 123, a twelfth transistor 124 for on/off control, and a first inverter 128.
The tenth transistor 122 is, for example, an n-channel transistor, and is connected between the second transistor 121 and the reference potential node 31. The drain electrode of the tenth transistor 122 is connected to the source electrode of the second transistor 121. The source electrode of the tenth transistor 122 is connected to the reference potential node 31. The gate electrode of the tenth transistor 122 is connected to a first control node 33. The size parameter of the second transistor 121 is “1”. The B second transistors 121 connected in parallel in the second circuit group constitute a part of a group of transistors that cause a current Ib in a ratio corresponding to the size parameter b to flow when turned on.
The eleventh transistor 123 is, for example, an n-channel transistor, and is connected in parallel to the first transistor 111 and the second transistor 121 between the input node 51 and the reference potential node 31. The drain electrode of the eleventh transistor 123 is connected to the input node 51. The source electrode of the eleventh transistor 123 is connected to the drain electrode of the twelfth transistor 124. The gate electrode of the eleventh transistor 123 is connected to the gate electrode of the first transistor 111 without via the low-pass filter circuit 127. The size parameter of the eleventh transistor 123 is “1”. The B eleventh transistors 123 connected in parallel in the second circuit group constitute a part of the group of the transistors that cause the current Ia in the ratio corresponding to the size parameter a to flow when turned on.
The twelfth transistor 124 is, for example, an n-channel transistor, and is connected between the eleventh transistor 123 and the reference potential node 31. The source electrode of the twelfth transistor 124 is connected to the reference potential node 31.
The input side of the first inverter 128 is connected to the gate electrode of the tenth transistor 122, that is, the first control node 33. The output side of the first inverter 128 is connected to the gate electrode of the twelfth transistor 124. The first inverter 128 selectively turns on any one of the tenth transistor 122 and the twelfth transistor 124 in accordance with a control signal to be input to the first inverter 128.
It is assumed that, in the second circuit 12, a control signal (for example, a high-level signal) for turning on the tenth transistor 122 to cause a current to flow to the second transistor 121 is supplied from the controller 25 to the first control node 33. In such a case, the tenth transistor 122 is turned on by the high-level signal, and a current I1 in a ratio corresponding to the size parameter “1” flows through the second transistor 121.
On the other hand, the high-level signal is also supplied to the first inverter 128. The first inverter 128 supplies a low-level signal obtained by inverting the supplied high-level signal to the gate electrode of the twelfth transistor 124. The twelfth transistor 124 is not turned on because the control signal supplied to the gate electrode is a low-level signal.
In addition, it is assumed that a control signal (for example, a low-level signal) for turning off the tenth transistor 122 is supplied from the controller 25 to the first control node 33. In such a case, the tenth transistor 122 is turned off by the low-level signal, and the current I1 does not flow through the second transistor 121.
On the other hand, the low-level signal is also supplied to the first inverter 128. The first inverter 128 supplies a high-level signal obtained by inverting the supplied low-level signal to the gate electrode of the twelfth transistor 124. The twelfth transistor 124 is turned on because the control signal supplied to the gate electrode is a high-level signal, and the current I1 in the ratio corresponding to the size parameter “1” flows through the eleventh transistor 123.
Each of the seventh circuits 17 includes a seventh transistor 171, a thirteenth transistor 172, a fourteenth transistor 173, a fifteenth transistor 174, and a second inverter 175.
The seventh transistor 171 is, for example, an n-channel transistor, and is connected in parallel to the fourth transistor 141 and the fifth transistor 151 between the input node 53 and the reference potential node 31. The drain electrode of the seventh transistor 171 is connected to the input node 53. The source electrode of the seventh transistor 171 is connected to the drain electrode of the thirteenth transistor 172. The gate electrode of the seventh transistor 171 is connected to the gate electrode of the first transistor 111. The size parameter of the seventh transistor 171 is “1”. The C seventh transistors 171 connected in parallel in the seventh circuit group constitute a part of a group of transistors that cause a current −Ic in a ratio corresponding to the size parameter c to flow when turned on.
The thirteenth transistor 172 is, for example, an n-channel transistor, and is connected between the seventh transistor 171 and the reference potential node 31. The source electrode of the thirteenth transistor 172 is connected to the reference potential node 31.
The fourteenth transistor 173 is, for example, an n-channel transistor, and is connected in parallel to the first transistor 111 and the second transistor 121 between the input node 51 and the reference potential node 31. The drain electrode of the fourteenth transistor 173 is connected to the input node 51. The source electrode of the fourteenth transistor 173 is connected to the drain electrode of the fifteenth transistor 174. The gate electrode of the fourteenth transistor 173 is connected to the gate electrode of the first transistor 111. The size parameter of the fourteenth transistor 173 is “1”. The C fourteenth transistors 173 connected in parallel in the seventh circuit group constitute a part of the group of the transistors that cause the current Ia in the ratio corresponding to the size parameter a to flow when turned on.
The fifteenth transistor 174 is, for example, an n-channel transistor, and is connected between the fourteenth transistor 173 and the reference potential node 31. The source electrode of the fifteenth transistor 174 is connected to the reference potential node 31. The gate electrode of the fifteenth transistor 174 is connected to a second control node 34.
The input side of the second inverter 175 is connected to the gate electrode of the fifteenth transistor 174, that is, the second control node 34. The output side of the second inverter 175 is connected to the gate electrode of the thirteenth transistor 172. The second inverter 175 selectively turns on any one of the thirteenth transistor 172 and the fifteenth transistor 174 in accordance with a control signal to be input to the second inverter 175.
It is assumed that, in the seventh circuit 17, a high-level signal for turning on the fifteenth transistor 174 to cause a current to flow to the fourteenth transistor 173 is supplied from the controller 25 to the second control node 34. In such a case, the fifteenth transistor 174 is turned on by the high-level signal, and a current I1 in the ratio corresponding to the size parameter “1” flows through the fourteenth transistor 173.
On the other hand, the high-level signal is also supplied to the second inverter 175. The second inverter 175 supplies a low-level signal obtained by inverting the supplied high-level signal to the gate electrode of the thirteenth transistor 172. The thirteenth transistor 172 is not turned on because the control signal supplied to the gate electrode is a low-level signal.
In addition, it is assumed that a low-level signal for turning off the fourteenth transistor 173 is supplied from the controller 25 to the second control node 34. In such a case, the fifteenth transistor 174 is turned off by the low-level signal, and the current I1 does not flow through the fourteenth transistor 173.
On the other hand, the low-level signal is also supplied to the second inverter 175. The second inverter 175 supplies a high-level signal obtained by inverting the supplied low-level signal to the gate electrode of the thirteenth transistor 172. The thirteenth transistor 172 is turned on because the control signal supplied to the gate electrode is a high-level signal, and the current I1 in the ratio corresponding to the size parameter “1” flows through the seventh transistor 171.
Each of the third circuits 13 includes a sixteenth transistor 132 connected between the third transistor 131 and the reference potential node 31. The sixteenth transistor 132 is, for example, an n-channel transistor, and the drain electrode of the sixteenth transistor 132 is connected to the source electrode of the third transistor 131. The source electrode of the sixteenth transistor 132 is connected to the reference potential node 31. The gate electrode of the sixteenth transistor 132 is connected to a predetermined fixed potential node, for example, the power supply potential node. The size parameter of the third transistor 131 is “1”. The A+B+C third transistors 131 connected in parallel in the third circuit group constitute a part of a group of transistors that cause a current Ia+b+c in a ratio corresponding to the size parameter a+b+c to flow when turned on.
As described above, in the amplifier circuit D5 illustrated in
Each of the fourth circuits 14 includes a seventeenth transistor 142 connected between the fourth transistor 141 and the reference potential node 31. The seventeenth transistor 142 is, for example, an n-channel transistor, and the drain electrode of the seventeenth transistor 142 is connected to the source electrode of the fourth transistor 141. The source electrode of the seventeenth transistor 142 is connected to the reference potential node 31. The gate electrode of the seventeenth transistor 142 is connected to a predetermined fixed potential node, for example, the power supply potential node. The size parameter of the fourth transistor 141 is “1”. The A fourth transistors 141 connected in parallel in the fourth circuit group constitute a part of a group of transistors that cause a current −Ia in the ratio corresponding to the size parameter a to flow.
Each of the fifth circuits 15 includes, in addition to the fifth transistor 151 and the low-pass filter circuit 157, an eighteenth transistor 152, a nineteenth transistor 153, a twentieth transistor 154, and a third inverter 158.
The eighteenth transistor 152 is, for example, an n-channel transistor, and is connected between the fifth transistor 151 and the reference potential node 31. The drain electrode of the eighteenth transistor 152 is connected to the source electrode of the fifth transistor 151. The source electrode of the eighteenth transistor 152 is connected to the reference potential node 31. The gate electrode of the eighteenth transistor 152 is connected to a third control node 35. The size parameter of the fifth transistor 151 is “1”. The B fifth transistors 151 connected in parallel in the fifth circuit group constitute a part of a group of transistors that cause a current −Ib in the ratio corresponding to the size parameter b to flow when turned on.
The nineteenth transistor 153 is, for example, an n-channel transistor, and is connected in parallel to the fourth transistor 141 and the fifth transistor 151 between the input node 53 and the reference potential node 31. The drain electrode of the nineteenth transistor 153 is connected to the input node 53. The source electrode of the nineteenth transistor 153 is connected to the drain electrode of the twentieth transistor 154. The gate electrode of the nineteenth transistor 153 is connected to the gate electrode of the fourth transistor 141 without via the low-pass filter circuit 157. The size parameter of the nineteenth transistor 153 is “1”. The B nineteenth transistors 153 connected in parallel in the fifth circuit group constitute a part of the group of the transistors that cause the current −Ia in the ratio corresponding to the size parameter a to flow when turned on.
The twentieth transistor 154 is, for example, an n-channel transistor, and is connected between the nineteenth transistor 153 and the reference potential node 31. The source electrode of the twentieth transistor 154 is connected to the reference potential node 31.
The input side of the third inverter 158 is connected to the gate electrode of the eighteenth transistor 152, that is, the third control node 35. The output side of the third inverter 158 is connected to the gate electrode of the twentieth transistor 154. The third inverter 158 selectively turns on any one of the eighteenth transistor 152 and the twentieth transistor 154 in accordance with a control signal to be input to the third inverter 158.
Since the switching control in the fifth circuits 15 is similar to that in the second circuits 12, the description thereof will be omitted.
Each of the eighth circuits 18 includes an eighth transistor 181, a twenty-first transistor 182, a twenty-second transistor 183, a twenty-third transistor 184, and a fourth inverter 185.
The eighth transistor 181 is, for example, an n-channel transistor, and is connected in parallel to the first transistor 111 and the second transistor 121 between the input node 51 and the reference potential node 31. The drain electrode of the eighth transistor 181 is connected to the input node 51. The source electrode of the eighth transistor 181 is connected to the drain electrode of the twenty-first transistor 182. The gate electrode of the eighth transistor 181 is connected to the gate electrode of the fourth transistor 141. The size parameter of the eighth transistor 181 is “1”. The C eighth transistors 181 connected in parallel in the eighth circuit group constitute a part of a group of transistors that cause a current Ic in the ratio corresponding to the size parameter c to flow when turned on.
The twenty-first transistor 182 is, for example, an n-channel transistor, and is connected between the eighth transistor 181 and the reference potential node 31. The source electrode of the twenty-first transistor 182 is connected to the reference potential node 31.
The twenty-second transistor 183 is, for example, an n-channel transistor, and is connected in parallel to the fourth transistor 141 and the fifth transistor 151 between the input node 53 and the reference potential node 31. The drain electrode of the twenty-second transistor 183 is connected to the input node 53. The source electrode of the twenty-second transistor 183 is connected to the drain electrode of the twenty-third transistor 184. The gate electrode of the twenty-second transistor 183 is connected to the gate electrode of the fourth transistor 141. The size parameter of the twenty-second transistor 183 is “1”. The C twenty-second transistors 183 connected in parallel in the eighth circuit group constitute a part of the group of the transistors that cause the current −Ia in the ratio corresponding to the size parameter a to flow when turned on.
The twenty-third transistor 184 is, for example, an n-channel transistor, and is connected between the twenty-second transistor 183 and the reference potential node 31. The source electrode of the twenty-third transistor 184 is connected to the reference potential node 31. The gate electrode of the twenty-third transistor 184 is connected to a fourth control node 36.
The input side of the fourth inverter 185 is connected to the gate electrode of the twenty-third transistor 184, that is, the fourth control node 36. The output side of the fourth inverter 185 is connected to the gate electrode of the twenty-first transistor 182. The fourth inverter 185 selectively turns on any one of the twenty-first transistor 182 and the twenty-third transistor 184 in accordance with a control signal to be input to the fourth inverter 185.
Since the switching control in the eighth circuits 18 is similar to that in the seventh circuits 17, the description thereof will be omitted.
Each of the sixth circuits 16 includes a twenty-fourth transistor 162 connected between the sixth transistor 161 and the reference potential node 31. The twenty-fourth transistor 162 is, for example, an n-channel transistor, and the drain electrode of the twenty-fourth transistor 162 is connected to the source electrode of the sixth transistor 161. The source electrode of the twenty-fourth transistor 162 is connected to the reference potential node 31. The gate electrode of the twenty-fourth transistor 162 is connected to a predetermined fixed potential node, for example, the power supply potential node. The size parameter of the sixth transistor 161 is “1”. The A+B+C sixth transistors 161 connected in parallel in the sixth circuit group constitute a part of the group of the transistors that cause the current Ia+b+c in the ratio corresponding to the size parameter a+b+c to flow when turned on.
As described above, in the amplifier circuit D5 illustrated in
The controller 25 is a control circuit that performs selective input of a plurality of first control signals to the second circuit group, selective input of a plurality of second control signals to the seventh circuit group, selective input of a plurality of third control signals to the fifth circuit group, and selective input of a plurality of fourth control signals to the eighth circuit group, in variable manners according to the DC gain to be set and the boost gain to be set.
In the amplifier circuit D5, the difference between the gain in a case where the frequency ω of the input currents IIP and IIN is higher than the cutoff frequency ωz of the low-pass filter circuit 127 and the low-pass filter circuit 157 and the gain in a case where the frequency ω of the input currents IIP and IIN is lower than the cutoff frequency ωz of the low-pass filter circuit 127 and the low-pass filter circuit 157 is determined according to the number of second transistors 121 to be turned on by the first control signals and the number of fifth transistors 151 to be turned on by the third control signals.
Furthermore, in the amplifier circuit D5, the gain in a case where the frequency ω of the input currents IIP and IIN is lower than the cutoff frequency ωz of the low-pass filter circuit 127 and the low-pass filter circuit 157 is determined according to the number of seventh transistors 171 to be turned on by the second control signals and the number of eighth transistors 181 to be turned on by the fourth control signals.
Furthermore, in the amplifier circuit D5, the gain in a case where the frequency ω of the input currents IIP and IIN is higher than the cutoff frequency ωz of the low-pass filter circuit 127 and the low-pass filter circuit 157 is larger than the gain in a case where the frequency ω of the input currents IIP and IIN is lower than the cutoff frequency ωz of the low-pass filter circuit 127 and the low-pass filter circuit 157.
More specifically, the controller 25 supplies corresponding control signals to a plurality of first control nodes 33, a plurality of second control nodes 34, a plurality of third control nodes 35, and a plurality of fourth control nodes 36 according to the DC gain to be set and the boost gain to be set. The controller 25 stores a lookup table for determining the size parameters a, b, and c based on the DC gain to be set and the boost gain to be set. The controller 25 determines the values of the size parameters a, b, and c based on the DC gain to be set, the boost gain to be set, and the lookup table. The controller 25 supplies corresponding control signals for setting the determined values of the size parameters a, b, and c to the plurality of first control nodes 33, the plurality of second control nodes 34, the plurality of third control nodes 35, and the fourth control nodes 36.
Next, switching control of the first circuit 11 and the second circuit 12 in the first current mirror circuit CM1 will be described. This switching control is executed using the size parameters a, b, and c determined based on the level of the DC gain and the level of the boost gain.
First, the determination of the size parameters a, b, and c will be described. The size parameters a, b, and c are determined using the lookup table with the DC gain and the boost gain as input information and the values (that is, in the first current mirror circuit CM1, the number of transistors to be driven in order to cause a current in a ratio corresponding to each size parameter to flow) of the size parameters a, b, and c as output information.
For example, it is assumed that the level (EQ) of the boost gain is set to 3 and the level (VGA) of the DC gain is set to 8. In such a case, (a, b, c)=(19, 3, 10) is obtained according to the lookup tables of
At this time, since b=3, the controller 25 supplies a control signal (for example, a high-level signal) for turning on the tenth transistor 122 to cause a current to flow to the second transistor 121 to the first control nodes 33 in the 3 second circuits 12 among the B second circuits 12 connected in parallel and constituting the second circuit group. At this time, since b=3, the controller 25 supplies a control signal (for example, a high-level signal) for turning on the twelfth transistor 124 to cause a current to flow to the eleventh transistor 123 to the first control nodes 33 in the remaining 11 (B−b=11) second circuits 12 among the B second circuits 12 connected in parallel and constituting the second circuit group.
In addition, since c=10, the controller 25 supplies a control signal (for example, a low-level signal) for turning on the thirteenth transistor 172 to cause a current to flow to the seventh transistor 171 to the second control nodes 34 in all the 10 seventh circuits 17 among the C seventh circuits 17 connected in parallel and constituting the seventh circuit group. On the other hand, a control signal (for example, a high-level signal) for turning on the fifteenth transistor 174 to cause a current to flow to the fourteenth transistor 173 is not supplied to any of the seventh circuits 17.
That is, in a case where the level (EQ) of the boost gain is set to 3 and the level (VGA) of the DC gain is set to 8, it is necessary to set (a, b, c)=(19, 3, 10) from the lookup tables. This corresponds to, for example, the need for the following three types of control. First, in the mirror source of the first current mirror circuit CM1, it is necessary to generate the current Ia corresponding to the size parameter a (=19) by turning on, in parallel, 19 transistors whose size parameters are “1” and whose gate electrodes are connected to the gate electrodes of the mirror destination transistors without via the low-pass filter circuit. In addition, it is necessary to generate the current Ib in a ratio corresponding to the size parameter b (=3) by turning on, in parallel, 3 transistors whose size parameters are “1” and whose gate electrodes are connected to the gate electrodes of the mirror destination transistors via the low-pass filter circuit. Further, it is necessary to generate the current −Ic in a ratio corresponding to the size parameter c (=10) by turning on, in parallel, 10 transistors whose size parameters are “1” and whose drain electrodes are connected to the input node different from the drain electrodes of the mirror destination transistors.
Therefore, the control of the controller 25 is to turn on the second transistors 121 whose size parameters are “1” in the 3 second circuits 12 among the 14 second circuits 12, and turn on the eleventh transistors 123 whose size parameters are “1” in the remaining 11 second circuits 12.
In the control of controller 25, the seventh transistor 171 having the size parameter “1” is turned on in each of the 10 seventh circuits 17 out of the 10 seventh circuits 17, and none of the fourteenth transistors 173 having the size parameter “1” is turned on in each of the 10 seventh circuits 17.
The 8 first circuits 11 are present, and the first transistors 111 whose size parameters are “1” are always in an on state. In addition, in the 11 second circuits 12, since the eleventh transistors 123 whose size parameters are “1” are turned on, a total of 19 (=8+11) transistors corresponding to the size parameter a=19 can be turned on.
As a result, in the mirror source of the first current mirror circuit CM1, the current Ia in the ratio corresponding to the size parameter a=19, the current Ib corresponding to the size parameter b=3, and the current −Ic for the size parameter c=10 can be caused to flow.
The size parameters a, b, and c may be determined at any timing. For example, it can be performed at the time of activation of a device on which the amplifier circuit D5 is mounted, or the like.
The same applies to the determination of the size parameters a, b, and c in the second current mirror circuit CM2 and the switching control based on the determined size parameters a, b, and c, and thus the description thereof will be omitted.
As described above, according to the amplifier circuit D5 according to the present embodiment, by setting a desired DC gain and a desired boost gain (peak gain), the size parameters a, b, and c for enabling the setting can be automatically determined based on the lookup table. The amplifier circuit D5 can perform the switching control according to the determined size parameters a, b, and c to amplify the DC gain and the boost gain.
That is, the user can individually and variably set the DC gain and the boost gain. As a result, it is possible to further cope with multi-leveling of the signal amplitude level.
An amplifier circuit D6 according to a sixth embodiment can have a larger DC gain and a larger boost gain by connecting any of the amplifier circuits D1 to D5 in each of multiple stages.
As illustrated in
The CTLE 81 is an input amplifier circuit that includes the respective amplifier circuits according to the first to sixth embodiments therein and continuously performs amplification processing and equalization processing on the time axis on differential input signals (serial input signals) received by differential input terminals 84 and 85. The DFE 82 is an equalization circuit that receives the output signal of the CTLE 81 and performs equalization processing by a feedback loop and determination of a signal level on the output signal of the CTLE 81. Note that the CTLE 81 and the DFE 82 are examples of input circuits. The DEMUX 83 is a conversion circuit that receives the output signal of the DFE 82 and performs conversion processing of converting the output signal of the DFE 82 from serial to parallel.
According to such a reception circuit D7, it is possible to implement a reception circuit having the effects of the amplifier circuits according to the first to sixth embodiments.
The reception circuit 80 is, for example, the reception circuit D7 illustrated in
According to such a reception circuit, it is possible to implement a reception circuit having the effects of the amplifier circuits according to the first to sixth embodiments.
First Modification
In the first and second embodiments, the single-ended amplifier circuits D1 and D2 have been described. On the other hand, a differential amplifier circuit can be configured using the two amplifier circuits D1 and D2.
Second Modification
In each of the above-described embodiments, the amplifier circuits using the n-channel transistors, and the like have been exemplified. As a matter of course, the amplifier circuits and the like according to each embodiment can be implemented using p-channel transistors.
In addition to the above embodiments, the following notes are disclosed.
According to an embodiment disclosed in the present specification, it is possible to implement an amplifier circuit, a differential amplifier circuit, a reception circuit, and a semiconductor integrated circuit that enable a boost gain amplification function and have a small area while maintaining linearity of a gain.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is a continuation of International Application No. PCT/JP2020/023110, filed on Jun. 11, 2020, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2020/023110 | Jun 2020 | US |
| Child | 18061757 | US |
