Patent Application
20250062723
This application claims priority under 35 U.S.C. § 119 to European patent application no. 23306374.2, filed Aug. 14, 2023, the contents of which are incorporated by reference herein.
Embodiments of the subject matter described herein relate generally to RF amplifiers.
High-efficiency radio-frequency (RF) amplifiers are increasingly finding use in communications applications. These high-efficiency RF amplifiers are desired because of the lower system size and cost achieved by the need for less cooling capability and because of the reduced energy needed to power these communications applications. Conventional high efficiency amplifiers (e.g., tuned class-AB) are operated at constant power supply voltages. Moreover, conventional high efficiency RF amplifiers are operated in a backed-off power condition. This backed-off power condition lowers amplifier efficiency.
Conventional high efficiency RF amplifiers may experience periods of low traffic conditions. This often means that the amplifiers have reduced efficiency because the amount of amplifier back off increases. This reduced efficiency results in excess energy usage. Thus, amplifier devices with improved efficiency are desired.
A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
In one aspect, an amplifier device may include a first amplifier electrically coupled to a first input terminal and to a first output terminal, wherein the first amplifier may include a first transistor that includes a first control electrode, a first current-carrying electrode and a second current carrying electrode, configured to support a current flow between the first-current-carrying electrode and the second current-carrying electrode, wherein the first control electrode is configured to control the current flow between first current-carrying electrode and the second current-carrying electrode, wherein the first control electrode may be radio frequency (RF) coupled to the first input terminal, and wherein the first current-carrying electrode may be electrically coupled to the first output terminal, according to an embodiment. In an embodiment, a first bias network may be electrically coupled to the first control electrode, wherein the first bias network may be configured to apply a first direct current (DC) bias to the first control electrode and may be RF-isolated from the first control electrode. In an embodiment, the amplifier device may include a second transistor that includes a second control electrode, a third current-carrying electrode and a fourth current carrying electrode, configured to support a current flow between the third-current-carrying electrode and the fourth current-carrying electrode, wherein the second control electrode is configured to control the current flow between third current-carrying electrode and the fourth current-carrying electrode, wherein the second control electrode may be RF coupled to the first input terminal, wherein the third current-carrying electrode may be electrically coupled to the first output terminal. A second bias network may be electrically coupled to the second control electrode, wherein the second bias network may be configured to apply a second DC bias to the second control electrode and may be RF-isolated from the second control electrode, according to an embodiment.
The amplifier device may further include a second amplifier electrically coupled to a second input terminal and a second output terminal, wherein the second amplifier may include a third transistor that includes a third control electrode, a fifth current-carrying electrode and a sixth current carrying electrode, configured to support a current flow between the fifth-current-carrying electrode and the sixth current-carrying electrode, wherein the third control electrode is configured to control the current flow between fifth current-carrying electrode and the sixth current-carrying electrode, wherein the third control electrode may be RF coupled to the second input terminal, and wherein the fifth current-carrying electrode may be electrically coupled to the second output terminal, according to an embodiment. A third bias network may be electrically coupled to the third control electrode, wherein the third bias network may be configured to apply a third DC bias to the third control electrode and may be RF-isolated from the third control electrode, according to an embodiment. A fourth transistor that includes a fourth control electrode, a seventh current-carrying electrode and an eighth current carrying electrode, configured to support a current flow between the seventh-current-carrying electrode and the eighth current-carrying electrode, wherein the fourth control electrode is configured to control the current flow between seventh current-carrying electrode and the eighth current-carrying electrode, wherein the fourth control electrode may be radio frequency (RF) coupled to the second input terminal, and wherein the seventh current-carrying electrode may be electrically coupled to the second output terminal, according to an embodiment. In an embodiment, a fourth bias network may be electrically coupled to the fourth control electrode, wherein the fourth bias network may be configured to apply a fourth DC bias to the second control electrode and may be RF-isolated from the fourth control electrode.
In an embodiment, the amplifier device may also include a transmission line having a phase shift and may be configured to electrically couple the first output terminal and the second output terminal. An impedance transformer may be electrically coupled to a summing node at the element selected from the group consisting of the first output terminal and the second output terminal.
In an embodiment, the amplifier device may include a splitter device having a splitter input and a first splitter output and a second splitter output and configured to divide a signal delivered to the splitter input between the first splitter output and the second splitter output with a splitter phase difference between the first splitter output and the second splitter output, wherein a difference between the phase difference and the phase shift of the transmission line is less than twenty percent, wherein the first input terminal is electrically coupled to the first splitter output and the second input terminal is electrically coupled to the second splitter output.
In an embodiment, the first amplifier may be configured as a carrier amplifier and the second amplifier may be configured as a peaking amplifier.
In an embodiment, the first amplifier may be configured to operate in a first state and to operate in a second state, according to an embodiment. In an embodiment, when in the first state, the first transistor and the second transistor may be configured to operate with a first bias applied to the first bias network, a second bias applied to the second bias network, wherein the first bias and second bias allow an RF current of at least fifty percent of the maximum current of the second transistor may flow from the third current-carrying electrode to the fourth current-carrying element of the second transistor when the first transistor is operated at a saturated output power, and a third bias applied to the first current-carrying electrode and to the third current-carrying electrode, according to an embodiment. When operating in the second state, the first transistor and the second transistor may be configured to operate with the first bias applied to the first bias network, a fourth bias applied to the second bias network such that the fourth bias allows an RF current of less than ten percent of the maximum current of the second transistor flows through the second transistor when the first transistor is operated at a saturated output power, and a fifth bias applied to the first current-carrying electrode and to the third current-carrying electrode, according to an embodiment.
In an embodiment, the first transistor may be configured as a field effect transistor, wherein the first control terminal may be configured as a gate electrode, wherein the first current-carrying element may be configured as a drain electrode, and wherein the second current-carrying element may be configured as a source electrode.
An embodiment may include a first coupling element having a first terminal and a second terminal, wherein the second terminal may be electrically coupled to the first control electrode.
An embodiment may include a second coupling element having a third terminal and a fourth terminal, wherein the fourth terminal may be electrically coupled to the second control electrode, and wherein the first terminal may be electrically coupled to the third terminal.
A driver amplifier comprising a transistor may be electrically coupled to the first terminal of the first coupling element and to the third terminal of the second coupling element.
An embodiment may include a first input harmonic matching network, configured to provide a harmonic termination for the first transistor at a harmonic frequency and may also include a second harmonic matching network, configured to provide a harmonic termination for the second transistor at the harmonic frequency.
In another aspect, an embodiment may include a power amplifier device comprising a first amplifier electrically coupled to a first input terminal and to a first output terminal. The first amplifier may include a first field effect transistor that includes a first gate electrode, a first drain electrode and a first source electrode, configured to support a current flow between the first drain electrode and the first source electrode, wherein the first gate electrode may be configured to control the current flow between the first drain electrode and the first source electrode, wherein the gate electrode may be radio frequency (RF) coupled to the first input terminal, and wherein the first drain electrode may be electrically coupled to the first output terminal, according to an embodiment. In an embodiment, a first bias network may be electrically coupled to the first gate electrode, wherein the first bias network may be configured to apply a first direct current (DC) bias to the first gate electrode and may be RF-isolated from the first gate electrode. In an embodiment, a second field effect transistor may include a second gate electrode, a second drain electrode and a second source electrode, configured to support a current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be configured to control the current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be RF coupled to the first input terminal, wherein the second drain electrode may be electrically coupled to the first output terminal. A second bias network may be electrically coupled to the second gate electrode, wherein the second bias network may be configured to apply a second DC bias to the second gate electrode and may be RF-isolated from the second gate electrode, according to an embodiment.
In an embodiment, a first capacitor having a first terminal and a second terminal, may be electrically coupled to the first gate electrode by its second terminal. A second capacitor having a third terminal and a fourth terminal, wherein the fourth terminal may be electrically coupled to the second gate electrode, and wherein the first terminal may be electrically coupled to the third terminal, according to an embodiment. In an embodiment, a first input matching network may be electrically coupled to the first gate electrode and configured to provide an impedance match for the first field effect transistor at a fundamental frequency and a second input matching network, may be electrically coupled to the second gate electrode and configured to provide an impedance match for the second transistor at the fundamental frequency.
A second amplifier may be electrically coupled to a second input terminal and a second output terminal, according to an embodiment. In an embodiment, the second amplifier may include a third field effect transistor that includes a third gate electrode, a third drain electrode and a third source electrode, configured to support a current flow between the third drain electrode and the third source electrode, wherein the third gate electrode is configured to control the current flow between the third drain electrode and the third source electrode, wherein the third gate electrode may be RF coupled to the second input terminal, and wherein the third drain electrode may be electrically coupled to the second output terminal. A third bias network may be electrically coupled to the third gate electrode, wherein the third bias network may be configured to apply a third DC bias to the third gate electrode and may be RF-isolated from the third gate electrode. An embodiment may include a fourth field effect transistor that includes a fourth gate electrode, a fourth drain electrode and a fourth source electrode, configured to support a current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode is configured to control the current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode may be radio frequency (RF) coupled to the second input terminal, and wherein the fourth drain electrode may be electrically coupled to the second output terminal. A fourth bias network may be electrically coupled to the fourth gate electrode, wherein the fourth bias network may be configured to apply a fourth DC bias to the fourth gate electrode and may be RF-isolated from the fourth gate electrode, according to an embodiment. In an embodiment, a transmission line having a phase shift may be configured to electrically couple the first output terminal and the second output terminal. An impedance transformer may be electrically coupled to a summing node at one of the first output terminal and the second output terminal, according to an embodiment. In an embodiment, a splitter device having a splitter input and a first splitter output and a second splitter output and configured to divide a signal delivered to the splitter input between the first splitter output and the second splitter output with a splitter phase difference between the first splitter output and the second splitter output, wherein a difference between the splitter phase difference and the phase shift of the transmission line may be less than twenty percent, may be coupled to the first input terminal at the first splitter output and the second input terminal may be electrically coupled to the second splitter output. A first amplifier may be configured as a carrier amplifier and the second amplifier may be configured as a peaking amplifier in a Doherty amplifier configuration, according to an embodiment.
An embodiment may include a first input harmonic matching network, configured to provide a harmonic termination for the first transistor at a harmonic frequency and a second harmonic matching network, configured to provide a harmonic termination for the second transistor at the harmonic frequency.
A driver amplifier comprising a transistor may be electrically coupled to the first terminal of the first capacitor and to the third terminal of the second capacitor, according to an embodiment.
In another aspect, an embodiment may include an apparatus that includes a base substrate, a first amplifier die coupled to the base substrate and electrically coupled to a first input terminal and to a first output terminal. In an embodiment, the first amplifier die may include a first field effect transistor that may include a first gate electrode, a first drain electrode, and a first source electrode, configured to support a current flow between the first drain electrode and the first source electrode, wherein the first gate electrode is configured to control the current flow between the first drain electrode and the first source electrode, wherein the gate electrode may be radio frequency (RF) coupled to the first input terminal, and wherein the first drain electrode is electrically coupled to the first output terminal. A first bias network may be electrically coupled to the first gate electrode, wherein the first bias network may be configured to apply a first direct current (DC) bias to the first gate electrode and may be RF-isolated from the first gate electrode, according to an embodiment. In an embodiment, a second field effect transistor may include a second gate electrode, a second drain electrode, and a second source electrode, configured to support a current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be configured to control the current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be RF coupled to the first input terminal, wherein the second drain electrode may be electrically coupled to the first output terminal. A second bias network may be electrically coupled to the second gate electrode, wherein the second bias network may be configured to apply a second DC bias to the second gate electrode and may be RF-isolated from the second gate electrode, according to an embodiment. An embodiment may include a first capacitor having a first terminal and a second terminal, wherein the second terminal may be electrically coupled to the first gate electrode. An embodiment may include a second capacitor element having a third terminal and a fourth terminal, and wherein the fourth terminal may be electrically coupled to the second gate electrode, and wherein the first terminal may be electrically coupled to the third terminal. A first input matching network may be electrically coupled to the first gate electrode and configured to provide an impedance match for the first field effect transistor at a fundamental frequency and a second input matching network and may be configured to provide an impedance match for the second field effect transistor at the fundamental frequency, according to an embodiment.
In an embodiment, the first field effect transistor and the second field effect transistor may be integrally formed on a first substrate, and wherein the first capacitor and the second capacitor may be formed on the first substrate.
In an embodiment, the first field effect transistor and the second field effect transistor may be formed on a first substrate, and the first capacitor and the second capacitor may be formed on a second substrate.
An embodiment may include a driver amplifier comprising a transistor formed on the second substrate, wherein the driver amplifier may be electrically coupled to the first terminal of the first capacitor and may be coupled to the third terminal of the second capacitor. The first bias network may be formed on the second substrate and the second bias network may be formed on the second substrate, according to an embodiment.
In an embodiment, a second amplifier may be coupled to the base substrate and may be electrically coupled to a second input terminal and a second output terminal, wherein the second amplifier may include a third transistor that includes a third gate electrode, a third drain electrode and a third source electrode, configured to support a current flow between the third drain electrode and the third source electrode. The third gate electrode is configured to control the current flow between the third drain electrode and the third source electrode, wherein the third control electrode is RF coupled to the second input terminal, and wherein the third drain electrode may be electrically coupled to the second output terminal, according to an embodiment. In an embodiment, a third bias network may be electrically coupled to the third gate electrode, wherein the third bias network may be configured to apply a third DC bias to the third gate electrode and may be RF-isolated from the third gate electrode. A fourth transistor may include a fourth gate electrode, a fourth drain electrode and a fourth source electrode an is configured to support a current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode may be configured to control the current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode may be radio frequency (RF) coupled to the second input terminal, and wherein the fourth drain electrode may be electrically coupled to the second output terminal, according to an embodiment. In an embodiment, a fourth bias network may be electrically coupled to the fourth gate electrode, wherein the fourth bias network may be configured to apply a fourth DC bias to the fourth gate electrode and may be RF-isolated from the fourth gate electrode. A transmission line formed over the base substrate having a phase shift and may be configured to electrically couple the first output terminal and the second output terminal, according to an embodiment. An impedance transformer may be formed over the base substrate and may be electrically coupled to a summing node at one of the first output terminal and the second output terminal, according to an embodiment. In an embodiment, a splitter device may be formed over the base substrate having a splitter input and a first splitter output and a second splitter output and configured to divide a signal delivered to the splitter input between the first splitter output and the second splitter output with a splitter phase difference between the first splitter output and the second splitter output, wherein a difference between the phase difference and the phase shift of the transmission line is less than twenty percent, wherein the first input terminal may be electrically coupled to the first splitter output and the second input terminal is electrically coupled to the second splitter output. The first amplifier may be configured as a carrier amplifier and the second amplifier may be configured as a peaking amplifier in a Doherty amplifier configuration, according to an embodiment.
The amplifier device embodiments provided herein may overcome some or all of the aforementioned issues with high-efficiency amplifiers. Specifically, the amplifier device embodiments described herein are configured to allow biasing of transistors within amplifier devices in deep class-C bias to effectively reduce the total size of the active transistors within the amplifier. Such biasing for reduced effective size of active transistors may be useful for increasing the efficiency of amplifier devices during times of low-power operation (e.g., during low traffic in a radio network).
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation described herein as exemplary, or an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
According to an embodiment, first amplifier 101 may include a first field effect transistor 110 (i.e., “first transistor”) that may include a first gate electrode 112 (i.e., “first control electrode”), a first drain electrode 114 (i.e., “first current-carrying electrode”), and a first source electrode 116 (“i.e. second current-carrying electrode”), configured to support a current flow between the first drain electrode 114 and the first source electrode 116, wherein the first gate electrode 112 physically and electrically separates the first source electrode 116 and the first drain electrode 114 and may be configured to control current flow in a variable conductivity channel between the first drain electrode 114 and the first source electrode 116, wherein the gate electrode is radio frequency (RF) coupled to the first input terminal 102, and wherein the first drain electrode 114 is electrically coupled to the first output terminal 127. In an embodiment, the first source electrode 116 of first transistor 110 may be electrically coupled to ground potential 115.
In an embodiment, a first bias network 118 may be electrically coupled to the first gate electrode 112, wherein the first bias network 118 may be configured to apply a first direct current (DC) bias 119 (i.e., “first bias”) to the first gate electrode 112 and is RF-isolated from the first gate electrode 112. As used herein, the term “RF-isolated” means that radio-frequency (RF) coupling between two components that are RF-isolated is less than −20 dB, according to an embodiment. In other embodiments, RF coupling between two components that are RF-isolated is less than −10 dB, though higher or lower values may be used. In an embodiment, a second field effect transistor 120 (i.e., “second transistor”) that includes a second gate electrode 122 (i.e., “second control electrode”), a second drain electrode 124 (i.e., “third current-carrying electrode”), and a second source electrode 126 (i.e., “fourth current-carrying electrode”), may be configured to support a current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be configured to control the current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be RF coupled to the first input terminal 102, wherein the second drain electrode 124 may be electrically coupled to the first output terminal 127. A second bias network 128 may be electrically coupled to the second gate electrode 122, wherein the second bias network 128 may be configured to apply a second DC bias 129A/129B to the second gate electrode 122 and may be RF-isolated from the second gate electrode 122, according to an embodiment. In an embodiment, the source electrodes 126 of second transistor 120 may be electrically coupled to ground potential 125.
Still referring to
In an embodiment, a fourth transistor 140 that includes a fourth gate electrode 142, a fourth drain electrode 144, and a fourth source electrode 146, may be configured to support a current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 may be configured to control the current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 may be radio frequency (RF) coupled to the second input terminal 106, and wherein the fourth drain electrode 144 may be electrically coupled to the second output terminal, according to an embodiment. A fourth bias network 148 electrically coupled to the fourth gate 142 electrode, wherein the fourth bias network 148 may be configured to apply fourth DC bias 149A/149B to the fourth gate electrode 142 and may RF-isolated from the fourth gate electrode 142. In an embodiment, the source electrode 146 of fourth transistor 140 may be electrically coupled to ground potential 145.
In an embodiment, the first, second, third, and fourth transistors 110, 120, 130, 140 may include field effect transistors (FET's) (such as heterojunction FET's (HFET's), metal-semiconductor FET's (MESFET's), or metal oxide semiconductor FET's (MOSFET's)), each of which include a gate (control terminal), a source (a first current-carrying terminal), and a drain (a second current-carrying terminal). For convenience of explanation and not for limitation, various embodiments of the invention will be illustrated using GaN HFET active devices for amplifier device 100 and silicon laterally diffused metal oxide semiconductor devices (LDMOS) devices for the driver amplifiers 308, 408 of
In an embodiment, the first transistor 110 may have a total gate width of between about 0.5 and about 50 millimeters (mm) (e.g., about 1 mm), although higher or lower values of the total gate width may be used in some embodiments. In an embodiment, first, second, third, and fourth transistors 110, 120, 130, and 140 have an input capacitance (i.e., gate-source capacitance) between first, second, third, and fourth gate electrodes 112, 122, 132, and 142 and first, second, third, and fourth source electrodes 116, 126, 136, and 146 of the first, second, third, and fourth transistors 110, 120, 130, 140. In an example embodiment, the first, second, third, and fourth transistors 110, 120, 130, 140 have a gate source capacitance between about 0.5 pF per millimeter of gate periphery (pF/mm) and about 3.5 pF/mm (e.g., 2.5 pF/mm), though higher or lower values may be used. In an embodiment, the first second, third, and fourth transistors 110, 120, 130, and 140 have an output capacitance (i.e., drain-source capacitance) between first, second, third, and fourth drain terminals 114, 124, 134, 144 and first, second, third, and fourth source electrodes 116, 126, 136, and 146. In an embodiment, first. second, third, and fourth transistors 110, 120, 130, and 140 have a drain-source capacitance between about 0.2 pF per millimeter of gate periphery (pF/mm) and about 1 pF/mm (e.g., about 0.4 pF/mm), though other higher or lower values may be used.
In an embodiment, first and second amplifiers 101 and 105 may be combined in a Doherty configuration. To this end, a transmission line 150 may be used in conjunction with the output capacitances of first, second, third, and fourth transistors 110, 120, 130, and 140 to achieve a phase shift between the outputs 127 and 137 of first and second amplifiers 101 and 105. Transmission line 150 may be configured to electrically couple the first output terminal 127 and the second output terminal 137, according to an embodiment. In an embodiment, the phase shift may be between about 80 and 100 degrees. In an embodiment, the phase shift introduced in part by transmission line 150 may be added to phase shift arises from capacitive loading of the output capacitance of first, second, third and fourth transistors 110, 120, 130, and 140 as well as additional inductance coupled in series at one or more ends of the transmission line 150 (not shown). Thus, a transmission line phase shift due only to transmission line 150 may be less than the phase shift and may be to achieve the desired amount of phase shift. For example, the transmission line phase shift may be, e.g., 20 degrees to 50 degrees, but due to output capacitance of transistors 110, 120, 130, 140, and possibly additional capacitors and inductors (not shown), the phase shift may be approximately 90 degrees, e.g., 80 and 100 degrees. In other embodiments, the phase shift may have higher or lower values, e.g., 30 to 120 degrees, depending on the application. In an embodiment, an impedance transformer 152 may be electrically coupled to second output 137 that creates a summing node at second output 137 and to output terminal 108. As used herein, the term “summing node” refers to a point at which a peaking amplifier is electrically connected to a carrier or main amplifier in, e.g., a Doherty amplifier configuration.
In other embodiments, the summing node and connection to impedance transformer 152 may be at the first output terminal 127. In these embodiments, first amplifier 101 may be configured as a carrier amplifier and second amplifier 105 may be configured as a peaking amplifier. In these embodiments, transmission lines having phase shifts approximating the phase difference of the splitter (e.g., 90 degrees) may be added to the carrier amplifier path and to the peaking amplifier path (not shown). A splitter 153 having a splitter input 155, a first splitter output 156, and a second splitter output 157 may be configured to divide a signal delivered to the splitter input 155 between the first splitter output 156 and the second splitter output 157 with a splitter phase difference between the first splitter output 156 and the second splitter output 157, according to an embodiment. In an embodiment, the splitter phase difference may be between about 45 degrees and about 135 degrees. In an embodiment, a difference between the splitter phase difference and the phase shift associated with transmission line 150 and second splitter output 157 may be less than twenty percent of the splitter phase difference. In an embodiment, the first amplifier 101 may be configured as a carrier amplifier and the second amplifier 105 may be configured as a peaking amplifier in a Doherty amplifier configuration.
In an embodiment, the first and second amplifiers 101, 105 may be configured to operate in high power state 161 depicted in
In an embodiment, amplifier device 100 may be operated in a transmitter system, wherein individual power supplies (not shown) may be used to supply first bias 119, second bias 129, third bias 139A/139B, fourth bias 149A/149B, and fifth bias 109A/109B. According to an embodiment, a bias controller (not shown) may be used to control the voltage levels provided for first bias 119, second bias 129A/129B, third bias 139, fourth bias 149A/149B, and fifth bias 109A/109B. In an embodiment, the bias controller may sense the traffic level in the amplifier system and, therefore, the output power required for amplifier device 100. As a result, the bias voltages applied to first and third biases 119, 139, second and fourth biases, 129A/129B, 149A/149B, and fifth bias 109A/109B, may be adjusted to optimize the efficiency of amplifier device 100.
For example, and in and in an embodiment, where first amplifier 101 is configured as a carrier amplifier and second amplifier 105 is configured as a peaking amplifier with first, second, third and fourth transistors 110, 120, 130, and 140 based on gallium nitride (GaN) transistor technology, the first, second, and fifth biases 119, 129A, 109A corresponding to high-power state 161 may include a gate voltage (e.g., gate bias of −2.5 V to −2.9V or approximately 0.1 to 0.5 V above a threshold voltage of −3V) that corresponds to a class A-B quiescent drain current bias, e.g., less than five percent of the full channel current of first transistor 110, and fifth bias 109A applied to the first, second, third, and fourth drain electrodes 114, 124, 134, 144 (e.g. a drain voltage of 48V) that corresponds to high-power operation, according to an embodiment. Likewise, the third and fourth biases 139, 149A of third and fourth transistors 130 and 140 of second amplifier 105 may include a gate voltage that corresponds to a class C bias, e.g., approximately zero current with a gate bias between approximately 0.1V and 2V below a threshold voltage (e.g. −3.1 V to −2V for −3V threshold voltage), while fifth bias 109A (e.g. 50V) is applied to drain electrodes 134, 144 of the third and fourth transistors 130, 140 according to an embodiment.
For example, and in an embodiment, where first amplifier 101 is configured as a carrier amplifier and second amplifier 105 is configured as a peaking amplifier with first, second, third and fourth transistors based on gallium nitride (GaN) transistor technology, the first bias 119 corresponding to low-power state 162 may include a gate voltage (e.g., gate bias of approximately −2.5 V to −2.9V or approximately 0.1 to 0.5 V above a threshold voltage of −3V) that corresponds to a class A-B bias, e.g., a quiescent drain current less than ten percent of the full channel current of first transistor 110, according to an embodiment. Likewise, the third bias 139 applied to third transistor 130 of second amplifier 105 may include a gate voltage that corresponds to a class C bias for transistor 130 (e.g., approximately zero current with a gate bias between approximately 0.1V and 1V below a threshold voltage (e.g. −3.1 V to −4V for −3V threshold voltage).The second and fourth biases 129B, 149B applied to the second and fourth bias networks 128, 148 may correspond to a deep class C condition (e.g., a gate bias of −8V, approximately 5V below the threshold voltage of approximately −3V) for second and fourth transistors 120, 140. Likewise, the fifth bias 109B applied to the first, second, third, fourth drain electrodes 114, 124, 134, 144 (e.g., a drain voltage of 28V) corresponds to low-power operation, according to an embodiment. In low-power state 162, the effect of the third and fourth biases 129B and 149B biasing transistors 120, 140 in deep class C may have the effect to reduce the overall effective gate periphery of first amplifier 101 and second amplifier 105 since the devices are operated in deep depletion and do not contribute current to the operation of amplifier device 100, according to an embodiment.
In an embodiment, a second field effect transistor 120 may include a second gate electrode 122, a second drain electrode 124, and a second source electrode 126, configured to support a current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be configured to control the current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be RF-coupled to the first input terminal 302, wherein the second drain electrode 124 may be electrically coupled to the first output terminal 127. A second bias network 380 that includes RF bypass capacitor 382 coupled to ground 383 and inductor 386 may be electrically coupled to the first gate electrode through inductor 386, may be electrically coupled to the second gate electrode 122, wherein the second bias network 380 may be configured to apply a second DC bias to the second gate electrode 122 through terminal 384, inductor 386, terminal 388, and bond wire 389 and may be RF-isolated from the second gate electrode 122, according to an embodiment. In an embodiment, the values of components of second bias network 380 (e.g., RF bypass capacitor 382 and inductor 386) may be analogous to those of first bias network 370.
In an embodiment, circuitry 390 that includes a first capacitor 394 (i.e., “first coupling element”) having a first terminal 394A and a second terminal 394B, may be electrically coupled to the first gate electrode 112 through terminal 395 and bond wire 398 by its second terminal 394B. A second capacitor 396 (i.e., “second coupling element”) having a third terminal 396A and a fourth terminal 396B, may be electrically coupled by terminal 397 via the fourth terminal 396B and bond wire 399 to the second gate electrode 122. The first terminal 394A may be electrically coupled to the third terminal 396A, according to an embodiment. In an embodiment, a first input matching network that may include bond wires 369, 379, and 398 may be electrically coupled to the first gate electrode 112 through terminals 368, 378, 395 and may be configured to provide an impedance match for the first transistor 110 at a fundamental frequency. A second input matching network that may include bond wires 359, 389, and 399 may be electrically coupled to the second gate electrode 122 and may be configured to provide an impedance match for the second transistor 120 at the fundamental frequency.
An embodiment may include first and input harmonic matching networks 350, 360 that includes capacitors 352, 362 and inductors 354, 364 connected in series and electrically coupled to grounds 356, 366 and may be configured to provide a harmonic termination for the first transistor 110 at a harmonic frequency. An embodiment may also include input harmonic matching networks 350, 360 that may include capacitors 352, 362 and inductors 354, 364 connected in series and electrically coupled to ground 356, 366 and to terminals 358, 368 and is configured to provide a harmonic termination for the first and second transistors 110, 120 at the harmonic frequency. In an embodiment, capacitors 352, 362 may have values between about 0.3 picofarads and about 5 picofarads, although other higher or lower values may be used. Inductors 354, 364 may have values of between about 0.3 nanohenries and about 2 nanohenries although other higher or lower values may be used, according to an embodiment.
A driver amplifier 308 may be electrically coupled to the first terminal 394A of the first capacitor and the third terminal 396A of the second capacitor and may be RF-coupled to first input terminal 302 through series capacitor 312 and from first input terminal 302 to first external input terminal 305. Transistor 330 is the primary active device of driver amplifier 308 and includes a gate electrode 332, source terminal 334, and drain electrode 336. In an embodiment, driver amplifier 308 may be coupled to first external input terminal 305 through bond wire 303 and may include an input matching network 310 coupled to the gate electrode 332 of transistor 330, input bias networks 320 coupled to the gate electrode 332 and driver drain bias networks 340 coupled to the drain electrode 336 of the transistor 330. Driver amplifier 308 may be coupled to first and second capacitors 394 and 396 through inductor 392 which may be configured to provide impedance matching, according to an embodiment.
In an embodiment, input matching network 310 may include a “T” network that includes input match inductors 314, 318 that are electrically coupled together in series at a point coupled to ground by input match capacitor 316. Input match inductors 314, 318 may have values between about 0.1 nanohenries and about 5 nanohenries, according to an embodiment. Input match capacitor may have a value of between about 0.5 picofarads and about 2 picofarads, according to an embodiment. In an embodiment, input bias network 320 may include DC block 321 that includes RF bypass capacitor 322 and DC ground 323 may be electrically coupled to the gate electrode 332 through inductor 325 and resistor 327, wherein the input bias networks 320 may be configured to apply a first direct current (DC) bias to the gate electrode 332. In an embodiment, RF bypass capacitor 322 may have a value between about 2 picofarads and about 50 picofarads, although other higher or lower values may be used. Inductor 325 may have a value of between about 5 nanohenries and about 100 nanohenries although other higher or lower values may be used, according to an embodiment. Resistor 327 may have a value between about 1 ohm and about 1000 ohms, according to an embodiment. Terminal 328 is used to provide a connection of the input bias network to the DC gate bias. In an embodiment, driver drain bias networks 340 may include DC block 341 that includes RF bypass capacitor 342 and RF grounds 343 and may be electrically coupled to the drain electrode 336 through inductor 345, wherein the driver drain bias networks 340 may be configured to apply a first direct current (DC) bias to the drain electrode 336 through terminal 348. In an embodiment, RF bypass capacitor 342 may have a value between about 2 picofarads and about 50 picofarads, although other higher or lower values may be used. Inductor 345 may have a value of between about 5 nanohenries and about 100 nanohenries although other higher or lower values may be used, according to an embodiment.
In an embodiment, other components included in second power amplifier device 400, (e.g. second external input terminal 405, bond wire 403, second input terminal 402, bond wire 407, driver amplifier 408, output terminal 409, input matching network 410, input match inductors 414, 418, input match capacitor 416, input bias networks 420, DC block 421, RF bypass capacitor 422, DC ground 423, inductor 425, resistor 427, driver terminals 428, 448, transistor 430, transistor gate electrode 432, transistor drain electrode 436, transistor source electrode 434, output bias networks 440, DC block 441, RF bypass capacitor 442, RF ground 443, inductor 445, series capacitor 412, coupling circuitry 490, inductor 492, first capacitor 494, second capacitor 496, bond wires 479, 489, 498, 499) have been described in connection with first power amplifier device 300 in
In this example embodiment, second power amplifier device 400 does not include input harmonic termination networks as are included in first power amplifier device 300 of
Apparatus 500 may include a base substrate 510, a first power amplifier device 300 coupled to the base substrate 510 and electrically coupled to a first input terminal 302 through driver and bias circuitry 301 and to a first output terminal 127. In an embodiment, the first amplifier 101 may include a first field effect transistor 110 that may include a first gate electrode 112, a first drain electrode 114, and a first source electrode 116 (not shown). A first bias network 370 (within driver and bias circuitry 301, not shown) may be electrically coupled to the first gate electrode 112 through bond wire 379, terminal 378, first bias network 370 (shown in
In an embodiment, a second power amplifier device 400 may be coupled to the base substrate 510 and may be electrically coupled to a second input terminal 402 and a second output terminal 137, wherein the second power amplifier device 400 may include a third transistor 130 that includes a third gate electrode 132, a third drain electrode 134, and a third source electrode 136 (not shown), configured to support a current flow between the third drain electrode 134 and the third source electrode 136 (see
In an embodiment, the first transistor 110 and the second transistor 120 may be integrally formed on a first substrate 509A, and the first capacitor 394 and the second capacitor 396 may be formed on a second substrate 511A, with terminals 395, 397 as part of driver and bias circuitry 301. In other embodiments, the first transistor 110 and the second transistor 120 may be formed on first substrate 509A, and the first capacitor and the second capacitor may be formed on the first substrate 509A (not shown). Analogously, and in an embodiment, the third transistor 130 and the fourth transistor 140 may be integrally formed on a third substrate 509B, and the first capacitor 494 and the second capacitor 496 may be formed on a fourth substrate 511B with terminals 495, 497, respectively, and as part of driver and bias circuitry 401.
An embodiment may include driver and bias circuitry 301, 401 that includes transistors 330, 430 formed on the third and fourth substrates 509B, 511B wherein the driver amplifier may be electrically coupled to the first terminal of the first capacitor and may be coupled to the third terminal of the second capacitor. The first bias network 370 and the second bias network 380 may be formed on the second substrate 511A, according to an embodiment. The third bias network 470 and the fourth bias network 480 may be formed on the fourth substrate 511B, according to an embodiment. Terminals 328, 348 and 428, 448 that provide biasing to transistors 330 and 430 may be coupled to module terminals 528A, 548A and 528B, and 548B, respectively for connections to external power supplies.
In an embodiment, a splitter 153 may be formed over the base substrate 510 having a splitter input 155 and a first splitter output 156 and a second splitter output 157 and configured to divide a signal delivered to the splitter input 155 between the first splitter output 156 and the second splitter output 157 with a splitter phase difference between the first splitter output and the second splitter output, wherein a difference between the splitter phase difference and the phase shift associated with transmission line 150 is less than twenty percent, wherein the first input terminal 102 may be electrically coupled to the first splitter output 156 and the second input terminal 106 is electrically coupled to the second splitter output 157. Expressing this differently, the phase shift of the transmission line 150 may approximate the splitter phase difference such that their difference is less than about twenty percent. As used herein, the “phase shift of [a] transmission line” means the phase shift encountered by a signal and includes the effect of the phase shift of the transmission line and any loading of the transmission line by other circuit components (e.g., capacitances and inductances). Thus, in an embodiment, the phase shift of the transmission line 150 also includes the effect of output capacitances of third transistor 130 and fourth transistor 140 and/or additional matching elements (not shown) seen at output terminal 137. The first power amplifier device 300 may be configured as a carrier amplifier and the second power amplifier device 400 may be configured as a peaking amplifier in a Doherty amplifier configuration, according to an embodiment. In an embodiment, splitter 153 may be realized using a compact hybrid coupler wherein branches of the compact hybrid coupler are realized in a compact form-factor using lumped element capacitors 558, inductors 559, and termination resistor 554. A coupling capacitor 555 may RF couple second splitter output 157 to the second power amplifier device 400. In other embodiments, the splitter 153 may be realized using a branch line coupler. In other embodiments, the splitter 153 may be realized using a Lange coupler. In still other embodiments, the splitter 153 may be realized using a Wilkinson power divider with and extra transmission line length used to achieve a phase difference between the first splitter output 156 and the second splitter output 157. Splitter input 155 may be coupled to module input 502 with coupling capacitor 504.
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An amplifier device includes a first input terminal, a second input terminal, a first transistor having a first control electrode and first and second current-carrying electrodes, wherein the first control electrode is radio frequency (RF) coupled to the first input terminal and DC-coupled to a first bias network electrically coupled to the first control electrode, wherein the first bias network is configured to apply a first direct current (DC) bias to the first control electrode and is RF-isolated from the first control electrode. The amplifier device further includes a second transistor that includes a second control electrode that is RF coupled to the second input terminal and a second bias network electrically coupled to the second transistor, wherein the second bias network is configured to apply a second DC bias to the second transistor and is RF-isolated from the second transistor.
For the sake of brevity, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first,” “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.
As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).
The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 23306374.2 | Aug 2023 | EP | regional |
