Amplifier system switchable between two amplifying operations

Abstract

An amplifier switchable between a dual-channel amplifier and a BTL amplifier includes first and second amplifying circuits having a non-inverting input, an inverting input and an output, a first input terminal receiving a first input signal and applying it to the non-inverting input of the first amplifying circuit, a second input terminal receiving a second input signal, a first switch selectively applying a signal to the non-inverting input of the first or second amplifying circuit, a second switch controlling the application of an output from the first amplifying circuit to the inverting input of the second amplifying circuit, a controlling circuit controlling the first and second switches, first through third loads and a third switch controlling the application of an output from the first and second amplifying circuits to the first and second loads, respectively, or to the respective ends of the third load.

Description

BACKGROUND OF THE INVENTION

This invention relates to an amplifier system, and more particularly, to a system which is switchable between two amplifying operations.

Audio signal power amplifiers can be classified into a single-channel amplifier and a dual-channel amplifier. The single-channel amplifier amplifies a monaural signal, and the dual-channel amplifier is used to amplify a stereophonic signal.

Examples of these amplifiers are shown in FIGS. 1 and 2 in block diagrams. FIG. 1 is a conventional dual-channel amplifier and FIG. 2 is a BTL type single-channel amplifier which uses two amplifiers to produce a large output.

Referring to FIG. 1, a main part 100 of the single-channel amplifier is formed in a semiconductor integrated circuit which includes two feedback amplifiers 200 and 300 and two feedback resistors R.sub.f3 and R.sub.f4. Each of the feedback amplifiers 200 and 300 has an inverting input (-) and a non-inverting input (+). These amplifiers 200 and 300 are energized by a power supply source Vcc. A first input signal V.sub.S1 is applied to the non-inverting input (+) of the amplifier 200. A series connection of a resistor R.sub.f1 and a capacitor C1 is connected between the inverting input (-) of the amplifier 200 and ground to form a feedback circuit together with the feedback resistor R.sub.f3. An output terminal of the amplifier 200 is connected to a first load R.sub.L1 through a capacitor C.sub.3. Similarly, a second input signal V.sub.S2, a resistor R.sub.f2, capacitors C.sub.2 and C.sub.4 and a second load R.sub.L2 are connected to the amplifier 300.

The amplifiers 200 and 300 amplify respectively, the first and second input signals V.sub.S1 and V.sub.S2 and their amplification functions are independent of each other. This arrangement is preferable for amplifying a stereophonic signal.

Another type of amplifier is shown in FIG. 2 and is a BTL amplifier having a feature that a large voltage output can be obtained. In more detail, a main part 100 has a circuit configuration similar to the main part 100 of FIG. 1 with the difference residing in the circuit configuration outside the main part 100. An input signal V.sub.S3 is introduced to the non-inverting input (+) of the amplifier 200 and the resistors R.sub.f1 and R.sub.f3 and the capacitor C.sub.1 are connected to the amplifier 200 to form a feedback amplifier similar to FIG. 1. The output of the amplifier 200 is connected to one end of a load R.sub.L3 and to one end of a resistor R.sub.a5. A signal attenuated by a voltage divider composed of the resistor R.sub.a5 and a resistor R.sub.f2 is applied to the inverting input (-) of the amplifier 300 through a capacitor C.sub.2. The non-inverting input (+) of the amplifier 300 is grounded through a capacitor C.sub.5. A resistor R.sub.f4 is provided to operate the amplifier 300 as a feedback amplifier. An output of the amplifier 300 is connected to the other end of the load R.sub.L3.

With the BTL amplifier of FIG. 2, the output applied to one end of the load R.sub.L3 through the amplifier 200 has a reverse phase to that applied to the other end of the load R.sub.L3 through the amplifier 300. Therefore, the output obtained at the load R.sub.L3 is twice the output at the loads R.sub.L1 and R.sub.L2. This amplifier is preferable for producing a large output.

Referring to FIGS. 1 and 2, both amplifiers use the same main part 100. Thus, by changing the circuit outside the main part 100, it is possible to change the amplifier of FIG. 1 to the amplifier of FIG. 2 and vice versa. However, it is difficult in fact to assemble the amplifier so as to be switchable between either configuration. Further, there has been proposed no integrated circuit integrating two amplifiers with a switching circuit for changing the amplifier function. Because of this fact, a switchable amplifier using a conventional integrated circuit requires a number of circuit elements to be combined with the integrated circuit.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an amplifier switchable between a dual-channel amplifier and a BTL amplifier.

It is another object of the present invention to provide a switchable amplifier suitable for an integrated circuit.

According to the present invention, a switchable amplifier includes a first and a second amplifying circuit each having an inverting input and a non-inverting input and an output, a first input terminal connected to the noninverting input of the first amplifying circuit, a second input terminal, a first output terminal receiving an output from the first amplifying circuit, a second output terminal receiving an output from the second amplifying circuit, a first switch coupled between the second input terminal and the non-inverting input of the second amplifying circuit, a second switch coupled between the first and second input terminals, a third switch coupled between the first output terminal and the inverting input of the second amplifying circuit and a control circuit controlling the ON-OFF conditions of the first, second and third switches, the ON-OFF condition of the first switch being kept opposite to the ON-OFF conditions of the second and third switches.

The switchable amplifier of the present invention can be changed by the control circuit from a dual-channel amplifier to a BTL amplifier and vice versa, and the circuit configuration for changing its function is simple. Further, the first, second and third switches and the main part of the control circuit can be built on a semiconductor chip together with the first and second amplifying circuits. This fact decreases significantly the number of circuit elements which must be attached outside the integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional dualchannel amplifier;

FIG. 2 is a block diagram of a conventional BTL amplifier;

FIG. 3 is a block diagram of a preferred embodiment of the present invention;

FIG. 4 is a circuit diagram of the preferred embodiment of the present invention; and

FIG. 5 is a circuit diagram of a second preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The preferred embodiment of the present invention is shown in the block diagram of FIG. 3 in which the circuit elements identical to those in FIGS. 1 and 2 are shown by the same reference numbers and characters as in FIGS. 1 and 2. The main part 100 encircled with a dotted line is preferably formed in a semiconductor integrated circuit. The integrated circuit (100) is constructed of the negative feedback power amplifying circuits 200 and 300, a switch control circuit 400 and switches SW1, SW2 and SW3. Moreover, the integrated circuit 100 is equipped with signal input terminals a and c, feedback terminals b and d, output terminals f and g, a BTL feedback terminal i, a switching control terminal j, a power supply terminal h and a grounding terminal e. Moreover, external switches SWa, SWb, and SWc are made coactive. It should be noted that the feedback resistors R.sub.f3, R.sub.f4 and the resistor R.sub.a5 can be arranged to be outside the integrated circuit (100).

Now, if the switch SWa is assumed to be in the position shown in FIG. 3, the switching control terminal j is in its open state so that the switch SW1 is in its ON, or closed state whereas the switches SW2 and SW3 are in their OFF, or open states. Thus, the signal input terminals a and c are respectively connected to the non-inverting inputs of the negative feedback power amplifying circuits 200 and 300. Moreover, the output terminals g and f are respectively connected through the switches SWb and SWc to the coupling capacitors C.sub.3 and C.sub.4. At this time, the input signal V.sub.S1 applied to the signal input terminal a is amplified by the negative feedback power amplifying circuit 300 and an output obtained at the output terminal f is fed to the load resistor R.sub.L2 through the switch SWc and the capacitor C.sub.4. Thus, the integrated circuit (100) functions as a dual-channel amplifier.

On the contrary, when the switching control terminal j is grounded by the switch SWa, the switches SW2 and SW3 are rendered ON whereas the switch SW1 is rendered OFF. At this time, the non-inverting input of the negative feedback power amplifying circuit 200 receives input signals from the signal input terminal a and from the signal input terminal c through the switch SW2. The non-inverting input of the negative feedback power amplifying circuit 300 is disconnected from the signal input terminal c by the OFF state of the switch SW1. It is noted that, if the non-inverting input of the negative feedback power amplifying circuit 300 is not internally biased, the non-inverting input should be grounded to the reference potential by a modification of the switch SW1. Moreover, the output terminal g of the negative feedback power amplifying circuit 200 is connected to the inverting input of the negative feedback power amplifying circuit 300 through the resistor R.sub.a5, the switch SW3, the BTL feedback terminal i, the capacitor C.sub.2 and the feedback terminal d. The output terminals g and f are connected through the switches SWb and SWc to the load resistor R.sub.L3, so that they are disconnected from the coupling capacitors C.sub.3 and C.sub.4. With this circuit arrangement, the input signal V.sub.S1 applied to the signal input terminal a, and the input signal V.sub.S2 applied to the signal input terminal are mixed through the switch SW2, and the mixed signal is transmitted to the non-inverting input of the negative feedback power amplifying circuit 200 to be amplified. The signal amplified by the negative feedback power amplifying circuit 200 is fed to one end of the load resistor R.sub.L3 from the output terminal g. Further, the signal obtained at the output terminal g is applied to the BTL feedback terminal i through the resistor R.sub.a5 and the switch SW3, to be attenuated by the resistors R.sub.a5 and R.sub.f2 to the same amplification as the original input signal V.sub.S1. The attenuated signal is applied to the inverting input of the negative feedback power amplifying circuit 300 through the capacitor C.sub.2 and the feedback terminal d. The amplifying circuit 300 produces an inverted output at the output terminal f and applies it to the other end of the load resistor R.sub.L3. Thus, the integrated circuit (100) functions as a BTL amplifier.

According to the present invention, an amplifier switchable between a dual-channel amplifier and a BTL amplifier is obtained with a simple structure. Only three switches are needed for switching the amplifier function.

Furthermore, the switches SW1, SW2 and SW3 and switch control circuit 400 are easily formed in a semiconductor integrated circuit (100) together with feedback power amplifying circuits 200 and 300. This significantly decreases the number of external circuit elements.

An example of a circuit design using the integrated circuit 100 will be explained hereinafter by referring to FIG. 4. The input signal V.sub.S1 is applied to the non-inverting input of the amplifying circuit 200 by way of the input terminal a, a transistor Q.sub.1, a resistor R.sub.2, a transistor Q.sub.3 and a transistor Q.sub.9. Transistors Q.sub.2, Q.sub.13, Q.sub.14, Q.sub.15, a diode D.sub.2 and their associated resistors R.sub.11, R.sub.15 are used for performing a stable biasing of the circuit. Transistors Q.sub.4, Q.sub.5 and Q.sub.6 and resistors R.sub.4 and R.sub.5 are arranged to mix the input signal V.sub.S2 and to stabilize the biasing current of diode D.sub.1 and the transistor Q.sub.9. The mixture is controlled by a switch transistor Q.sub.7 which corresponds to the switch SW2 in FIG. 3. The stabilization of the biasing current is achieved together with the operation of the circuit constructed of transistors Q.sub.8, Q.sub.10 and Q.sub.16 and resistors R.sub.7, R.sub.8 and R.sub.16 which is controlled by the transistor Q.sub.11 operated in opposite phase to the transistor Q.sub.7.

Similarly, the input signal V.sub.S2 is applied to the non-inverting input of the amplifying circuit 300 by way of a transistor Q.sub.17, a resistor R.sub.18, a transistor Q.sub.20 and a transistor Q.sub.28, when the system is operating as a dual-channel amplifier. At this time, a switch transistor Q.sub.19 which corresponds to the switch SW1 in FIG. 3 is non-conducting to allow the input signal V.sub.S2 to be applied to the amplifying circuit 300. This non-conducting state of transistor Q.sub.19 thus corresponds to the ON position of switch SW2. Transistors Q.sub.18, Q.sub.29 and Q.sub.30 and their associated resistors R.sub.26 and R.sub.27 perform a stable biasing of the circuit. Transistors Q.sub.21, Q.sub.22, Q.sub.23 and Q.sub.24 and resistors R.sub.21, R.sub.22, R.sub.32 and R.sub.33 control the current flowing through a diode D.sub.3. The current flowing through the diode D.sub.3 is also adjusted by the circuit constructed of transistors Q.sub.25, Q.sub.26 and Q.sub.27 and resistors R.sub.24, R.sub.25 and R.sub.34. The switch transistors Q.sub.11 and Q.sub.19 are controlled by a switch transistor Q.sub.12 which corresponds to the switch control circuit 400 of FIG. 3.

Transistors Q.sub.31 and Q.sub.32 and their associated resistors R.sub.28, R.sub.29 and R.sub.a5 operate as the switch SW3 in FIG. 3. When the switch SWa is turned to the BTL side, the transistor Q.sub.32 turns on to apply the output from the amplifying circuit 200 to the inverting input of the amplifying circuit 300 after the output is attenuated by the resistors R.sub.a5 and R.sub.f2. The attenuation factor is adjusted to have the same value as the amplification factor of the amplifying circuit 200.

Next, the operation of the circuit will be described. First of all, the switches SWa, SWb and SWc are assumed to be in their Dual position. The transistors Q.sub.7, Q.sub.12, Q.sub.24 and Q.sub.31 are in their conducting states whereas the transistors Q.sub.11 and Q.sub.19 are in their non-conducting states, so that the transistors Q.sub.4 and Q.sub.6 are rendered non-conducting whereas transistors Q.sub.17 and Q.sub.20 are rendered conducting. The input signal V.sub.S1 is transmitted through the transistors Q.sub.1 and Q.sub.3 to the current mirror circuit consisting of the diode D.sub.1 and the transistor Q.sub.9 and further to the amplifying circuit 200. After the input signal V.sub.S1 is amplified by the amplifying circuit 200, it is fed from the output terminal g to the load R.sub.L1. In a like manner, the input signal V.sub.S2 is transmitted to the current mirror circuit of the diode D.sub.3 and the transistor Q.sub.28 through the transistor Q.sub.17 and the resistor R.sub.18 and further to the amplifying circuit 300. After the input signal V.sub.S2 is amplified by the amplifying circuit 300, it is fed from the output terminal f to the load R.sub.L2. Thus, the integrated circuit 100 acts as a dual-channel amplifier.

When the switches SWa, SWb and SWc are in their BTL positions, however, the switching control terminal c is grounded, so that the transistors Q.sub.7, Q.sub.12, Q.sub.24 and Q.sub.31 are rendered non-conducting whereas the transistors Q.sub.11 and Q.sub.19 are rendered conducting. Therefore, the transistors Q.sub.4, Q.sub.6 and Q.sub.32 are conducting whereas the transistors Q.sub.17 and Q.sub.20 are non-conducting. The input signal V.sub.S1 is transmitted to the diode D.sub.1 in a similar manner to the aforementioned dual-channel operation. On the other hand, the input signal V.sub.S2 is also transmitted to the diode D.sub.1 through the transistors Q.sub.6 and Q.sub.4 so that it is mixed with the input signal V.sub.S1. The mixed signal is amplified by the amplifying circuit 200.

The output from the amplifying circuit 200 is delivered to the load R.sub.L3 through the output terminal g and the switch SWb and also to the inverting input of the amplifying circuit 300 through the resistor R.sub.a5, the transistor Q.sub.32, the BTL feedback terminal i, the capacitor C.sub.2 and the feedback terminal d. The signal to be applied to the amplifying circuit 300 has its voltage attenuated by the resistors R.sub.a5 and R.sub.f2 to a value equal to the signal voltage at the noninverting input of the amplifying circuit 200. The input signal thus transmitted is amplified by the amplifying circuit 300 which generates an inverted output from the output terminal j. As a result, the load R.sub.L3 receives at both terminals the respective output signals having their phases inverted. Thus, the integrated circuit 100 acts as a BTL amplifier. It should be noted that, if the mixing function of the input signal V.sub.S2 with the input signal V.sub.S1 is not desired, the input signal V.sub.S1 may be cut off by arranging another switch between the V.sub.S1 source and the input terminal a.

The circuit arrangement of this embodiment shown in FIG. 4 is designed to avoid switching noise accompanying the switching between the dual-channel amplifier operation and the BTL amplifier operation. This noise is caused by a change in the bias current of the signal path. Therefore, the bias current of the signal path is arranged to be constant in spite of the switching. When the system operates as a dual-channel amplifier, because the switch transistor Q.sub.7 is ON to render the transistor Q.sub.4 OFF, the current from the diode D.sub.1 flows through the transistors Q.sub.3 and Q.sub.8. On the contrary, when the system operates as a BTL amplifier, the switch transistor Q.sub.11 is ON to render the transistor Q.sub.8 OFF, so that the current from the diode D.sub.1 flows through the transistors Q.sub.3 and Q.sub.4. Thus, in spite of the switching, the current from the diode D.sub.1 will always have the same value. In the same manner, the current from the diode D.sub.3 flows through the transistors Q.sub.20 and Q.sub.25 in the dual-channel amplifier operation and through the transistors Q.sub.21 and Q.sub.25 in the BTL amplifier operation. This current is also constant in spite of the switching. Thus, the currents flowing through the diodes D.sub.1 and D.sub.3 are constant in the dual-channel amplifier operation and the BTL amplifier operation, and therefore, the bias potentials at the non-inverting inputs of the amplifying circuits 200 and 300 are also constant in the both amplifier operation. As a result, the switching noise which may occur upon switching is avoided.

This will be explained in more detail in the following. First, in a case where the switch SWa is in its "Dual" position, the current from the diode D.sub.1 flows through the transistors Q.sub.3 and Q.sub.8. Accordingly, the bias potential V.sub.BI1 at the non-inverting input of the amplifying circuit 200 is expressed by the following equations: ##EQU1##

I.sub.D1 =I.sub.CQ3 +I.sub.CQ8 (2); I.sub.CQ3 =(V.sub.BQ3 -V.sub.BEQ3)/R.sub.3 (3); I.sub.CQ8 =(V.sub.BQ8 -V.sub.BEQ8)/R.sub.7 (4); and V.sub.BQ8 =I.sub.CQ10 .times.R.sub.8 +V.sub.BQ16 +V.sub.BEQ16 (5); wherein: I.sub.D1 : current of diode D.sub.1 ; I.sub.CQ3, I.sub.CQ8, I.sub.CQ9 and I.sub.CQ10 : collector currents of transistors Q.sub.3, Q.sub.8, Q.sub.9 and Q.sub.10 ; V.sub.BEQ3, V.sub.BEQ8 and V.sub.BEQ15 : voltages between bases and emitters of transistors Q.sub.3, Q.sub.8 and Q.sub.15 ; and V.sub.BQ3, V.sub.BQ8, V.sub.BQ15 and V.sub.BQ16 : base potentials of transistors Q.sub.3, Q.sub.8, Q.sub.15 and Q.sub.16.

In the other case where the switch SWa is in its "BTL" position, the bias potential V.sub.BI2 at the non-inverting input terminal is expressed by the following equations:

V.sub.BI2 =I.sub.D1 .times.R.sub.15 +V.sub.BEQ15 +V.sub.BQ15 (6); I.sub.D1 =I.sub.CQ3 +I.sub.CQ4 (7); I.sub.CQ4 =(V.sub.BQ4 -V.sub.BEQ4)/R.sub.4 (8); and V.sub.BQ4 =I.sub.CQ5 .times.R.sub.5 +V.sub.BQ6 +V.sub.BEQ6 (9); wherein: I.sub.CQ4 and I.sub.CQ5 : collector currents of transistors Q.sub.4 and Q.sub.5 ; V.sub.BEQ4 : voltage between base and emitter of transistor Q.sub.4 ; and V.sub.BQ4 and V.sub.BQ6 : base potentials of transistors. In the equations (5) and (9), I.sub.CQ5 =I.sub.CQ10 because the transistors Q.sub.5 and Q.sub.10 are of identical shape and, together with the diode D.sub.2, constitute current mirror circuits, and V.sub.BQ16 =V.sub.BQ6 because the transistors Q.sub.6 and Q.sub.16 are of identical shape and because the resistors R.sub.6 and R.sub.16 have equal values. Since the resistors R.sub.5 and R.sub.8 have equal values, V.sub.BQ8 =V.sub.BQ4. In the equations (4) and (8), V.sub.BEQ4 =V.sub.BEQ8 and R.sub.4 =R.sub.7, because the transistors Q.sub.4 and Q.sub.8 are of identical shape and because the resistors R.sub.4 and R.sub.7 are designed to have equal values. Consequently, I.sub.CQ4 =I.sub.CQ8. In the equations (1) and (6), therefore, V.sub.BI1 =V.sub.BI2 so that the bias potentials at the non-inverting input terminal of the amplifying circuit 200 are equal, notwithstanding whether the switch SWa is in the "Dual" or "BTL" position, thus avoiding any fluctuation due to the interchange between those two states. As a result, no switching noise is generated by that interchange.

With respect to the bias potentials at the non-inverting input of the amplifying circuit 300 in the both amplifier operation, they are also constant. The bias potential at the non-inverting input of the amplifying circuit 300 is determined by the base potential V.sub.BQ30 of a transistor Q.sub.30, the base-emitter voltage V.sub.BEQ30 of the transistor Q.sub.30, and the voltage drop (R.sub.27 .times.I.sub.CQ28) of the resistor R.sub.27. Here, since the transistor Q.sub.28 and the diode D.sub.3 constitute a current mirror circuit, the collector current I.sub.CQ28 of the transistor Q.sub.28 becomes equal to the current I.sub.D3 of the diode D.sub.3. Consequently the current I.sub.D3 of the diode D.sub.3 is determined by the respective collector currents I.sub.CQ20, I.sub.CQ21 and I.sub.CQ25 of the transistors Q.sub.20, Q.sub.22 and Q.sub.25. In case the switch SWa is in its Dual position, more specifically, the transistors Q.sub.17 and Q.sub.20 are in their conducting states whereas the transistors Q.sub.21 and Q.sub.23 are in their nonconducting states so that I.sub.D3 =I.sub.CQ20 +I.sub.CQ25. When the switch SWa is in its BTL position, the transistors Q.sub.17 and Q.sub.20 are in their non-conducting states whereas the transistors Q.sub.21 and Q.sub.23 are in their conducting states, so that I.sub.D3 =I.sub.CQ21 +I.sub.CQ25. Similar to the upper part of the embodiment of FIG. 4, the respective collector currents I.sub.CQ20 and I.sub.CQ21 are designed to be equal by employing the identical transistor pairs of transistors Q.sub.17 and Q.sub.23 and transistors Q.sub.20 and Q.sub.21 , and identical resistor pairs of resistors R.sub.6 and R.sub.32, resistors R.sub.18 and R.sub.22 and resistors R.sub.20 and R.sub.21. The transistors Q.sub.20 and Q.sub.21 are alternately rendered conductive. Therefore, the current I.sub.D3 does not fluctuate when the switch SWa is turned. As a result, because the bias potential at the non-inverting input of the amplifying circuit 300 never changes, no switching noise is generated by switching the switch SWa.

FIG. 5 shows a second preferred embodiment of the present invention. The amplifier of this embodiment shown as a monolithic integrated circuit 110, has one amplifying circuit 210, but has two input terminals a and b which are supplied with first and second input signals V.sub.S111 and V.sub.S112, respectively. The amplifying circuit 210 includes non-inverting and inverting inputs, and an output connected to an output terminal f. A first feedback resistor R.sub.f113 is connected between the inverting input and the output of the amplifying circuit 200. The inverting input is connected to a terminal d which is grounded through a capacitor C.sub.111 and a second feedback resistor R.sub.f111. As the input signal V.sub.S111, an audio signal from a tape recoder or a recode player may be supplied to the terminal a, and a voice signal from a microphone may be applied to the terminal b as the second input signal V.sub.S112. A switch SW connected to a terminal c is provided for switching the amplifying operation of the amplifier 110 shown in FIG. 5. When the switch SW is in its "MIX OFF" position, the amplifier 110 receives only the first input signal V.sub.S111, and supplies its amplified signal to a load R.sub.L through the output terminal f and a capacitor C.sub.112. When the switch SW is in its "MIX ON" position, the amplifier 110 receives the first and second input signals V.sub.S111 and V.sub.S112, mixes them, and supplies an amplified signal of the mixed signal to the load R.sub.L. Thus, the amplifier shown in FIG. 5 generates two types of output signal by the switching between "MIX OFF" and "MIX ON" positions in the switch SW.

At this time, if a bias potential at the non-inverting input of the amplifying circuit 210 is changed by the switching operation of the switch SW, the switching noise is supplied to the load R.sub.L. However, the amplifier 110 shown in FIG. 5 has such a circuit arrangement that the switching noise can be avoided.

In FIG. 5, a bias current is set by means of a transistor Q.sub.123 and resistors R.sub.121, R.sub.122 and R.sub.123, and supplied to the respective circuit portions through a current mirror circuit composed of a diode D.sub.112 and transistors Q.sub.112, Q.sub.115 and Q.sub.120. An emitter follower circuit constructed of a transistor Q.sub.111 and a resistor R.sub.112 and a constant current circuit constructed of a transistor Q.sub.113 and a resistor R.sub.113 are biased by the transistor Q.sub.112. Likewise, an emitter follower circuit constructed of a transistor Q.sub.116 and a resistor R.sub.115, and a constant current circuit constructed of a transistor Q.sub.114 and a resistor R.sub.114 are biased by the transistor Q.sub.115. Moreover, constant current circuits constructed of a transistor Q.sub.126 and a resistor R.sub.118, and a transistor Q.sub.118 and a resistor R.sub.117 are biased by the transistor Q.sub.120.

A switching circuit is constructed of resistors R.sub.119 and R.sub.120 and transistors Q.sub.117, Q.sub.121 and Q.sub.122. When the switch SW is in its "MIX OFF" position, the transistors Q.sub.117 and Q.sub.122 are biased by the resistor R.sub.120 into conducting states whereas the transistor Q.sub.121 is biased into its inconducting state. As a result, the collector of the transistor Q.sub.115 is grounded to the earth to render the transistors Q.sub.114 and Q.sub.116 inconducting but the transistors Q.sub.118 and the transistor Q.sub.126 conducting. When the switch SW is in its "MIX ON" position, on the contrary, the transistors Q.sub.117 and Q.sub.122 have their bases grounded to the earth and rendered inconducting, whereas the transistor Q.sub.121 is biased by the resistor R.sub.119 into its conducting state. As a result, the transistors Q.sub.114 and Q.sub.116 are rendered conducting whereas the transistors Q.sub.115 and Q.sub.126 are rendered inconducting with a result that the collector of the transistor Q.sub.10 is grounded to the earth.

A transmission circuit is constructed of a current mirror circuit having a diode D.sub.111 and a transistor Q.sub.119. The diode D.sub.111 has its cathode connected to the collectors of the transistors Q.sub.113, Q.sub.114 and Q.sub.118. The transistor Q.sub.119 has its collector connected to both a resistor R.sub.125 and the non-inverting input of the amplifying circuit 210. Moreover, the transistor Q.sub.119 supplies a bias current to the resistor R.sub.125 and a transistor Q.sub.125 so that the bias potential at the non-inverting input of the amplifying circuit 200 is set by the transistors Q.sub.124 and Q.sub.125 and the resistors R.sub.122, R.sub.123, R.sub.124 and R.sub.125.

The operations of the circuit having the construction thus far described will be described in the following.

First of all, when the switch SW connected to the switching terminal c is in its "MIX OFF" position, the signal of the first signal source V.sub.S111, which is applied to the input terminal a, is transmitted through the transistor Q.sub.111, the resistor R.sub.112 and the transistor Q.sub.113 to the diode D.sub.111. The signal of the second signal source V.sub.S112 which is applied to the input terminal b, is not transmitted to the diode D.sub.111 because the transistors Q.sub.116 and Q.sub.114 are in their inconducting states by the conducting state of the transistor Q.sub.117. As a result, only the first signal is further transmitted by the current mirror circuit, which is constructed of the diode D.sub.111 and the transistor Q.sub.119, to the non-inverting input of the amplifying circuit 200.

When the switch SW is in its "MIX ON" position, on the contrary, the signal of the first signal source V.sub.S111 is transmitted to the diode D.sub.1 in a similar manner to the aforementioned case. The signal of the second signal source V.sub.S112 is also transmitted to the diode D.sub.1 because the transistors Q.sub.116 and Q.sub.114 are in their conducting states. As a result, the first and second signals V.sub.S111 and V.sub.S112 transmitted to the diode D.sub.111 are mixed, and the mixed signal is transmitted by the current mirror circuit constructed of the diode D.sub.111 and the transistor Q.sub.119 to the amplifying circuit 200.

The bias potentials at the non-inverting input of the amplifying circuit 200 in the two states, i.e., in the MIX OFF and MIX ON states will be described in the following.

The bias potential at the non-inverting input of the amplifying circuit 200 is determined by the base potential V.sub.BQ125 of the transistor Q.sub.125, the base-emitter voltage V.sub.BEQ125 of the transistor Q.sub.125, and the voltage drop (R.sub.125 .times.I.sub.CQ119) across the resistor R.sub.125. The current I.sub.CQ119 represents the collector current of the transistor Q.sub.119. Since the transistor Q.sub.119 and the diode D.sub.111 constitute a current mirror circuit, the current I.sub.CQ119 is equal to the current I.sub.D111 flowing through the diode D.sub.111. The current I.sub.D111 is determined by the collector currents I.sub.CQ113, I.sub.CQ114 and I.sub.CQ118 of the transistors Q.sub.113, Q.sub.114 and Q.sub.118. In the case where the switch SW is in its "MIX OFF" position, the transistors Q.sub.113 and Q.sub.118 is in the conducting state, whereas the transistor Q.sub.114 is in nonconducting state. Therefore, the current I.sub.D111 is equal to the sum of the collector currents I.sub.CQ113 and I.sub.CQ118 (I.sub.D111 =I.sub.CQ113 +I.sub.CQ118). When the switch SW is in "MIX ON" position, the transistors Q.sub.113 and Q.sub.114 is in the conducting state, whereas the transistor Q.sub.118 is in the non-conducting state. Accordingly, the current I.sub.D111 is equal to the sum of the collector currents I.sub.CQ113 and I.sub.CQ114 (I.sub.D111 =I.sub.CQ113 +I.sub.CQ114). The collector currents I.sub.CQ224 and I.sub.CQ118 are designed to be equal by employing the identical transistor pairs of transistors Q.sub.114 and Q.sub.118 and transistors Q.sub.116 and Q.sub.126, and identical resistor pairs of resistors R.sub.114 and R.sub.117, resistors R.sub.115 and R.sub.118 and resistors R.sub.116 and R.sub.126. Consequently, the current I.sub.D111 does not fluctuate when the switch SW is turned. Therefore, the bias potential at the non-inverting input of the amplifying circuit 200 does not change, so that no switching noise is generated.

As has been described hereinbefore, according to the present invention, it is possible to provide a power amplifier which can easily switch its function to generate two types of an output signal. The amplifier is also advantageous in that it is suitable for formation in a semiconductor integrated circuit and that there is no switching noise during its switchover between functions.

Claims

1. An amplifier comprising:

first and second input terminals;

first and second output terminals;

a first amplifying circuit having a non-inverting input and an output;

first means for coupling said first input terminal to said non-inverting input of said first amplifying circuit;

second means for coupling the output of said first amplifying circuit to said first output terminal;

a second amplifying circuit having a non-inverting input, an inverting input and an output;

first switch-means for selectively coupling said second input terminal to either one of said first means and said non-inverting input of said second amplifying circuit;

third means for coupling the output of said second amplifying circuit to said second output terminal;

second switch means for selectively connecting said second means to said inverting input of said second amplifying circuit;

a switch controlling circuit controlling said first and second switch means between a first state in which said second input terminal and said second means are coupled respectively to said first means and said inverting input of said second amplifying circuit and a second state in which said first switch means couples said second input terminal to said non-inverting input of said second amplifying circuit and said second switch means disconnects said second means from said inverting input of said second amplifying circuit;

first and second loads;

a third load having first and second ends; and

third switch means for selectively connecting said first output terminal and said second output terminal to said first load and said second load, respectively, or to said first and second ends of said third load, respectively.

2. An amplifier as claimed in claim 1, wherein said first switch means comprises a first switch inserted between said second input terminal and said non-inverting input of said second amplifying circuit and a second switch inserted between said second input terminal and said first means.

3. An amplifier as claimed in claim 1, wherein said second siwtch means includes an attenuator for applying the signal at said second means to said inverting input of said second amplifying circuit after attenuating its signal level.

4. An amplifier as claimed in claim 2, wherein said second siwtch means includes an attenuator for applying the signal at said second means to said inverting input of said second amplifying circuit after attenuating its signal level.

5. An amplifier comprising a first input terminal; a second input terminal; a first feedback terminal; a second feedback terminal; feedback coupling means for coupling said second feedback terminal to said first feedback terminal; a first output terminal; a second output terminal; a switch control terminal; a first amplifying circuit having a non-inverting input and an output; first means for coupling said first input terminal to said non-inverting input of said first amplifying circuit; second means for coupling said output of said first amplifying circuit to said first output terminal; a second amplifying circuit having a non-inverting input, an inverting input and an output; first switch means for selectively coupling said second input terminal to either one of said first means or said non-inverting input of said second amplifying circuit; third means for coupling said first feedback terminal to said inverting input of said second amplifying circuit; fourth means for coupling the output of said second amplifying circuit to said second output terminal; second switch means for selectively coupling said second means to said second feedback terminal; a switch controlling circuit for controlling said first and second switch means between a first state in which said second input terminal and said second means couple respectively to said first means and said second feedback terminal and a second state in which said second input terminal is coupled to said non-inverting input of said second amplifying circuit while said second means is coupled to said second feedback terminal; and fifth means for coupling said switch controlling circuit to said switch control terminal.

6. An amplifier as claimed in claim 5, wherein said first switch means comprises a first switch inserted between said second input terminal and said non-inverting input of said second amplifying circuit and a second switch inserted between said second input terminal and said first means.

7. An amplifier as claimed in claim 5, wherein said second switch means includes a resistor for attenuating the signal level at said second means and for providing said attenuated signal to said second feedback terminal.

8. An amplifier as claimed in claim 6, wherein said second siwtch means includes a resistor for attenuating the signal level at said second means and for providing said attenuated signal to said second feedback terminal.

9. An amplifier as claimed in claim 7, said second switch means further comprising an additional resistor connected to said second feedback terminal, said amplifier further comprising a first input source coupled to said first input terminal; a second input source coupled to said second input terminal; feedback means comprising a capacitor connected between said first and second feedback terminals; third switch means connected to said switch control terminal for controlling said switch controlling circuit; a first load; a second load; a third load having first and second ends; and fourth switch means for alternatively connecting said first and second output terminals to said first and second loads, respectively, or to said first and second ends of said third load.

10. An amplifier as claimed in claim 9, further comprises fifth switch means inserted between said second input terminal and said second input signal source for controlling the connection therebetween.

11. An amplifier as claimed in claim 8, said feedback means further comprising a capacitor connected between said first and second feedback terminals, said second switch means further comprising an additional resistor connected to said feedback terminal, said amplifier further comprising a first input source coupled to said first input terminal, a second input source coupled to said second input terminal, third switch means connected to said switch control terminal for controlling said switch controlling circuit, a first load, a second load, a third load having a first end and a second end, and fourth switch means for alternatively connecting said first and second output terminals to said first and second loads, respectively, or to said first and second ends of said third loads.

12. An amplifier as claimed in claim 11, further comprising fifth switch means inserted between said second input terminal and said second input signal source for controlling the connection therebetween.

13. An amplifier device having first and second inputs, first and second amplifying circuits each having inverting and non-inverting inputs and an output, means for coupling said inverting input of said first amplifying circuit to a reference, and means for coupling said first input to said non-inverting input of said first amplifying circuit, said amplifier device further comprising;

first switch means switchable between a first state in which it couples said second input to said non-inverting input of said second amplifying circuit and a second state in which it disconnects said second input from said non-inverting input of said second amplifying circuit;

second switch means switchable between a second state in which it couples said output of said first amplifying circuit to said inverting input of said second amplifying circuit and a first state in which it disconnects said output of said first amplifying circuit from said inverting input of said second amplifying circuit; and

switch control means for controlling said first and second switch means to switch said amplifier device between a dual-channel state in which both said first and second siwtch means are in their first states and a single channel state in which both said first and second switch means are in their second states.

14. An amplifier device as claimed in claim 13, further comprising third switch means switchable between a second state in which it connects said second input to said non-inverting input of said first amplifying circuit and a first state in which it disconnects said second input from said non-inverting input of said first amplifying circuit, said third switch means being controlled by said switch control means to switch to its first state when said first and second switch means are switched to their first states and to switch to its second state when said first and second switch means are switched to their second states.

15. An amplifier device as claimed in claim 13, further comprising a load having first and second ends, and fourth switch means switchable together with said first and second siwtch means between a second state in which it connects said outputs of said first and second amplifying circuits to said first and second ends, respectively, and a second state in which it does not connect said amplifying circuit outputs to said first and second ends.

16. An amplifier device as claimed in claim 14, further comprising a load having first and second ends, and fourth switch means switchable together with said first and second switch means between a second state in which it connects said outputs of said first and second amplifying circuits to said first and second ends, respectively, and a second state in which it does not connect said amplifying circuit outputs to said first and second ends.

17. An amplifier device as claimed in claim 14, further comprising first and second loads and fourth switch means switchable together with said first and second switch means between a first state in which it connects said outputs of said first and second amplifying circuits to said first and second loads, respectively, and a second state in which it does not connect said amplifying circuit outputs to said first and second loads.

18. An amplifier device as claimed in claim 17, further comprising a third load having first and second ends, said fourth switch means connecting said outputs of said first and second amplifying circuits to said first and second ends, respectively, in said second state of said fourth switch means.

19. An amplifier device as claimed in claim 13, wherein said second switch means includes at least one transistor (Q.sub.20) receiving an input and providing a corresponding output, means (e.g. Q.sub.17) for providing a second input signal from said second input to said at least one transistor, and means (Q.sub.19) controlled by said switch control means for selectively enabling and disabling said at least one transistor.

20. An amplifier device as claimed in claim 13, wherein said means for coupling said first input to said non-inverting input of said first amplifying circuit comprises at least one transistor (Q.sub.3) having an output terminal (e.g. collector) and means (e.g. Q.sub.1) for applying a first input signal to said at least one transistor, and wherein said third switch means comprises at least a second transistor (Q.sub.4) having an output (e.g. collector) connected to said output of said at least one transistor, means (e.g. Q.sub.6) for applying a second input signal to said second transistor and means (Q.sub.7) controlled by said switch control means for selectively enabling and disabling said second transistor.

21. An amplifier device as claimed in claim 20, wherein said second switch means includes at least a third transistor receiving an input and providing a corresponding output, means for providing a second input signal from said second input to said third transistor and means controlled by said switch control means for selectively enabling and disabling said third transistor.

22. An amplifier device as claimed in claim 21, wherein said second switch means further comprises a fourth transistor receiving an input and providing a corresponding output and having its output connected in common to said output of said third transistor, said amplifier device further comprising bias means (e.g. Q.sub.2, Q.sub.5, Q.sub.18, Q.sub.22) for providing substantially equal bias currents to each of said first through fourth transistors.

23. An amplifier device as claimed in claim 22, further comprising a fifth transistor (Q.sub.8) coupled in parallel with said second transistor, a sixth transistor (Q.sub.25) coupled in parallel with said fourth transistor, said fifth and sixth transistors receiving said substantially equal bias current from said bias means, and means (e.g. Q.sub.11, Q.sub.12) controlled by said switch control means for selectively enabling and disabling said fifth transistor during disabling and enabling, respectively, of said second transistor.