Claims
- 1. A negative voltage regulator for regulating a negative voltage, comprising:
- a current source,
- a first FET having a drain coupled to said current source, a source for connection to ground, and a gate;
- a second FET having a drain coupled to said power supply, a gate coupled to the drain of said first FET, and a source;
- a third FET having a drain coupled to the source of said second FET and to the gate of said first FET, a gate and a source connected together and to said negative voltage, whereby a regulated negative voltage is provided at the drain of said third FET.
- 2. The negative voltage regulator of claim 1 further comprising diode means connected between the source of said second FET and the drain of said third FET.
- 3. A negative voltage regulator for regulating a negative voltage for biasing a depletion-mode FET, comprising:
- a current source,
- a first FET having a drain coupled to said current source, a source coupled to ground, and a gate,
- a second FET having a drain coupled to a power supply, a gate coupled to the drain of said first FET, and a source,
- a third FET having a drain coupled to the source of said second FET, a gate and a source connected together and to said negative voltage, the drain of said third FET being resistively coupled to the gate of said depletion-mode FET, and the gate of said first FET being resistively coupled to the gate of said depletion-mode FET, whereby the effect of increased temperature on the performance of said regulator is reduced.
- 4. The regulator of claim 3 wherein said current source comprises a resistor coupled between said power supply and the drain of said first FET.
- 5. The negative voltage regulator of claim 3 wherein said first FET and said depletion-mode FET have substantially the same pinch-off characteristics, and the gate-width of said first FET is such that said negative voltage regulator provides a desired regulated negative voltage to bias said depletion-mode FET.
- 6. The negative voltage regulator of claim 3 wherein said current source comprises a fourth FET having a drain coupled to said power supply, a gate and a source connected together and to the drain of said first FET.
- 7. The negative voltage regulator of claim 6 wherein said depletion-mode FET and said first and fourth FETs have substantially the same pinch-off characteristics, and the gate-width of said first FET is a predetermined factor times the gate-width of said fourth FET, whereby said depletion mode FET is biased at substantially its characteristic zero-bias saturation current divided by said predetermined factor.
- 8. The negative voltage regulator of claim 7 wherein the predetermined factor is 2, whereby said depletion-mode FET is biased at substantially one half of its characteristic zero-bias saturation current for class A operation.
- 9. The negative voltage regulator of claim 7 wherein the predetermined factor is 4, whereby said depletion-mode FET in said amplifying stage is biased at substantially one quarter of its characteristic zero-bias saturation current for class AB operation.
- 10. The negative voltage regulator of claim 7 wherein the predetermined factor is such that said depletion-mode FET is biased around or below pinch-off for class B operation.
- 11. The negative voltage generator of claim 3 further comprising diode means connected between the source of said second FET and the drain of said third FET.
Parent Case Info
This is a division of application Ser. No. 08/764,350 filed Dec. 12, 1996. This application claim the benefit of U.S. Provisional Appln. No. 60/008,678 Dec. 15, 1995.
US Referenced Citations (34)
Divisions (1)
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Number |
Date |
Country |
Parent |
764350 |
Dec 1996 |
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