Patent Application
20250105789
A technology described herein relates to differential amplifiers, and to equalizer circuits utilizing differential amplifiers.
Input signals for integrated circuits can have very high frequencies, on the order of gigahertz in some cases. Communication channels which deliver the input signals can suffer channel loss, particularly at high frequencies. Accordingly, receivers in these environments often include high-speed input buffers having equalizer circuits to compensate for channel loss, and to provide for uniform gain across wide input frequencies. One type of equalizer has been referred to as a continuous time linear equalizer CLTE, which can be based on a differential amplifier with source degeneration. Source degeneration can be tuned to improve the AC gain at the operating frequencies for the equalizers, including at frequencies on the order of gigahertz.
In integrated circuit manufacturing, so-called process corner variations can impact the operating characteristics of circuits on the chips. Thus, a problem encountered in the manufacturing of equalizer circuits used in the receivers on integrated circuits, and other differential amplifier base circuits, relates to maintaining operating characteristics across process corners.
It is desirable to provide improved circuit structures that can be more stable across process corners for high-frequency equalizers and differential amplifiers.
An amplifier including an input pair of transistors with a source-side resistor circuit is described. The source-side resistor circuit includes a transistor biased in a triode region. The source-side resistor circuit in combination with a capacitance, causes source degeneration in the amplifier with an improved gain at a target frequency. The resistance of the source-side resistor circuit and the gain of the transistors in the differential amplifier can track across process corners.
An amplifier circuit is described comprising an input pair of transistors, the transistors in the pair having respective source, drain, gate and bulk terminals. A source side resistor circuit is connected to the sources of the transistors in the input pair. The source side resistor circuit includes a first MOS transistor having a first channel terminal connected to the source of a first transistor in the differential pair, and a second channel terminal connected to the bulk terminal, and a second MOS transistor having a first channel terminal connected to the source of a second transistor in the differential pair, and a second channel terminal connected to the bulk terminal. A bias circuit to bias the first MOS transistor and the second MOS transistor in a triode region is described.
An equalizer circuit is described with good uniformity in compensation across a target frequency range, using an input pair with a source-side resistor circuit which includes a transistor biased in a triode region.
An input buffer for a high speed data channel is described using an equalizer circuit like that described herein.
Other aspects and advantages of the present technology can be seen on review of the drawings, the detailed description and the claims, which follow.
A detailed description of embodiments of the present invention is provided with reference to the
The channel circuit 30 can have a low pass filter response, causing channel loss at high frequency as represented by the graph 35 showing signal magnitude in decibels dB versus frequency. Thus, in a target frequency range between f1 and f2, the signal gain can fall in accordance with a low pass filter response of the channel. The equalizer circuit 40 can compensate for low pass filter response of the channel by providing gain in the target frequency range as represented by the graph 45. Characteristics of the signal at the output of the equalizer circuit 40 can be seen in the graph 55, resulting from a combination of the low pass filter characteristic of the channel, with the gain characteristics of the equalizer. The signal can have uniform gain across the target frequency range between frequencies f1 and f2.
In systems as described herein, the equalizer circuit 40 includes an input pair of transistors having a source-side resistor circuit that includes a transistor biased on the triode region (MOS RS). The input pair can be configured as a differential amplifier. The differential amplifier is configured to amplify the difference between two input signals while rejecting the part of the signal common to both inputs. The source-side resistor circuit provides source degeneration. The gain of the transistors in the input pair can track the resistance of the resistor circuit across process corners, sometimes referred to as fast-fast ff, typical-typical tt and slow-slow ss corners.
The gates of the transistors MR1 and MR2 of the resistor circuit are connected to a bias voltage SEN. As illustrated in the circuit, the bias voltage SEN can be provided by a switch 150 response to a control signal VEN to provide a first state SwB to enable the differential amplifier and to set transistors MR1 and MR2 in a triode operating region during operation, and a second state Sw to turn off transistors MR1 and MR2. An example of a bias circuit to provide the voltages SwB and Sw is described with reference to
A capacitor circuit including at least one capacitor connected to the source of at least one of the transistors M7 and M8 at nodes 117 and 118, and in this example including source capacitor 121 and source capacitor 122 connected to the sources of the transistors M7 and M8. The source capacitor 121 is connected between node 117 and a reference node such as VSS or ground. The source capacitor 122 is connected between node 118 and the reference node. The capacitance (2CS) of the capacitor circuit (source capacitors 121 and 122 in this example) is tuned along with the resistor circuit to set the frequency response of the differential amplifier.
A drain resistor having resistance RD is connected between the drain of transistor M7 at node 127 and the reference node. Also, a drain resistor having a resistance RD is connected between the drain of transistor M8 at node 128 and the reference node. In the circuit, parasitic capacitance CP is illustrated across the drain resistors.
Input voltages DQ and DQB are applied at the gates of the input pair of transistors M7 and M8.
Output voltages VOUTN and VOUTP of the differential amplifier are generated at nodes 127 and 128, respectively.
A circuit having an input pair with source degeneration, like that illustrated in
It is desirable for the circuit to have a peaking ratio which remains constant across operating temperatures and process corners. The peaking ratio is defined as the ratio between the ideal peak gain and the DC gain of the circuit, and is a function of the effective gain gm of the input pair and the effective resistance RS of the source side resistor circuit. For example, the peaking gain can be expressed by the following:
In the circuit illustrated, in operation the gate to source voltage of M7 or M8 is about equal to the gate to source voltage of MR1 and MR2. As a result, RS varies over temperature and process corners with gm in a manner that tends to maintain a constant peaking ratio. Accordingly, the input pair of transistors has an effective gain gm, and the resistor circuit has an effective resistance RS, and the effective resistance RS of the resistor circuit can vary with the gm over an operating range of temperature and process corners in a way tending to maintain a constant peaking ratio across the operating range in some embodiments.
Circuit 301 includes a pair of P-channel transistors M5 and M6, having source terminals coupled together at node 220. The channel bodies or bulk terminals of transistors M5 and M6 are also connected to node 220. Transistor M2 is connected to provide current at node 220 configured in a current mirror relationship with transistors M1 and M3 with its gate connected to node 205, and its source connected to an external supply voltage EXVDD. The drain terminals of transistors M5 and M6 are connected to nodes 211 and 212, respectively. A drain-side resistor having a resistance R is connected between node 211 and reference node 227. Also a drain-side resistor having a resistance R is connected between node 212 and reference node 227. Differential output voltages VP1 and VN1 are provided at nodes 211 and 212, respectively, which are in turn coupled to the gates of transistors M7 and M8, as mentioned above.
A single ended input signal DQ is applied to the gate of transistor M6. A reference voltage VREFQ is applied to the gate of transistor M5.
Circuit 302 includes P-channel transistor M4 in series with a current mirror transistor M1, configured in a current mirror relationship with transistors M2 and M3 with its gate connected to node 205, and its source connected to an external supply voltage EXVDD. A voltage VPBAIS is applied at node 205 from a bias circuit or other source of a voltage to implement the current mirror. A drain side resistor having resistance R is connected between the drain of transistor M4 at node 210 and the reference node 227. Transistor M4 can have the same dimensions as the differential pair M5 and M6. This circuit produces a node voltage VPS at node 210 which tracks the common mode voltage of the signals VP1 and VN1 at nodes 211 and 212. The voltage VPS can be used in a bias circuit like that shown in
The gates of transistors M9 and M10 are connected to nodes 406 and 405, respectively. The gate of transistor M11 is connected to a supply voltage VCCQ, while the gate of transistor M12 is connected to the reference voltage VSS. The supply voltage VCCQ can be a regulated supply voltage generated on-chip.
The circuit of
When SwB is applied to the gates of the transistors MR1 and MR2 at node 115, VL is Vbulk−VDS of MR1 and VR is Vbulk−VDS of MR2. However, the VDS values of MR1 and MR2 are small. So, VL and VR will be close to Vbulk.
In this circuit, when node 115 is set to SwB, the gate-to-source voltage VGS of the transistors MR1 and MR2 in the resistor circuit is VPS−Vbulk. VPS should be lower than Vbulk by an amount to set transistors MR1 and MR2 in the triode region.
Using an equalizer circuit as described herein, the peaking ratio can be maintained relatively constant over the target frequency range, across process corners. In a simulation for comparison of a circuit replacing the MOS transistors MR1 and MR2 of
The gates of the transistors MR1 and MR2 of the resistor circuit are connected to a first bias voltage SEN1. The bias voltage SEN1 can be provided by a switch 601 response to a first control signal VEN1 to provide a first state voltage SwB to the differential amplifier and to the transistors MR1 and MR2, biasing them in a triode operating region during operation, and a second state voltage Sw to transistors MR1 and MR2, turning them off.
The transistors MR3 and MR4 can have different sizes than transistors MR1 and MR2. In this example the transistors MR3 and MR4 can be larger transistors such that when operated the resistance provided is very low. This can maintain operation of the circuit when tracking is not used.
The gates of the transistors MR3 and MR4 of the resistor circuit are connected to a second bias voltage SEN2. The second bias voltage SEN2 can be provided by a switch 602 response to a control signal VEN2 to provide a first state S2wB to set transistors MR3 and MR4 in a triode operating region during operation, and a second state S2w to turn off the transistors MR3 and MR4.
An example of a bias circuit to provide the voltages S1wB and S1w is described with reference to
The gates of the transistors MR1 and MR2 of the resistor circuit are connected to a first bias voltage SEN1, provided for example by a selector 701 responsive to an enable signal VEN1. As illustrated in the circuit, the first bias voltage has a first state S1wB to enable the differential amplifier and to set transistors MR1 and MR2 in a triode operating region during operation, and a second state S1w to turn off the transistors MR1 and MR2.
The transistors MR3 and MR4 can have different sizes than transistors MR1 and MR2, and thereby cause different effects in the circuit. In this example the transistors MR3 and MR4 can be larger transistors such that when operated the resistance provided is very low. This can maintain operation of the circuit when tracking is not used.
The gates of the transistors MR3 and MR4 of the resistor circuit are connected to a second bias voltage SEN2, provided for example by a selector 702 responsive to an enable signal VEN2. As illustrated in the circuit, the second bias voltage has a first state S2wB to set transistors MR3 and MR4 in a triode operating region during operation, and a second state S2w to turn off the transistors MR3 and MR4.
The transistors MR5 and MR6 can have different sizes similar to transistors MR1 and MR2, and thereby cause slightly different effects in the circuit. In this example the transistors MR5 and MR6 can be sized in a manner that provides for tuning the tracking characteristic by changing between the first and third pairs.
The gates of the transistors MR5 and MR6 of the resistor circuit are connected to a third bias voltage SEN3, provided for example by a selector 703 responsive to an enable signal VEN3. The selection of the pair of transistors to be operable in the circuit can be accomplished using independent enable signals to the bias circuits, like that described with reference to
In general, embodiments of the technology can include source side resistor circuits comprising a plurality of pairs of transistors, selected for different effects on the characteristics of the output signals to be produced.
The embodiments described herein are based on amplifiers with an input pair using P-channel transistors (PMOS). In alternative systems, N-channel transistors (NMOS) could be utilized, changing the current mirror transistors and the transistors in the source-side resistor circuit to NMOS transistors. Also, the source resistor, drain resistor and current mirror positions are inverted. P-channel embodiments are preferred in lower voltage systems.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
