This invention relates to envelope detectors and demodulator circuits, and more particularly to an envelope detector circuit for an Amplitude-Modulation (AM) or Amplitude-Shift-Keying (ASK) signal.
Many types of electronic systems include a receiver that must process a received signal. The signal may be applied to a carrier wave, such as by adjusting or modulating the amplitude of the carrier wave. Amplitude-Modulation (AM) and Amplitude-Shift-Keying (ASK) are two methods to modulate an amplitude to carry a signal.
A receiver may use an envelope detector to extract the signal from the carrier wave. The envelope detector outputs a signal that generally follows the peaks in the carrier wave over time. The envelope signal may then undergo further processing, such as by a demodulator or a digital-signal processor (DSP).
An envelope detector ideally generates an upper envelope signal 104 from the positive peaks of carrier wave 102, and lower envelope signal 106 from the negative peaks or troughs of carrier wave 102. However, circuit losses in a real envelope detector may produce a voltage drop or loss, so that upper envelope real output 108 is lower in voltage than upper envelope signal 104. Similarly, lower envelope real output 110 has a smaller absolute voltage than lower envelope signal 106.
These circuit loses may be caused by voltage drops from a diode rectifier, a filter such as an R-C filter that imposes an R-C time constant limit, and various impedances that are sensitive to frequency. For example, a simple envelope detector having a diode rectifier followed by a filter has a maximum frequency that is limited by the filter's R-C time constant. Ripple on a power or ground line may disrupt the stability of some envelope detectors, such as those based on transistor inverters or drivers. Transistors having a grounded source or drain may inject power-line or ground ripple into the detected signal. Schmidt-trigger stages may not operate over a wide range of input voltages or signals with large swings. Active circuits such as opamps, equalizers, differentiators, and Phase-Locked Loops (PLL's) increase circuit complexity and may introduce secondary problems such as harmonics and loop stability.
Prior-art envelope detectors are often sensitive to frequency. As the frequency of carrier wave 102 or of the data being carried increases, the impedance losses and voltage drop can increase significantly. As frequency rises, the voltage drop can approach the total amplitude of carrier wave 102, creating an upper frequency limit to the envelope detector and the receiver. Thus very high data bit rates may not be allowed. Very complex circuits to tune the phases of recovered clocks may be needed, but these complex circuits may impose their own limits to operating frequency due to their complexity. Jitter and phase errors may increase and cause problems. Getting the clock phase to exactly match the peak in carrier wave 102 may be quite difficult.
What is desired is an envelope detector that can operate at very high frequencies and data rates. An envelope detector circuit that does not have many active components such as amplifier transistors with powered or grounded sources or drains is desirable to reduce ripple problems. An envelope detector with time-multiplexed or parallel paths is desirable to increase data rates.
The present invention relates to an improvement in envelope detectors. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
A first detection channel samples RF_IN through sample switch 20, which is clocked by CK1. Diode 22 allows positive current to flow to charge sampling capacitor 24 during the positive peaks in carrier wave 102 on RF_IN. The sampled charge on charge sampling capacitor 24 passes through hold switch 28 when CK2 is active to charge summing output capacitor 94. When CK3 is active, reset switch 26 discharges sampling capacitor 24, causing node NQ1 to fall to ground.
A second detection channel samples RF_IN through sample switch 30, which is clocked by CK1B. Diode 32 allows positive current to flow to charge sampling capacitor 34 during the positive peaks in carrier wave 102 on RF_IN. The sampled charge on charge sampling capacitor 34 passes through hold switch 38 when CK4 is active to charge summing output capacitor 94 and node NQ3. When CK5 is active, reset switch 36 discharges sampling capacitor 34, causing node NQ2 to fall to ground.
The AM or ASK modulated signal on RF_IN is blocked from the second channel by sample switch 30 being open, but passes through sample switch 20 to charge sampling capacitor 24 and node NQ1 in the first channel. Reset switch 26 and hold switch 28 are open in the first channel.
The prior-sampled signal on sampling capacitor 34 and node NQ2 in the second channel charges or discharges summing output capacitor 94 through hold switch 38. Thus the output voltage on output node NQ3 is adjusted somewhat.
In
In the second channel, sampling capacitor 34 is discharged by reset switch 36 being on. This resetting prepares the second channel to sample the RF_IN input in the future third and fourth phases. Node NQ3 and summing output capacitor 94 are isolated by hold switches 28, 38 being open. During the second phase, summing output capacitor 94 holds the output voltage for use by downstream logic, such as a DSP or demodulator.
In
The AM or ASK modulated signal on RF_IN is blocked from the first channel by sample switch 20 being open, but passes through sample switch 30 to charge sampling capacitor 34 and node NQ2 in the second channel. Reset switch 36 and hold switch 38 are open in the second channel.
The prior-sampled signal on sampling capacitor 24 and node NQ1 in the first channel charges or discharges summing output capacitor 94 through hold switch 28. Thus the output voltage on output node NQ3 is adjusted somewhat, this time by the first channel.
In
In the first channel, sampling capacitor 24 is discharged by reset switch 26 being on. This resetting prepares the first channel to sample the RF_IN input in a later first and second phase. Node NQ3 and summing output capacitor 94 are isolated by hold switches 28, 38 being open. During the fourth phase, summing output capacitor 94 holds the output voltage for use by downstream logic, such as a DSP or demodulator.
The four phases highlighted in
The first channel samples RF_IN during the first cycle of RF_IN, when the sampled voltage is 1.00 volt, and during the third full cycle of RF_IN, when the sampled voltage is 1.19 volt. During the first cycle of RF_IN, the internal node NQ1 in the first channel reaches 0.58 volt rather than the full 1.00 volt of RF_IN due to losses in the channel, such as through diode 22 and by charge sharing with sampling capacitor 24 and with parasitic capacitances in the first channel.
During the third full cycle of RF_IN, internal node NQ1 rises to 0.72 volt when RF_IN is 1.19 volt. CK3 resets NQ1 to ground through reset switch 26 during the fourth phase. During the third phase, CK2 is high and hold switch 28 connects NQ1 to output NQ3. The voltage on output NQ3 rises or falls as charge is shared between sampling capacitor 24 and summing output capacitor 94. In this ideal example, NQ3 matches NQ1, but in a real circuit some voltage losses could occur. Thus NQ3 changes to 0.58 volt during the third phase.
The second channel samples RF_IN during the second cycle of RF_IN, when the sampled voltage is 1.06 volt, and during the fourth full cycle of RF_IN, when the sampled voltage is 1.04 volt. During the second cycle of RF_IN, the internal node NQ2 in the second channel reaches 0.63 volt rather than the full 1.06 volt of RF_IN due to losses in the channel, such as through diode 32 and by charge sharing with sampling capacitor 34 and with parasitic capacitances in the second channel.
During the fourth full cycle of RF_IN, internal node NQ2 rises to 0.62 volt when RF_IN is 1.04 volt. CK5 resets NQ2 to ground through reset switch 36 during the second phases. During the first phases, CK4 is high and hold switch 38 connects NQ2 to output NQ3. The voltage on output NQ3 rises or falls as charge is shared between sampling capacitor 34 in the second channel and summing output capacitor 94. In this ideal example, NQ3 matches NQ2, but in a real circuit some voltage losses could occur. Thus NQ3 changes to 0.63 volt during the first phase of the third cycle of RF_IN.
The output NQ3 is alternately driven by the first channel and the second channel in alternate cycles of the input RF_IN. Each channel can operate at half of the overall speed and data rate of RF_IN. Thus the data rate supported may be doubled by operating the two channels in parallel.
Both a positive envelope detector, such as shown in
Since there is only one channel, the maximum sampling rate is half of that for
When the input signal RF_IN is ASK coded or Amplitude-Modulated (AM), the frequency and phase of carrier wave 102 is relatively constant. Only the amplitude is modulated. Thus the clock tends to be very stable. An independent clock source may be generated with the same frequency as the carrier wave of the transmitter that generates RF_IN. The phase of the clock source may be matched or locked to the phase of RF_IN using a Phase-Locked Loop (PLL) or by other methods, but this is not necessary. When the maximum data rate is used, a PLL may be added so that the rising clock edge occurs when RF_IN is below ground or the midpoint voltage. Multiple clock phases may be generated, and a clock phase that samples RF_IN below ground is selected for use. Since the peaks of RF_IN are sampled over one full cycle, the exact timing of the clocks is less sensitive to the exact phase, or phase errors between input RF_IN and the clock source. The peak voltage is captured even when some phase error exists. Since the internal sampling capacitors are reset after each sample by reset switches, there is little or no carry over to future cycles should a sampling error occur for one cycle.
The charge merging function that was performed by output capacitor 94 (
First channel 70 samples RF_IN on the first of every four RF_IN cycles through sample switch 20 when CK1 is high to charge sampling capacitor 24 as described for
Second channel 72 samples RF_IN on the second of every four RF_IN cycles through sample switch 30 when CK6 is high to charge sampling capacitor 34 as described for
Third channel 74 samples RF_IN on the third of every four RF_IN cycles through a sample switch when CK7 is high to charge an internal sampling capacitor. A hold switch shares charge to an output capacitor on output node NQ5 when CK8 is high. CK9 discharges the internal sampling capacitor using a reset switch. Switches and capacitors within third channel 74 are the same as for first channel 70 but are not shown.
Fourth channel 76 samples RF_IN on the fourth of every four RF_IN cycles through a sample switch when CK10 is high to charge an internal sampling capacitor. A hold switch shares charge to an output capacitor on output node NQ6 when CK11 is high. CK12 discharges the internal sampling capacitor using a reset switch. Switches and capacitors within fourth channel 76 are the same as for first channel 70 but are not shown.
Clock generator 40 generates the clocks CK1-CK12 as shown in the timing diagrams
Having four channels rather than two channels allows the switches, capacitors, and other circuitry within each channel to have twice as much time to operate. There is twice as much time available for charge sharing, charging, and discharging as for the two-channel embodiment, assuming identical conditions, process, and device sizes. The four channel embodiment may have a maximum theoretical data rate of double that of the two channel detector.
During the first of every four cycles of RF_IN, CK1 goes high to allow the first channel to sampled RF_IN. Then in the second cycle of RF_IN CK2 goes high to open the old switch and adjust the first-channel output NQ3 to post-processing circuit 50. Finally CK3 goes high to reset the first channel and discharge the internal sampling capacitor 24.
During the second of every four cycles of RF_IN, CK6 goes high to allow the second channel to sampled RF_IN. Then in the third cycle of RF_IN CK4 goes high to open the old switch and adjust the second-channel output NQ4 to post-processing circuit 50. Finally CK5 goes high to reset the second channel and discharge the internal sampling capacitor 34.
During the third of every four cycles of RF_IN, CK7 goes high to allow the third channel to sampled RF_IN. Then in the fourth cycle of RF_IN CK8 goes high to open the old switch and adjust the third-channel output NQ5 to post-processing circuit 50. Finally CK9 goes high to reset the third channel and discharge its internal sampling capacitor.
During the fourth of every four cycles of RF_IN, CK10 goes high to allow the fourth channel to sampled RF_IN. Then in the following first cycle (fifth) of RF_IN CK11 goes high to open the old switch and adjust the fourth-channel output NQ5 to post-processing circuit 50. Finally CK12 goes high to reset the fourth channel and discharge its internal sampling capacitor.
Post-processing circuit 50 receives the channel inputs NQ3-NQ6 with a delay of about one cycle of input RF_IN. Some additional delay by post-processing circuit 50 occurs before the final envelope detection signal is available to other circuits.
The width of hold clocks CK2, CK4, CK8, and CK11 are increased from half a cycle to three half-cycles. Likewise, the width of reset clocks CK3, CK5, CK9, and CK12 are increased from half a cycle to three half-cycles, and are delayed until after the hold clocks have been de-asserted. Post-processing circuit 50 still receives the channel outputs NQ3-NQ6 at the same time theoretically, although when the circuit is running at a higher speed the charge-sharing delays may push the actual time when the output signals are stable into a latter cycle.
When CK is high, n-channel transistor 82 closes the drain to source connection, allowing current flow and connecting together the two terminals. Also, CKB is low, so p-channel transistor 84 closes the drain to source connection, allowing current flow and connecting together the two terminals.
When CK is low, n-channel transistor 82 opens the drain to source connection, blocking current flow and isolating the two terminals. Also, CKB is high, so p-channel transistor 84 opens the drain to source connection, blocking current flow and isolating the two terminals.
The bulk or substrate terminal of n-channel transistor 82 can be connected to the lowest available voltage, such as ground when the midpoint is VDD/2, or to an average of the negative peak voltages, or to a substrate bias voltage VBB. Similarly, the bulk or substrate terminal of p-channel transistor 84 can be connected to the highest available voltage, such as VDD.
Several other embodiments are contemplated by the inventors. For example various combinations of the embodiments shown are contemplated. Any embodiment may use a clock recovered from input RF_IN or from an independent clock source as shown in
Output capacitor 44 followed by buffers or demodulator stages or post-processing circuit 50 may generate a full-swing, rail-to-rail output signal. Clock-recovery inverter 42 may be a limiting amplifier or a chain of inverters to perform clock recovery or demodulation. Clock generator 40 may be a combination of latches, flip-flops, logic gates, inverters, delay cells, buffers, and transmission gates. The independent clock source CK_SRC may be generated from the input signal RF_IN or a pre-cursor, and thus the clock source CK_SRC may not be truly independent but be a derived clock source. The clock source CK_SRC could have a different frequency than RF_IN, such as by being a multiple or a divided version of the transmitted carrier wave. Clocks may be non-overlapping, or may be tweaked, skewed, or have edges delayed to prevent race or feed-through conditions.
Although single-ended signals have been described, fully differential signals could also be used with the envelope detector. Fully differential switches could be used, or two paths, for positive and negative differential lines, could be dedicated to each differential signal. Rather than grounding components, the grounded terminals could be connected to the other of the differential paths.
While a Radio-Frequency (RF) input RF_IN has been described, the frequency of the input does not have to be in the RF range, but could be other frequencies, such as audio or microwave. While Amplitude-Modulation (AM) and Amplitude-Shift-Keying (ASK) coded inputs have been described, other kinds of amplitude modulation coding schemes could be used, such as Pulse-Amplitude-Modulation (PAM). While the RF_IN input being generated by a transmitter and received by a receiver has been described as a general environment, the transmitter and receiver could be on the same board, substrate, or chip. While a carrier wave that is a sine wave has been described, the carrier wave could have other shapes, such as a rectangular wave, a triangle wave, saw tooth wave, etc. or various distortions, especially at higher speeds.
The envelope detection circuit may be used for other applications and systems, such as for Global-Positioning Systems (GPS), Near-Field-Communications (NFC), Radio-Frequency Identification (RFID) readers, cable modems, Radio-Frequency (RF) base stations, transmitters, and receivers.
In an actual system the peak voltages may be larger or smaller than shown in
While diode 22 has been shown after sample switch 20, diode 22 could be located before sample switch 20. Then a single diode could be substituted for the two diodes 22, 32. The merged or combined diode is placed between RF_IN and a rectifier node. The rectifier node connects to the left inputs of switch 20 and of switch 30. Thus a single combined diode is used for both channels. Likewise, other diodes could be placed before or after sample switches while still being in series with the sample switches.
Although in the ideal case there is little or no voltage drop between the ideal envelope signal and the actual envelop signal, such as shown in
While diodes have been described in each channel, these diodes could be p-n junctions or could be diode-connected transistors. A bridge rectifier or an external rectifier could also be used. An n-channel transistor with its gate and drain connected together and to sample switch 20 with a source connected to node NQ1 can act as a diode for positive envelope detection. Capacitors may be transistors with sources and drains connected together as one capacitor terminal, and the gate as the second capacitor terminal. Other kinds of capacitors could be used, such as a Metal-Insulator-Metal (MIM) capacitor or a Metal-Oxide-Metal (MoM) capacitor or Metal-Metal or Poly-Poly or Metal-Poly or other off-chip capacitors such as a ceramic capacitor or a thin-film capacitor or a polyester capacitor.
Some embodiments may not use all components. For example, switches may be added or deleted in some embodiments. Different kinds of switches may be used, such as 2-way switches or 3-way switches. Muxes may be used as switches. Input or output resistors could be added, or input or output filters used. Inversions may be added.
Capacitors, resistors, and other filter elements may be added. Switches could be n-channel transistors, p-channel transistors, or transmission gates with parallel n-channel and p-channel transistors, or more complex circuits, either passive or active, amplifying or non-amplifying. External switches such as relays could also be used.
Additional components may be added at various nodes, such as resistors, capacitors, inductors, transistors, extra buffering, etc., and parasitic components may also be present. Enabling and disabling the circuit could be accomplished with additional transistors or in other ways. Pass-gate transistors or transmission gates could be added for isolation.
The final sizes of transistors, capacitors, and other components may be selected after circuit simulation or field testing. Metal-mask options or other programmable components may be used to select the final transistor sizes. Transistors may be connected together in parallel to create larger transistors that have the same fringing or perimeter effects across several sizes. Currents may be positive currents or negative currents that flow in an opposite direction. Charging of a capacitor may be charging with positive charge or charging with negative charge. Thus the terms charging and discharging can be with respect to current in either direction, or with either positive or negative charges. Peaks in the input signal may be positive peaks or negative peaks (troughs).
The background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant.
Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result.
Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Number | Name | Date | Kind |
---|---|---|---|
3241079 | Snell | Mar 1966 | A |
5614851 | Holzer et al. | Mar 1997 | A |
5724002 | Hulick | Mar 1998 | A |
7269395 | Choi et al. | Sep 2007 | B2 |
7737731 | Luo et al. | Jun 2010 | B1 |
7907005 | Kranabenter | Mar 2011 | B2 |
20100189196 | Wang et al. | Jul 2010 | A1 |
20120083205 | Marcu et al. | Apr 2012 | A1 |
20130101064 | Sorrells et al. | Apr 2013 | A1 |
20130170583 | Ichiyama et al. | Jul 2013 | A1 |