Patent Grant
7834671
1. Field of the Invention
The present invention relates to an analog buffer, and more particularly, to an analog buffer with voltage compensation mechanism.
2. Description of the Related Art
Because liquid crystal display (LCD) devices are characterized by thin appearance, low power consumption, and low radiation, LCD devices have been widely applied in various electronic products for panel displaying. The operation of an LCD device is featured by varying voltage drops between opposite sides of the liquid crystal cells of the LCD device for twisting the angles of the liquid crystal molecules in the liquid crystal cells so that the transparency of the liquid crystal cells can be controlled for illustrating images with the aid of the light source provided by a backlight module.
In general, the LCD device comprises a plurality of pixel units, a plurality of data lines and a source driver. The source driver comprises a plurality of source driving circuits. The source driving circuits perform latching operations, level shifting operations, digital-to-analog converting operations and analog signal buffering operations on the digital image data signals inputted to the LCD device for generating a plurality of analog signals. Each source driving circuit is coupled to a corresponding data line for writing the generated analog signals into corresponding pixel units.
Accordingly, the analog buffer of each source driving circuit for performing the analog signal buffering operation functions as a key element for writing the generated analog signals into corresponding pixel units. With the aid of the analog buffers having enhanced driving ability for performing high-speed and accurate buffering operations, the LCD device is capable of providing high display quality. That is, the display quality of the LCD device is corresponding directly to the performance of the analog buffers. Furthermore, the source driver is installed with lots of analog buffers in that each source driving circuit should be installed with an individual analog buffer, and therefore a significant part of the layout area of the LCD device is required for accommodating the analog buffers. For that reason, simplified designs of the analog buffer and related control circuit without degrading the driving performance are required for realizing advanced low-cost LCD devices having thinner appearance.
In accordance with an embodiment of the present invention, an analog buffer with voltage compensation mechanism is disclosed. The analog buffer comprises a first transistor, a second transistor, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch.
The first transistor comprises a drain for receiving a first supply voltage, a source for outputting an output voltage, and a gate. The second transistor comprises a drain for receiving a second supply voltage, a source coupled to the source of the first transistor, and a gate. The first capacitor comprises a first end coupled to the gate of the first transistor, and a second end. The second capacitor comprises a first end coupled to the gate of the second transistor, and a second end. The first switch comprises a first end coupled to the second end of the first capacitor, and a second end coupled to the source of the first transistor. The second switch comprises a first end coupled to the second end of the second capacitor, and a second end coupled to the source of the second transistor. The third switch comprises a first end for receiving a first reference voltage, and a second end coupled to the first end of the first capacitor. The fourth switch comprises a first end for receiving a second reference voltage, and a second end coupled to the first end of the second capacitor. The fifth switch comprises a first end for receiving an input voltage, and a second end coupled to the second end of the first capacitor. The sixth switch comprises a first end for receiving the input voltage, and a second end coupled to the second end of the second capacitor. The analog buffer performs a voltage compensation operation for generating the output voltage based on the first reference voltage and the second reference voltage.
In accordance with another embodiment of the present invention, an analog buffer with voltage compensation mechanism is disclosed. The analog buffer comprises a first transistor, a second transistor, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, a fourth capacitor, a seventh switch, an eighth switch, a ninth switch, and a tenth switch.
The first transistor comprises a drain for receiving a first supply voltage, a source for outputting an output voltage, and a gate. The second transistor comprises a drain for receiving a second supply voltage, a source coupled to the source of the first transistor, and a gate. The first capacitor comprises a first end coupled to the gate of the first transistor, and a second end. The second capacitor comprises a first end coupled to the gate of the second transistor, and a second end. The first switch comprises a first end coupled to the second end of the first capacitor, and a second end coupled to the source of the first transistor. The second switch comprises a first end coupled to the second end of the second capacitor, and a second end coupled to the source of the second transistor. The third switch comprises a first end for receiving a first reference voltage, and a second end coupled to the first end of the first capacitor. The fourth switch comprises a first end for receiving a second reference voltage, and a second end coupled to the first end of the second capacitor. The fifth switch comprises a first end for receiving an input voltage, and a second end coupled to the second end of the first capacitor. The sixth switch comprises a first end for receiving the input voltage, and a second end coupled to the second end of the second capacitor. The third capacitor comprises a first end coupled to the gate of the first transistor, and a second end. The fourth capacitor comprises a first end coupled to the gate of the second transistor, and a second end. The seventh switch comprises a first end coupled to the first end of the fifth switch, and a second end coupled to the second end of the third capacitor. The eighth switch comprises a first end coupled to the first end of the sixth switch, and a second end coupled to the second end of the fourth capacitor. The ninth switch comprises a first end coupled to the second end of the third capacitor, and a second end coupled to the source of the first transistor. The tenth switch comprises a first end coupled to the second end of the fourth capacitor, and a second end coupled to the source of the second transistor. The analog buffer performs a voltage compensation operation for generating the output voltage based on the first reference voltage and the second reference voltage.
In accordance with another embodiment of the present invention, an analog buffer with voltage compensation mechanism is disclosed. The analog buffer comprises a first transistor, a second transistor, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a third transistor, a fourth transistor, a seventh switch, an eighth switch, a ninth switch, and a tenth switch.
The first transistor comprises a drain for receiving a first supply voltage, a source for outputting an output voltage, and a gate. The second transistor comprises a drain for receiving a second supply voltage, a source coupled to the source of the first transistor, and a gate. The first capacitor comprises a first end coupled to the gate of the first transistor, and a second end. The second capacitor comprises a first end coupled to the gate of the second transistor, and a second end. The first switch comprises a first end coupled to the second end of the first capacitor, and a second end coupled to the source of the first transistor. The second switch comprises a first end coupled to the second end of the second capacitor, and a second end coupled to the source of the second transistor. The third switch comprises a first end for receiving a first reference voltage, and a second end coupled to the first end of the first capacitor. The fourth switch comprises a first end for receiving a second reference voltage, and a second end coupled to the first end of the second capacitor. The fifth switch comprises a first end for receiving an input voltage, and a second end coupled to the second end of the first capacitor. The sixth switch comprises a first end for receiving the input voltage, and a second end coupled to the second end of the second capacitor. The third transistor comprises a drain for receiving a third supply voltage, a source coupled to the source of the first transistor, and a gate. The fourth transistor comprises a drain for receiving a fourth supply voltage, a source coupled to the source of the second transistor, and a gate. The seventh switch comprises a first end coupled to the gate of the third transistor, and a second end coupled to the source of the third transistor. The eighth switch comprises a first end coupled to the gate of the fourth transistor, and a second end coupled to the source of the fourth transistor. The ninth switch comprises a first end coupled to the gate of the first transistor, and a second end coupled to the gate of the third transistor. The tenth switch comprises a first end coupled to the gate of the second transistor, and a second end coupled to the gate of the fourth transistor. The analog buffer performs a voltage compensation operation for generating the output voltage based on the first reference voltage and the second reference voltage.
In accordance with another embodiment of the present invention, an analog buffer with voltage compensation mechanism is disclosed. The analog buffer comprises a first transistor, a second transistor, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, a fourth capacitor, a seventh switch, an eighth switch, a ninth switch, a tenth switch, a third transistor, a fourth transistor, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch.
The first transistor comprises a drain for receiving a first supply voltage, a source for outputting an output voltage, and a gate. The second transistor comprises a drain for receiving a second supply voltage, a source coupled to the source of the first transistor, and a gate. The first capacitor comprises a first end coupled to the gate of the first transistor, and a second end. The second capacitor comprises a first end coupled to the gate of the second transistor, and a second end. The first switch comprises a first end coupled to the second end of the first capacitor, and a second end coupled to the source of the first transistor. The second switch comprises a first end coupled to the second end of the second capacitor, and a second end coupled to the source of the second transistor. The third switch comprises a first end for receiving a first reference voltage, and a second end coupled to the first end of the first capacitor. The fourth switch comprises a first end for receiving a second reference voltage, and a second end coupled to the first end of the second capacitor. The fifth switch comprises a first end for receiving an input voltage, and a second end coupled to the second end of the first capacitor. The sixth switch comprises a first end for receiving the input voltage, and a second end coupled to the second end of the second capacitor. The third capacitor comprises a first end coupled to the gate of the first transistor, and a second end. The fourth capacitor comprises a first end coupled to the gate of the second transistor, and a second end. The seventh switch comprises a first end coupled to the first end of the fifth switch, and a second end coupled to the second end of the third capacitor. The eighth switch comprises a first end coupled to the first end of the sixth switch, and a second end coupled to the second end of the fourth capacitor. The ninth switch comprises a first end coupled to the second end of the third capacitor, and a second end coupled to the source of the first transistor. The tenth switch comprises a first end coupled to the second end of the fourth capacitor, and a second end coupled to the source of the second transistor. The third transistor comprises a drain for receiving a third supply voltage, a source coupled to the source of the first transistor, and a gate. The fourth transistor comprises a drain for receiving a fourth supply voltage, a source coupled to the source of the second transistor, and a gate. The eleventh switch comprises a first end coupled to the gate of the third transistor, and a second end coupled to the source of the third transistor. The twelfth switch comprises a first end coupled to the gate of the fourth transistor, and a second end coupled to the source of the fourth transistor. The thirteenth switch comprises a first end coupled to the gate of the first transistor, and a second end coupled to the gate of the third transistor. The fourteenth switch comprises a first end coupled to the gate of the second transistor, and a second end coupled to the gate of the fourth transistor. The analog buffer performs a voltage compensation operation for generating the output voltage based on the first reference voltage and the second reference voltage.
These and other objectives of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, it is to be noted that the present invention is not limited thereto.
The first transistor 211 comprises a drain for receiving a first supply voltage Vdd1, a source for outputting an output voltage Vout, and a gate. The second transistor 212 comprises a drain for receiving a second supply voltage Vss1, a source coupled to the source of the first transistor 211, and a gate. The first transistor 211 can be an N-type MOS transistor. The second transistor 212 can be a P-type MOS transistor, and the MOS transistor may be replaced by other components have similar functions. In the circuit operation of the analog buffer 200, the first transistor 211 and the second transistor 212 are operated in the class-AB source-follower operation mode based on the common-drain configuration for lowering power consumption.
The seventh switch 237 comprises a first end and a second end respectively coupled to the gate and source of the first transistor 211. The eighth switch 238 comprises a first end and a second end respectively coupled to the gate and source of the second transistor 212. The ninth switch 239 comprises a first end and a second end. The second end of the ninth switch 239 is coupled to the gate of the first transistor 211. The tenth switch 240 comprises a first end and a second end. The second end of the tenth switch 240 is coupled to the gate of the second transistor 212. The third switch 233 comprises a first end coupled to the reference voltage generator 290 for receiving the first reference voltage Vb1, and a second end coupled to the first end of the ninth switch 239. The fourth switch 234 comprises a first end coupled to the reference voltage generator 290 for receiving the second reference voltage Vb2, and a second end coupled to the first end of the tenth switch 240.
The first capacitor 221 comprises a first end and a second end. The first end of the first capacitor 221 is coupled to the second end of the third switch 233. The second capacitor 222 comprises a first end and a second end. The first end of the second capacitor 222 is coupled to the second end of the fourth switch 234. The fifth switch 235 comprises a first end for receiving an input voltage Vin, and a second end coupled to the second end of the first capacitor 221. The sixth switch 236 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the second capacitor 222. The first switch 231 comprises a first end and a second end respectively coupled to the second end of the first capacitor 221 and the source of the first transistor 211. The second switch 232 comprises a first end and a second end respectively coupled to the second end of the second capacitor 222 and the source of the second transistor 212.
In one embodiment, the internal circuit structure of the reference voltage generator 290 in
In another embodiment, the internal circuit structure of the reference voltage generator 290 in
When the first control signal P1 and the first enable control signal Ea are set to be enabled signals and the second control signal P2 and the second enable control signal Eab are set to be disabled signals during the interval T10, the output voltage Vout is changed from the previous voltage V0±ΔV0 to the preset voltage Vpreset; meanwhile, the first capacitor 221 is charged to have the capacitor voltage as the gate-source voltage of the first transistor 211 in turn-on state, and the second capacitor 222 is charged to have the capacitor voltage as the gate-source voltage of the second transistor 212 in turn-on state.
When the second control signal P2 and the first enable control signal Ea are set to be enabled signals and the first control signal P1 and the second enable control signal Eab are set to be disabled signals during the interval T11, the output voltage Vout is changed from the preset voltage Vpreset to the voltage V1±ΔV1 based on the voltage V1 of the input voltage Vin in conjunction with the capacitor voltages of the first capacitor 221 and the second capacitor 222. Since the gate-source voltages of the first transistor 211 and the second transistor 212 in turn-on state are compensated by the capacitor voltages of the first capacitor 221 and the second capacitor 222, the variation error ΔV1 can be lowered to an acceptable tiny offset with respect to the input voltage Vin.
When the second enable control signal Eab is set to be an enabled signal and the first control signal P1, the second control signal P2 and the first enable control signal Ea are set to be disabled signals during the interval T12, the first transistor 211 and the second transistor 212 are turned off for retaining the voltage V1±ΔV1 of the output voltage Vout and for saving power consumption corresponding to the first transistor 211 and the second transistor 212.
When the first control signal P1 and the first enable control signal Ea are set to be enabled signals and the second control signal P2 and the second enable control signal Eab are set to be disabled signals during the interval T20, the output voltage Vout is changed from the voltage V1±ΔV1 to the preset voltage Vpreset; meanwhile, the first capacitor 221 and the second capacitor 222 are charged to have the capacitor voltages respectively equal to the gate-source voltages of the first transistor 211 and the second transistor 212 in turn-on state.
When the second control signal P2 and the first enable control signal Ea are set to be enabled signals and the first control signal P1 and the second enable control signal Eab are set to be disabled signals during the interval T21, the output voltage Vout is changed from the preset voltage Vpreset to the voltage V2±ΔV2 based on the voltage V2 of the input voltage Vin in conjunction with the capacitor voltages of the first capacitor 221 and the second capacitor 222. Since the gate-source voltages of the first transistor 211 and the second capacitor 222 in turn-on state are compensated by the capacitor voltages of the first capacitor 221 and the second capacitor 222, the variation error ΔV2 can be lowered to an acceptable tiny offset with respect to the input voltage Vin.
When the second enable control signal Eab is set to be an enabled signal and the first control signal P1, the second control signal P2 and the first enable control signal Ea are set to be disabled signals during the interval T22, the first transistor 211 and the second transistor 212 are turned off for retaining the voltage V2±ΔV2 of the output voltage Vout and for saving power consumption corresponding to the first transistor 211 and the second transistor 212.
Based on the above description, it is obvious that the seventh switch 237 through the tenth switch 240 are utilized to control on/off states of the first transistor 211 and the second transistor 212 for saving power consumption. If the design key issue of the analog buffer 200 is focused on production cost instead of power consumption, then the seventh switch 237 through the tenth switch 240 can be omitted for lowering production cost. That is, in another embodiment of the analog buffer 200, the seventh switch 237 and the eighth switch 238 are replaced with open circuits, and the ninth switch 239 and the tenth switch 240 are replaced with short circuits, which is also applied to the following embodiments. It is noted that the enable signal and the disable signal are not limited to the signals having high voltage level and low voltage level respectively. In another embodiment, the enable signal and the disable signal can be set as the signals having low voltage level and high voltage level respectively without degrading the performance of the analog buffer.
The first transistor 511 comprises a drain for receiving a first supply voltage Vdd1, a source for outputting an output voltage Vout, and a gate. The second transistor 512 comprises a drain for receiving a second supply voltage Vss1, a source coupled to the source of the first transistor 511, and a gate. The first transistor 511 can be an N-type MOS transistor. The second transistor 512 can be a P-type MOS transistor. In the circuit operation of the analog buffer 500, the first transistor 511 and the second transistor 512 are operated in the class-AB source-follower operation mode based on the common-drain configuration for lowering power consumption.
The eleventh switch 541 comprises a first end and a second end respectively coupled to the gate and source of the first transistor 511. The twelfth switch 542 comprises a first end and a second end respectively coupled to the gate and source of the second transistor 512. The thirteenth switch 543 comprises a first end and a second end. The second end of the thirteenth switch 543 is coupled to the gate of the first transistor 511. The fourteenth switch 544 comprises a first end and a second end. The second end of the fourteenth switch 544 is coupled to the gate of the second transistor 512. The third capacitor 523 comprises a first end and a second end. The first end of the third capacitor 523 is coupled to the first end of the thirteenth switch 543. The fourth capacitor 524 comprises a first end and a second end. The first end of the fourth capacitor 524 is coupled to the first end of the fourteenth switch 544. The ninth switch 539 comprises a first end coupled to the second end of the third capacitor 523, and a second end coupled to the source of the first transistor 511. The tenth switch 540 comprises a first end coupled to the second end of the fourth capacitor 524, and a second end coupled to the source of the second transistor 512.
The seventh switch 537 comprises a first end for receiving an input voltage Vin, and a second end coupled to the second end of the third capacitor 523. The eighth switch 538 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the fourth capacitor 524. The third switch 533 comprises a first end coupled to the reference voltage generator 590 for receiving the first reference voltage Vb1, and a second end coupled to the first end of the thirteenth switch 543. The fourth switch 534 comprises a first end coupled to the reference voltage generator 590 for receiving the second reference voltage Vb2, and a second end coupled to the first end of the fourteenth switch 544.
The first capacitor 521 comprises a first end and a second end. The first end of the first capacitor 521 is coupled to the second end of the third switch 533. The second capacitor 522 comprises a first end and a second end. The first end of the second capacitor 522 is coupled to the second end of the fourth switch 534. The fifth switch 535 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the first capacitor 521. The sixth switch 536 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the second capacitor 522. The first switch 531 comprises a first end and a second end respectively coupled to the second end of the first capacitor 521 and the source of the first transistor 511. The second switch 532 comprises a first end and a second end respectively coupled to the second end of the second capacitor 522 and the source of the second transistor 512. The fifteenth switch 545 comprises a first end and a second end respectively coupled to the second end of the first capacitor 521 and the second end of the second capacitor 522.
In one embodiment, the internal circuit structure of the reference voltage generator 590 in
When the first control signal P1 and the first enable control signal Ea are set to be enabled signals and the second control signal P2, the third control signal P3 and the second enable control signal Eab are set to be disabled signals during the interval T10, the output voltage Vout is changed from the previous voltage V0±ΔV02 to the preset voltage Vpreset; meanwhile, the first capacitor 521 is charged to have the capacitor voltage as the first gate-source voltage of the first transistor 511 in turn-on state, and the second capacitor 522 is charged to have the capacitor voltage as the second gate-source voltage of the second transistor 512 in turn-on state.
When the second control signal P2 and the first enable control signal Ea are set to be enabled signals and the first control signal P1, the third control signal P3 and the second enable control signal Eab are set to be disabled signals during the interval T11, the output voltage Vout is changed from the preset voltage Vpreset to the voltage V1±ΔV11 based on the voltage V1 of the input voltage Vin in conjunction with the capacitor voltages of the first capacitor 521 and the second capacitor 522. Since the third gate-source voltage of the first transistor 511 in turn-on state is compensated by the capacitor voltage (the first gate-source voltage) of the first capacitor 521 and the fourth gate-source voltage of the second transistor 512 in turn-on state is compensated by the capacitor voltage (the second gate-source voltage) of the second capacitor 522, the variation error is reduced to ΔV11. However, the third gate-source voltage and the fourth gate-source voltage are not completely compensated by the first gate-source voltage and the second gate-source voltage respectively. Consequently, the third capacitor 523 and the fourth capacitor 524 are charged to have the capacitor voltages respectively equal to the third gate-source voltage and the fourth gate-source voltage during the interval T11 for the following compensation operation.
When the third control signal P3 and the first enable control signal Ea are set to be enabled signals and the first control signal P1, the second control signal P2 and the second enable control signal Eab are set to be disabled signals during the interval T12, the fifteenth switch 545 is turned on for shorting the second ends of the first capacitor 521 and the second capacitor 522 so that the third capacitor 523 and the fourth capacitor 524 are capable of holding the third gate-source voltage and the fourth gate-source voltage respectively for performing accurate compensation operation. Then, the output voltage Vout is changed from the voltage V1±ΔV11 to the voltage V1±ΔV12 based on the voltage V1 of the input voltage Vin in conjunction with the capacitor voltages (the third gate-source voltage and the fourth gate-source voltage) of the third capacitor 523 and the fourth capacitor 524. That is, the accurate compensation operation reduces the variation error from ΔV11 to ΔV12 for generating the output voltage Vout having an acceptable tiny offset with respect to the input voltage Vin.
When the second enable control signal Eab is set to be an enabled signal and the first control signal P1, the second control signal P2, the third control signal P3 and the first enable control signal Ea are set to be disabled signals during the interval T13, the first transistor 511 and the second transistor 512 are turned off for retaining the voltage V1±ΔV12 of the output voltage Vout and for saving power consumption corresponding to the first transistor 511 and the second transistor 512. The circuit operations of the analog buffer 500 from the interval T20 to the interval T23 are similar to the aforementioned circuit operations from the interval T10 to the interval T13, and for the sake of brevity, further similar description is omitted.
The first transistor 611 comprises a drain for receiving a first supply voltage Vdd1, a source for outputting an output voltage Vout, and a gate. The second transistor 612 comprises a drain for receiving a second supply voltage Vss1, a source coupled to the source of the first transistor 611, and a gate. The third transistor 613 comprises a drain for receiving a fifth supply voltage Vdd3, a source coupled to the source of the first transistor 611, and a gate. The fourth transistor 614 comprises a drain for receiving a sixth supply voltage Vss3, a source coupled to the source of the second transistor 612, and a gate. In the circuit operation of the analog buffer 600, the fifth supply voltage Vdd3 can be set to be greater than the first supply voltage Vdd1, and the sixth supply voltage Vss3 can be set to be less than the second supply voltage Vss1 for achieving high-speed voltage adjusting performance while performing auxiliary capacitor charge operations by making use of the third transistor 613 and the fourth transistor 614.
The first transistor 611 and the third transistor 613 can be N-type MOS transistors. The second transistor 612 and the fourth transistor 614 can be P-type MOS transistors. In the circuit operation of the analog buffer 600, the first transistor 611, the second transistor 612, the third transistor 613 and the fourth transistor 614 are operated in the class-AB source-follower operation mode based on the common-drain configuration for lowering power consumption.
The seventh switch 637 comprises a first end and a second end respectively coupled to the gate and source of the third transistor 613. The eighth switch 638 comprises a first end and a second end respectively coupled to the gate and source of the fourth transistor 614. The ninth switch 639 comprises a first end coupled to the gate of the first transistor 611, and a second end coupled to the gate of the third transistor 613. The tenth switch 640 comprises a first end coupled to the gate of the second transistor 612, and a second end coupled to the gate of the fourth transistor 614. The eleventh switch 641 comprises a first end and a second end respectively coupled to the gate and source of the first transistor 611. The twelfth switch 642 comprises a first end and a second end respectively coupled to the gate and source of the second transistor 612.
The thirteenth switch 643 comprises a first end and a second end. The second end of the thirteenth switch 643 is coupled to the gate of the first transistor 611. The fourteenth switch 644 comprises a first end and a second end. The second end of the fourteenth switch 644 is coupled to the gate of the second transistor 612. The third switch 633 comprises a first end coupled to the reference voltage generator 690 for receiving the first reference voltage Vb1, and a second end coupled to the first end of the thirteenth switch 643. The fourth switch 634 comprises a first end coupled to the reference voltage generator 690 for receiving the second reference voltage Vb2, and a second end coupled to the first end of the fourteenth switch 644.
The first capacitor 621 comprises a first end and a second end. The first end of the first capacitor 621 is coupled to the second end of the third switch 633. The second capacitor 622 comprises a first end and a second end. The first end of the second capacitor 622 is coupled to the second end of the fourth switch 634. The fifth switch 635 comprises a first end for receiving an input voltage Vin, and a second end coupled to the second end of the first capacitor 621. The sixth switch 636 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the second capacitor 622. The first switch 631 comprises a first end and a second end respectively coupled to the second end of the first capacitor 621 and the source of the first transistor 611. The second switch 632 comprises a first end and a second end respectively coupled to the second end of the second capacitor 622 and the source of the second transistor 612.
In one embodiment, the internal circuit structure of the reference voltage generator 690 in
When the first control signal P1, the first enable control signal Ea and the third enable control signal Q1 are set to be enabled signals and the second control signal P2, the second enable control signal Eab and the fourth enable control signal Q1b are set to be disabled signals during the interval T10, the output voltage Vout is changed from the previous voltage V0±ΔV0 to the preset voltage Vpreset; meanwhile, the first capacitor 621 is charged to have the capacitor voltage as the gate-source voltage of the first transistor 611 and the third transistor 613 in turn-on state, and the second capacitor 622 is charged to have the capacitor voltage as the gate-source voltage of the second transistor 612 and the fourth transistor 614 in turn-on state. Since the voltage adjustments of the capacitor voltages of the first capacitor 621 and the second capacitor 622 are performed via the first transistor 611 through the fourth transistor 614, the charging operations for the first capacitor 621 and the second capacitor 622 can be carried out much faster for shortening the interval T10 so that the analog buffer 600 is able to perform analog signal buffering operations at a higher speed.
When the second control signal P2, the first enable control signal Ea and the fourth enable control signal Q1b are set to be enabled signals and the first control signal P1, the second enable control signal Eab and the third enable control signal Q1 are set to be disabled signals during the interval T11, the output voltage Vout is changed from the preset voltage Vpreset to the voltage V1±ΔV1 based on the voltage V1 of the input voltage Vin in conjunction with the capacitor voltages of the first capacitor 621 and the second capacitor 622. Since the gate-source voltages of the first transistor 611 through the fourth transistor 614 in turn-on state are compensated by the capacitor voltages of the first capacitor 621 and the second capacitor 622, the variation error ΔV1 can be lowered to an acceptable tiny offset with respect to the input voltage Vin.
When the second enable control signal Eab and the fourth enable control signal Q1b are set to be enabled signals and the first control signal P1, the second control signal P2, the first enable control signal Ea and the third enable control signal Q1 are set to be disabled signals during the interval T12, the first transistor 611 through the fourth transistor 614 are turned off for retaining the voltage V1±ΔV1 of the output voltage Vout and for saving power consumption corresponding to the first transistor 611 through the fourth transistor 614. The circuit operations of the analog buffer 600 from the interval T20 to the interval T22 are similar to the aforementioned circuit operations from the interval T10 to the interval T12, and for the sake of brevity, further similar description is omitted.
In an alternative circuit operation of the analog buffer 600, the second control signal P2, the first enable control signal Ea and the third enable control signal Q1 are set to be enabled signals and the first control signal P1, the second enable control signal Eab and the fourth enable control signal Q1b are set to be disabled signals during the interval T11 so that the analog buffer 600 is able to perform analog signal buffering operations at a much higher speed by turning on the first transistor 611 through the fourth transistor 614 for fast changing the output voltage Vout from the preset voltage Vpreset to the voltage V1±ΔV1 for shortening the interval T11.
The first transistor 711 comprises a drain for receiving a first supply voltage Vdd1, a source for outputting an output voltage Vout, and a gate. The second transistor 712 comprises a drain for receiving a second supply voltage Vss1, a source coupled to the source of the first transistor 711, and a gate. The third transistor 713 comprises a drain for receiving a fifth supply voltage Vdd3, a source coupled to the source of the first transistor 711, and a gate. The fourth transistor 714 comprises a drain for receiving a sixth supply voltage Vss3, a source coupled to the source of the second transistor 712, and a gate. Similarly, in the circuit operation of the analog buffer 700, the fifth supply voltage Vdd3 can be set to be greater than the first supply voltage Vdd1, and the sixth supply voltage Vss3 can be set to be less than the second supply voltage Vss1 for achieving high-speed voltage adjusting performance while performing auxiliary capacitor charge operations by making use of the third transistor 713 and the fourth transistor 714.
The first transistor 711 and the third transistor 713 can be N-type MOS transistors. The second transistor 712 and the fourth transistor 714 can be P-type MOS transistors. In the circuit operation of the analog buffer 700, the first transistor 711, the second transistor 712, the third transistor 713 and the fourth transistor 714 are operated in the class-AB source-follower operation mode based on the common-drain configuration for lowering power consumption.
The eleventh switch 741 comprises a first end and a second end respectively coupled to the gate and source of the third transistor 713. The twelfth switch 742 comprises a first end and a second end respectively coupled to the gate and source of the fourth transistor 714. The thirteenth switch 743 comprises a first end coupled to the gate of the first transistor 711, and a second end coupled to the gate of the third transistor 713. The fourteenth switch 744 comprises a first end coupled to the gate of the second transistor 712, and a second end coupled to the gate of the fourth transistor 714. The fifteenth switch 745 comprises a first end and a second end respectively coupled to the gate and source of the first transistor 711. The sixteenth switch 746 comprises a first end and a second end respectively coupled to the gate and source of the second transistor 712.
The seventeenth switch 747 comprises a first end and a second end. The second end of the seventeenth switch 747 is coupled to the gate of the first transistor 711. The eighteenth switch 748 comprises a first end and a second end. The second end of the eighteenth switch 748 is coupled to the gate of the second transistor 712. The third capacitor 723 comprises a first end and a second end. The first end of the third capacitor 723 is coupled to the first end of the seventeenth switch 747. The fourth capacitor 724 comprises a first end and a second end. The first end of the fourth capacitor 724 is coupled to the first end of the eighteenth switch 748. The ninth switch 739 comprises a first end coupled to the second end of the third capacitor 723, and a second end coupled to the source of the first transistor 711. The tenth switch 740 comprises a first end coupled to the second end of the fourth capacitor 724, and a second end coupled to the source of the second transistor 712.
The seventh switch 737 comprises a first end for receiving an input voltage Vin, and a second end coupled to the second end of the third capacitor 723. The eighth switch 738 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the fourth capacitor 724. The first capacitor 721 comprises a first end and a second end. The first end of the first capacitor 721 is coupled to the first end of the seventeenth switch 747. The second capacitor 722 comprises a first end and a second end. The first end of the second capacitor 722 is coupled to the first end of the eighteenth switch 748. The third switch 733 comprises a first end coupled to the reference voltage generator 790 for receiving the first reference voltage Vb1, and a second end coupled to the first end of the first capacitor 721. The fourth switch 734 comprises a first end coupled to the reference voltage generator 790 for receiving the second reference voltage Vb2, and a second end coupled to the first end of the second capacitor 722.
The fifth switch 735 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the first capacitor 721. The sixth switch 736 comprises a first end for receiving the input voltage Vin, and a second end coupled to the second end of the second capacitor 722. The first switch 731 comprises a first end and a second end respectively coupled to the second end of the first capacitor 721 and the source of the first transistor 711. The second switch 732 comprises a first end and a second end respectively coupled to the second end of the second capacitor 722 and the source of the second transistor 712. The nineteenth switch 749 comprises a first end and a second end respectively coupled to the second end of the first capacitor 721 and the second end of the second capacitor 722.
In one embodiment, the internal circuit structure of the reference voltage generator 790 in
When the first control signal P1, the first enable control signal Ea and the third enable control signal Q1 are set to be enabled signals and the second control signal P2, the third control signal P3, the second enable control signal Eab and the fourth enable control signal Q1b are set to be disabled signals during the interval T10, the output voltage Vout is changed from the previous voltage V0±ΔV02 to the preset voltage Vpreset; meanwhile, the first capacitor 721 is charged to have the capacitor voltage as the first gate-source voltage of the first transistor 711 and the third transistor 713 in turn-on state, and the second capacitor 722 is charged to have the capacitor voltage as the second gate-source voltage of the second transistor 712 and the fourth transistor 714 in turn-on state. Since the voltage adjustments of the capacitor voltages of the first capacitor 721 and the second capacitor 722 are performed via the first transistor 711 through the fourth transistor 714, the charging operations for the first capacitor 721 and the second capacitor 722 can be carried out much faster for shortening the interval T10 so that the analog buffer 700 is able to perform analog signal buffering operations at a higher speed.
When the second control signal P2, the first enable control signal Ea and the fourth enable control signal Q1b are set to be enabled signals and the first control signal P1, the third control signal P3, the second enable control signal Eab and the third enable control signal Q1 are set to be disabled signals during the interval T11, the output voltage Vout is changed from the preset voltage Vpreset to the voltage V1±ΔV11 based on the voltage V1 of the input voltage Vin in conjunction with the capacitor voltages of the first capacitor 721 and the second capacitor 722. Since the third gate-source voltage of the first transistor 711 and the third transistor 713 in turn-on state is compensated by the capacitor voltage (the first gate-source voltage) of the first capacitor 721 and the fourth gate-source voltage of the second transistor 712 and the fourth transistor 714 in turn-on state is compensated by the capacitor voltage (the second gate-source voltage) of the second capacitor 722, the variation error is reduced to ΔV11. However, the third gate-source voltage and the fourth gate-source voltage are not completely compensated by the first gate-source voltage and the second gate-source voltage respectively. Consequently, the third capacitor 723 and the fourth capacitor 724 are charged to have the capacitor voltages respectively equal to the third gate-source voltage and the fourth gate-source voltage during the interval T11 for the following compensation operation.
When the third control signal P3, the first enable control signal Ea and the fourth enable control signal Q1b are set to be enabled signals and the first control signal P1, the second control signal P2, the second enable control signal Eab and the third enable control signal Q1 are set to be disabled signals during the interval T12, the nineteenth switch 749 is turned on for shorting the second ends of the first capacitor 721 and the second capacitor 722 so that the third capacitor 723 and the fourth capacitor 724 are capable of holding the third gate-source voltage and the fourth gate-source voltage respectively for performing accurate compensation operation. Then, the output voltage Vout is changed from the voltage V1±ΔV11 to the voltage V1±ΔV12 based on the voltage V1 of the input voltage Vin in conjunction with the capacitor voltages (the third gate-source voltage and the fourth gate-source voltage) of the third capacitor 723 and the fourth capacitor 724. That is, the accurate compensation operation reduces the variation error from ΔV11 to ΔV12 for generating the output voltage Vout having an acceptable tiny offset with respect to the input voltage Vin.
When the second enable control signal Eab and the fourth enable control signal Q1b are set to be enabled signals and the first control signal P1, the second control signal P2, the third control signal P3, the first enable control signal Ea and the third enable control signal Q1 are set to be disabled signals during the interval T13, the first transistor 711 through the fourth transistor 714 are turned off for retaining the voltage V1±ΔV12 of the output voltage Vout and for saving power consumption corresponding to the first transistor 711 through the fourth transistor 714. The circuit operations of the analog buffer 700 from the interval T20 to the interval T23 are similar to the aforementioned circuit operations from the interval T10 to the interval T13, and for the sake of brevity, further similar description is omitted.
In an alternative circuit operation of the analog buffer 700, the second control signal P2, the first enable control signal Ea and the third enable control signal Q1 are set to be enabled signals and the first control signal P1, the third control signal P3, the second enable control signal Eab and the fourth enable control signal Q1b are set to be disabled signals during the interval T11 so that the analog buffer 700 is able to perform analog signal buffering operations at a much higher speed by turning on the first transistor 711 through the fourth transistor 714 for fast changing the output voltage Vout from the preset voltage Vpreset to the voltage V1±ΔV11 for shortening the interval T11.
Furthermore, in an alternative circuit operation of the analog buffer 700, the third control signal P3, the first enable control signal Ea and the third enable control signal Q1 are set to be enabled signals and the first control signal P1, the second control signal P2, the second enable control signal Eab and the fourth enable control signal Q1b are set to be disabled signals during the interval T12 so that the analog buffer 700 is able to perform analog signal buffering operations at a much higher speed by turning on the first transistor 711 through the fourth transistor 714 for fast changing the output voltage Vout from the voltage V1±ΔV11 to the voltage V1±ΔV12 for shortening the interval T12. However, the voltage difference between the voltage V1±ΔV11 and the voltage V1±ΔV12 is substantially quite small, and therefore the reduced time of the shortened interval T12 are quite limited, which is paid by much higher power consumption caused by the third transistor 713 and the fourth transistor 714 in turn-on state. Accordingly, in a preferred circuit operation of the analog buffer 700, the third transistor 713 and the fourth transistor 714 are turned off for saving power consumption during the interval T12.
The present invention is by no means limited to the embodiments as described above by referring to the accompanying drawings, which may be modified and altered in a variety of different ways without departing from the scope of the present invention. Thus, it should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alternations might occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 97114802 A | Apr 2008 | TW | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6876235 | Li | Apr 2005 | B2 |
| 20040183772 | Nakajima et al. | Sep 2004 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20090267655 A1 | Oct 2009 | US |
