Analog circuit fault mode classification method

Abstract

An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors Vij to each of fault modes Fi of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors VijF of the voltage signal sample vectors Vij by using subspace projection; (3) standardizing the extracted fault characteristic vectors VijF to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a 371 application of the International PCT application serial no. PCT/CN2015/095424, filed on Nov. 24, 2015, which claims the priority benefit of China application no. 201510482928.2, filed on Aug. 07, 2015. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The present invention relates of the field of analog circuit fault diagnosis, and more particularly, to an analog circuit fault mode classification method.

BACKGROUND

The rapid development of modern electronic and computer technologies drives more and more complicated composition and structure of electronic equipment as well as increasingly large scale thereof. To improve system safety and reliability, higher and newer requirements are raised on circuit test and diagnosis. Analog circuits in an electronic system are prone to get wrong, and analog circuit fault diagnosis has also been a “bottleneck” that restricts the circuit industry of China. It is of great theoretical values and practical significance to develop the analog circuit industry in order to conform to the new development of modern microelectronics technologies and information technologies.

At present, an analog circuit fault model classifier based on a support vector machine has the advantages that it is suitable for small sample decision, has lower requirements on the number of learning samples and can mine the classification information hidden in data under the circumstance of limited characteristic information. But its defects are that the dimensionality of the fault characteristic vectors is too large, which will increase the difficulty of learning and training of the support vector machine. In addition, different processing methods on the training data will also affect the classification accuracy of the fault mode classifier.

SUMMARY

A technical problem to be solved by the present invention is to provide an analog circuit fault mode classification method to overcome the above defects of the prior art, so as to facilitate lightening the learning and training difficulties of the fault mode classifier and improving the classification accuracy of the fault mode classifier.

According to the present invention, a fault mode classifier is constructed on the basis of a support vector machine, and fault characteristics are extracted by using a subspace projection method, then the fault characteristics are standardized, and finally the standardized fault characteristics are utilized to train the support vector machine, so that the analog circuit fault mode classifier is constructed.

A technical solution to be adopted by the present invention to solve the technical problems thereof is as follows:

An analog circuit fault mode classification method comprises the following steps:

An analog circuit fault mode classification method is characterized by comprising the following steps:

(1) collecting M groups of voltage signal sample vectors V_ij at a node to be tested under each of fault modes F_i of the analog circuit by using a data collection board, wherein i=1, 2, . . . , N, j=1, 2, . . . , M V_ij represents a j^th voltage signal sample vector of a i^th fault mode, and N represents a total number of the fault modes;

(2) sequentially extracting fault characteristic vectors V_ij^F of the voltage signal sample vectors V_ij working under the fault modes F_i by using subspace projection, wherein i=1, 2, . . . , N, j=1, 2, . . . , M, and V_ij^F represents a fault characteristic vector of the j^th voltage signal sample under the i^th fault mode;

(3) standardizing the extracted fault characteristic vectors V_ij^F to obtain standardized fault characteristic vectors {circumflex over (V)}_ij^F, wherein a computing method thereof is

${\hat{V}}_{\mathrm{ij}}^F=\frac{V_{\mathrm{ij}}^F}{V_{\mathrm{ij}}^F};$

(4) sequentially constructing a binary-class support vector machine with respect to two different fault modes F_i1 and F_i2, wherein i₁=1, 2, . . . , N, i₂=1, 2, . . . , N, (i₁≠i₂), N is the total number of the fault modes, then N(N−1)/2 different binary-class support vector machines can be constructed in total; and

(5) simultaneously feeding a standardized fault characteristic vectors to be tested into the N(N−1)/2 binary-class support vector machines for classification and determination, and counting votes according to classification results of each binary-class support vector machine; if a fault mode to be tested belongs to the fault mode F_i, and i=1, 2, . . . , N, then adding 1 to the votes of F_i, wherein a fault mode obtaining the most votes finally is the fault mode that the circuit to be tested belongs to.

Further, the step of extracting the fault characteristic vectors V_ij^F by using the subspace projection in step (2) is:

(2.1) computing dimensionality of the voltage signal sample vectors V_ij: L=length(v_ij);

(2.2) generating an L×L dimensional Toeplitz transformation matrix Φ:

$\Phi =\left[\begin{array}{cccc}{F}_{11}& F_{12}& \dots & F_{1L}\\ F_{12}& F_{13}& \dots & F_{11}\\ \dots & \dots & \dots & \dots \\ F_{1L}& F_{11}& \dots & F_{1\left(L-1\right)}\end{array}\right],\mathrm{wherein}$ $F_{1k}=e^{-j\frac{2\pi }{L}k},k=1,2,\dots ,L;$

(2.3) computing a projected vector of the voltage signal sample vectors V_ij in the Toeplitz transformation matrix Φ: V_p=Φ^TV_ij, wherein T represents to transpose a matrix;

(2.4) computing maximum projection subspace and the fault characteristic vectors V_ij^F:

(2.4.1) initializing a subspace projection coordinate dimensionality K: K=┌log₂(N)┐, wherein ┌⋅┐ represents rounding up to an integer, and N is the total number of the fault modes of the circuit to be tested;

(2.4.2) constructing a maximum projection subspace index vector I with a dimensionality of 1×K, and initializing the vector into a 1×K dimensional null vector, i.e., I=[00 . . . 0], and meanwhile constructing a counting variable p and initializing p=1;

(2.4.3) updating the maximum projection subspace index vector I: I(p)=Index(Max(|V_p|)), wherein I(p) herein represents the p^th vector value in the vector I, Max(⋅) represents to compute a maximum vector element, V_p represents the projected vector of the voltage signal sample vectors V_ij in the Toeplitz transformation matrix Φ, and Index(⋅) represents to calculate an index;

(2.4.4) determining whether p<K; if no, then performing step (2.4.5); otherwise, performing p=p+1 and using 0 to replace the maximum element in the projected vector V_P, and retuning to step (2.4.3);

(2.4.5) using I vector elements as row index values of the Toeplitz transformation matrix Φ to extract corresponding row vectors to constitute a matrix Φ_A with a dimensionality of K×L;

(2.4.6) computing the maximum projection subspace Φ_Λ^†: Φ_Λ^†=(Φ_ΛΦ_Λ^T)⁻¹Φ_Λ; and

(2.4.7) computing the fault characteristic vector V_ij^F with subspace projection: V_ij^F=Φ_Λ^†V_ij.

Further, the specific step of constructing each binary-class support vector machine in step (4) is:

(4.1) constructing a binary classifier decision model

$f\left(x\right)=\sum _i^{\stackrel{\_}{N}}{\alpha }_i{y}_i\exp \left(-{x-x_i}^2/2\right)+b,$ wherein N represents the number of training data samples, x_i is called as a support vector, α_i is a certain real number, b is a bias, and y_i∈y={+1, −1} is a class identifier;

(4.2) dividing a training sample set: constituting the standardized fault characteristic vectors {circumflex over (V)}_i1j^F and {circumflex over (V)}_i2j^F under the fault modes F_i1 and F_i2 into a training sample set S={{S₊}, {S₋}}, wherein j=1, 2, . . . , M, S₊={({circumflex over (V)}_i11^F, +1), ({circumflex over (V)}_i12^F, +1), . . . , ({circumflex over (V)}_i1M^F, +1)}, S₋={({circumflex over (V)}_i21^F, −1), ({circumflex over (V)}_i22^F, −1), . . . , ({circumflex over (V)}_i2M^F, −1)}, a class identifier of F_i1 is defined as +1, and a class identifier of F_i2 is defined as −1;

(4.3) using the training sample set S to train the binary classifier decision model so as to determine parameters α_i and b of the binary-class support vector machine;

(4.4) outputting a determination function of the binary-class support vector machine:

$y=\mathrm{sgn}\left(\sum _i^{\stackrel{\_}{N}}{\alpha }_i{y}_i\exp \left(-{x-x_i}^2/2\right)+b\right),$ wherein sgn (⋅) is a sign function, and N represents the number of the training data samples; and

(4.5) completing a mode determination for a characteristic to be tested according to the decision function: determination votes during test process are performed according to the determination function; if y=1 is outputted, then the votes of the fault mode F_i1 plus 1; otherwise, the votes of the fault mode F_i2 plus 1.

Further, the specific step of using the training sample set S to train the binary classifier decision model so as to determine the parameters α_i and b of the binary-class support vector machine in step (4.3) is:

(4.3.1) standardizing a kernel matrix:

$\stackrel{\_}{K}=\left[\begin{array}{cccc}{\stackrel{\_}{K}}_{11}& {\stackrel{\_}{K}}_{12}& \dots & {\stackrel{\_}{K}}_{1,2M}\\ {\stackrel{\_}{K}}_{21}& {\stackrel{\_}{K}}_{22}& \dots & {\stackrel{\_}{K}}_{2,2M}\\ ⋮& ⋮& ⋮& ⋮\\ {\stackrel{\_}{K}}_{2M,1}& {\stackrel{\_}{K}}_{2M,2}& \dots & {\stackrel{\_}{K}}_{2M,2M}\end{array}\right],$ wherein k_ij=exp(−∥x_i−x_j∥²/2), i, j=1, 2, . . . , 2M, M represents the number of the voltage signal sample vectors collected;

D=diag(1/sqrt(diag(K))), wherein diag(⋅) represents to compute a diagonal matrix, and sqrt(⋅) represents to compute a root-mean-square of matrix elements; K is updated: K←D*K*D; and K represents to the standardized kernel matrix;

(4.3.2) training a binary classifier, which a training pseudo-code is as follows:

inputting the training sample set S={{S₊}, {S₋}};

treating process: if a class identifier y_i=+1, then

${\alpha }_i^{+}=\frac{1}{M};$ otherwise, α_i⁺=0;

if a class identifier y_i=−1, then

${\alpha }_i^{-}=\frac{1}{M};$ otherwise, α_i⁻=0; M represents the number of the voltage signal sample vectors collected;

α⁺=[α₁⁺, α₂⁺, . . . , α_2M⁺], α⁻=[α₁⁻, α₂⁻, . . . , α_2M⁻]; and

(4.3.3) computing classifier parameters:

wherein the real number α_i=α_i⁺−α_i⁻; and

the bias b=0.5((α⁺)^TKα⁺−(α⁻)^TKα⁻), wherein (⋅)^T represents transpose of matrix or vector; and K represents to the standardize kernel matrix.

Compared with the prior art, the present invention has the following advantages.

(1) The present invention extracts the fault characteristic vectors by using a subspace projection method in the present invention, and determines a proper dimensionality of the fault characteristic vectors according to the length of the voltage signal sample vectors, ensures the integrality of the fault characteristic information and also reduces redundant fault characteristics, and is beneficial for decreasing the learning and training difficulties of the fault mode classifier.

(2) The present invention uses a standardizing processing method to process the fault characteristic vectors, which has more apparent effects on improving the classification accuracy of the fault mode classifier.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a flow of an analog circuit fault mode classification method according to the invention.

FIG. 2 is a block diagram illustrating steps of constructing a binary-class support vector machine according to the invention.

DETAILED DESCRIPTION

The invention will be described in details hereinafter with reference to the drawings and embodiments.

Referring to FIG. 1, an analog circuit fault mode classification method comprises the following steps:

(1) collecting M groups of voltage signal sample vectors V_ij at a node to be tested under each of the fault modes F_i of the analog circuit by using a data collection board, wherein i=1, 2, . . . , N, j=1, 2, . . . , M, V_ij represents a j^th voltage signal sample vector of a i^th fault mode, and N represents a total number of the fault modes;

(2) sequentially extracting fault characteristic vectors V_ij^F of the voltage signal sample vectors V_ij working under the fault modes F_i by using subspace projection, wherein i=1, 2, . . . , N, j=1, 2, . . . , M, and V_ij^F represents a fault characteristic vector of the j^th voltage signal sample under the i^th fault mode;

(3) standardizing the extracted fault characteristic vectors V_ij^F to obtain standardized fault characteristic vectors {circumflex over (V)}_ij^F, wherein a computing method thereof is

${\hat{V}}_{\mathrm{ij}}^F=\frac{V_{\mathrm{ij}}^F}{V_{\mathrm{ij}}^F};$

(4) sequentially constructing a binary-class support vector machine with respect to two different fault modes F_i1 and F_i2, wherein i₁=1, 2, . . . , N, i₂=1, 2, . . . , N, (i₁≠i₂), N is the total number of the fault modes, then N(N−1)/2 different binary-class support vector machines can be constructed in total; and

(5) simultaneously feeding a standardized fault characteristic vectors to be tested into the N(N−1)/2 binary-class support vector machines for classification and determination, and counting votes according to classification results of each binary-class support vector machine; if a fault mode to be tested belongs to the fault mode F_i, and i=1, 2, . . . , N, then adding 1 to the votes of F_i wherein a fault mode obtaining the most votes finally is the fault mode that the circuit to be tested belongs to.

The step of extracting the fault characteristic vectors V_ij^F by using the subspace projection in step (2) is:

(2.1) computing dimensionality of the voltage signal sample vectors V_ij: L=length(V_ij);

(2.2) generating an L×L dimensional Toeplitz transformation matrix Φ:

$\Phi =\left[\begin{array}{cccc}{F}_{11}& F_{12}& \dots & F_{1L}\\ F_{12}& F_{13}& \dots & F_{11}\\ \dots & \dots & \dots & \dots \\ F_{1L}& F_{11}& \dots & F_{1\left(L-1\right)}\end{array}\right],\mathrm{wherein}$ $F_{1k}=e^{-j\frac{2\pi }{L}k},k=1,2,\dots ,L;$

(2.3) computing a projected vector of the voltage signal sample vectors V_ij in the Toeplitz transformation matrix Φ: V_p=Φ^TV_ij, wherein T represents to transpose a matrix;

(2.4) computing maximum projection subspace and the fault characteristic vectors V_ij^F:

(2.4.1) initializing a subspace projection coordinate dimensionality K: K=┌log₂(N)┐, wherein ┌⋅┐ represents rounding up to an integer, and N is the total number of the fault modes of the circuit to be tested;

(2.4.2) constructing a maximum projection subspace index vector I with a dimensionality of 1×K, and initializing the vector into a 1×K dimensional null vector, i.e., I=[00 . . . 0], and meanwhile constructing a counting variable p and initializing p=1;

(2.4.3) updating the maximum projection subspace index vector I: I(p)=Index(Max(|V_p|)), wherein I(p) herein represents the p^th vector value in the vector I, Max(⋅) represents to compute a maximum vector element, V_p represents the projected vector of the voltage signal sample vectors V_ij in the Toeplitz transformation matrix Φ, and Index(⋅) represents to calculate an index;

(2.4.4) determining whether p<K; if no, then performing step (2.4.5); otherwise, performing p=p+1 and using 0 to replace the maximum element in the projected vector V_p, and retuning to step (2.4.3);

(2.4.5) using I vector elements as row index values of the Toeplitz transformation matrix Φ to extract corresponding row vectors to constitute a matrix Φ_A with a dimensionality of K×L;

(2.4.6) computing the maximum projection subspace Φ_Λ^†: Φ_Λ^†=(Φ_ΛΦ_Λ^T)⁻¹Φ_Λ; and

(2.4.7) computing the fault characteristic vector V_ij^F with subspace projection: V_ij^F=Φ_Λ^†V_ij.

Referring to FIG. 2, the specific step of constructing each binary-class support vector machine in step (4) is:

(4.1) constructing a binary classifier decision model

$f\left(x\right)=\sum _i^{\stackrel{\_}{N}}{\alpha }_i{y}_i\exp \left(-{x-x_i}^2\text{/}2\right)+b,$ wherein N represents the number of training data samples, x_i is called as a support vector, α_i is a certain real number, b is a bias, and y_i∈y={+1, −1} is a class identifier;

(4.2) dividing a training sample set: constituting the standardized fault characteristic vectors {circumflex over (V)}_i1j^F and {circumflex over (V)}_i2j^F under the fault modes F_i1 and F_i2 into a training sample set S={{S₊}, {S₋}}, wherein j=1, 2, . . . , M, S₊={({circumflex over (V)}_i11^F, +1), ({circumflex over (V)}_i12^F, +1), . . . , ({circumflex over (V)}_i1M^F, +1)}, S₋={({circumflex over (V)}_i21^F, −1), ({circumflex over (V)}_i22^F, −1), . . . , ({circumflex over (V)}_i2M^F, −1)}, a class identifier of F_i1 is defined as +1, and a class identifier of F_i2 is defined as −1;

(4.3) using the training sample set S to train the binary classifier decision model so as to determine parameters α_i and b of the binary-class support vector machine;

(4.4) outputting a determination function of the binary-class support vector machine:

$y=\mathrm{sgn}\left(\sum _i^{\stackrel{\_}{N}}{\alpha }_i{y}_i\exp \left(-{x-x_i}^2\text{/}2\right)+b\right),$ wherein sgn(⋅) is a sign function, and N represents the number of the training data samples; and

(4.5) completing a mode determination for a characteristic to be tested according to the decision function: determination votes during test are performed according to the determination function; if y=1 is outputted, then the votes of the fault mode F_i1 plus 1; otherwise, the votes of the fault mode f_i2 plus 1.

The specific step of using the training sample set S to train the binary classifier decision model so as to determine the parameters α_i and b of the binary-class support vector machine in step (4.3) is:

(4.3.1) standardizing a kernel matrix:

$\stackrel{\_}{K}=\left[\begin{array}{cccc}{\stackrel{\_}{K}}_{11}& {\stackrel{\_}{K}}_{12}& \dots & {\stackrel{\_}{K}}_{1,2M}\\ {\stackrel{\_}{K}}_{21}& {\stackrel{\_}{K}}_{22}& \dots & {\stackrel{\_}{K}}_{2,2M}\\ ⋮& ⋮& ⋮& ⋮\\ {\stackrel{\_}{K}}_{2M,1}& {\stackrel{\_}{K}}_{2M,2}& \dots & {\stackrel{\_}{K}}_{2M,2M}\end{array}\right],$ wherein K_ij=exp(−∥x_i−x_j∥²/2), i, j=1, 2, . . . , 2M, M represents the number of the voltage signal sample vectors collected;

D=diag(1/sqrt(diag(K))), wherein diag(⋅) represents to compute a diagonal matrix, and sqrt(⋅) represents to compute a root-mean-square of matrix elements; K is updated: K←D*K*D; and K represents to the standardized kernel matrix;

(4.3.2) training a binary classifier, which a training pseudo-code thereof is as follows:

inputting the training sample set S={{S₊}, {S₋}};

treating process: if a class identifier y_i=+1, then

${\alpha }_i^{+}=\frac{1}{M};$ otherwise, α_i⁺=0;

if a class identifier y_i=−1, then

${\alpha }_i^{-}=\frac{1}{M};$ otherwise, α_i⁻=0; M represents the number of the voltage signal sample vectors collected;

α⁺=[α₁⁺, α₂⁺, . . . , α_2M⁺], α⁻=[α₁⁻, α₂⁻, . . . , α_2M⁻]; and

(4.3.3) computing classifier parameters:

wherein the real number α_i=α_i⁺−α_i⁻; and

the bias b=0.5((α⁺)^TKα⁺−(α⁻)^TKα⁻), wherein (⋅)^T represents transpose of matrix or vector; and K represents to the standardize kernel matrix.

Claims

1. An analog circuit fault mode classification method, comprising: (1) collecting M groups of voltage signal sample vectors Vij at a node to be tested under each of fault modes Fi of the analog circuit by using a data collection board, wherein j=1, 2, . . . , M, i=1, 2, . . . , N, Vij represents a jth voltage signal sample vector of a ith fault mode, and N represents a total number of the fault modes;(2) sequentially extracting fault characteristic vectors VijF of the voltage signal sample vectors Vij working under the fault modes Fi by using subspace projection, wherein i=1, 2, . . . , N, j=1, 2, . . . , M, and VijF represents a fault characteristic vector of the jth voltage signal sample under the ith fault mode;(3) standardizing the extracted fault characteristic vectors VijF to obtain standardized fault characteristic vectors {circumflex over (V)}ijF, wherein a computing method for obtaining the standardized fault characteristic vectors is

2. The analog circuit fault mode classification method according to claim 1, wherein the step of extracting the fault characteristic vectors VijF by using the subspace projection in step (2) comprises: (2.1) computing dimensionality L of the voltage signal sample vectors Vij: L=length(Vij);(2.2) generating an L×L dimensional Toeplitz transformation matrix Φ:

3. The analog circuit fault mode classification method according to claim 1, wherein the specific step of constructing each binary-class support vector machine in step (4) comprises: (4.1) constructing a binary classifier decision model

4. The analog circuit fault mode classification method according to claim 3, wherein the specific step of using the training sample set S to train the binary classifier decision model so as to determine the parameters αi and b of the binary-class support vector machine in step (4.3) comprises: (4.3.1) standardizing a kernel matrix: