Patent Application
20060156097
This invention relates generally to semiconductor memories such as flash memories.
In non-volatile memory design, stringent cycling requirements may pose reliability issues. Generally, a cycle is one program and one erase operation. For instance, a memory may be specified to operate properly through a 100,000 cycles. This means the component must be able to be programmed and erased reliably 100,000 times.
As a part is cycled, many intrinsic properties of the memory degrade, including the minimum drain voltage needed to program the cell. After 100,000 cycles, the minimum drain voltage of the cell is much higher than at zero cycles. On the other hand, there is also a maximum drain voltage that can be applied during programming without disturbing the memory cell. Like the minimum drain voltage, the maximum drain voltage also degrades over cycling. The region between the maximum drain voltage and the minimum drain voltage, that determines the cell's drain voltage during programming, can be called program drain window. So, over cycling, the program drain window is positive in order for the non-volatile memory to program reliably.
As non-volatile memory cells decrease in size, intrinsic properties of the memory cell also become worse than with previous technologies. One property that degrades is the minimum drain voltage of the cell. Since the minimum voltage at time zero is typically set to the minimum drain voltage at a specified lifetime cycle count, the program drain window may be at a deficit. For example, the minimum drain voltage at zero cycles may be higher than the maximum drain voltage at zero cycles. Thus, it would be useful to know how many times a given device has been cycled.
Thus, there is a need for ways to monitor non-volatile memories over their useful life.
Referring to
Generally, in many non-volatile semiconductor memories and, particularly, in flash memories, a block erase may be implemented, where instead of selectively erasing some cells, an entire block of cells is erased and then rewritten with the correct information. In order to determine the number of cycles which the block undergoes, it may be desirable, in one embodiment, to determine when a block erase has been ordered.
Thus, each time an erase is ordered, the program pulse may be provided to the frequency generator 11. In one embodiment, the frequency generator 11 may be a delay chain or string of inverters. In another embodiment, it may be a ring oscillator. The frequency generator 11 produces a pulse of the desired pulse width, such as 500 nanoseconds, each time an erase command is issued or detected by the microcontroller 10 in one embodiment of the present invention.
If the switch 14 is in its closed position, as indicated in
In one embodiment, the counter 16 may be in an otherwise unused row of memory cells associated with the block. For example, in some memories, one or more rows along the edge of the integrated circuit semiconductor memory may never be utilized. An unused row of this type, which may be called a dummy row, may be utilized to implement an analog counter in accordance with some embodiments of the present invention. In such case, an otherwise unused memory row may be utilized to implement an analog counter. Thus, when X counters 16 in an unused memory row are used, each counter counting to N, a total count of X times N, can be detected.
In one embodiment, the counter 16 is a flash memory cell. It has a gate voltage, indicated as VG, which may also correspond to a row voltage, and a drain voltage, indicated as VD, which may correspond to a column voltage. Typically, the counter 16 has its drain, gate, and source biased to place the device in saturation mode. That is, the drain-to-source voltage potential is greater than or equal to the gate-to-source voltage potential minus the threshold voltage of the transistor.
The counter 16 may have a p-well and the n-well connected as indicated. The source may be coupled to ground. Typically, to program the counter 16, the p and n-wells are connected to the source terminal which is tied to ground.
With constant drain, gate, and source voltage applied to the cell, its threshold increases over time. This is shown in
Referring again to
The comparator 20 is coupled to a reference cell 18. In one embodiment of the present invention, the reference cell 18 is another flash memory cell in the same row with the counter 16. It may be preprogrammed to a desired threshold level. Then, when the comparator 20 determines that the threshold voltage of the counter 16 and reference cell 18 are the same, the number of constant width pulses seen by the counter 16 may be determined. In one embodiment, this count corresponds to the number of cycles experienced by a memory block associated with the counter 16.
To facilitate programming of the reference cell 18, in some embodiments, instead of programming it with the number of pulses which equal the desired count to be detected on the counter 16, the cell 18 may be programmed with fewer pulses of greater width.
In the embodiment depicted in
The frequency generator 11 may program the counter 16 after an erase has already been completed on the other cells in a block that includes the counter 16. During the erase cycle for the other cells in the block, the counter 16 and the reference cell 18 are not erased. If they were erased, they would lose the count and the reference level needed to determine when the counter 16 reaches the desired count. After the desired count or threshold voltage has been reached, then the reference cell 18 and the counter 16 may be erased in some cases.
Referring to
To make this determination, the switch 14 is opened, the switch 44 is closed, the switch 45 is closed, and the comparator 20 is turned on. As a result, the threshold voltage of the counter 16 can be compared to the threshold voltage of the preprogrammed reference cell 18.
Referring to
Referring to
To erase the other cells, their gates are biased negatively to repel charge off their floating gates in a flash memory embodiment. At this time, the counter row R1 may be turned off by applying zero or positive volts to the row R1.
Then, the counter 16 may be selected as indicated in block 68. The selection may be implemented by the switch 14 in particular and by the application of the gate voltage to the row R1. At this point, after an erase has occurred, the other cells in the block may be deselected as indicated in block 70.
Then, the program pulse may be issued by the microcontroller 10 to the frequency generator 11 as indicated in block 72. At the same time, the gate of the counter 16 goes positive to attract electrons onto the floating gate and to continue to increase the threshold voltage of the counter 16, for example, according to the characteristic curve illustrated in
Then, the comparator 20 is turned on as indicated in block 74. The switches 44 and 45 are closed as indicated in block 76. The reference cell 18 is selected, as indicated in block 78, by turning on its gate voltage.
A check at diamond 80 determines whether the threshold voltage of the counter 16 equals that of the reference cell 18, indicating that the predetermined count has been reached. If so, an indication is provided (block 82). The indication may be an alert that may be issued to a system by the memory that includes the counter 16. Next, the counter 16 may be erased or reset, as indicated in block 84, in some embodiments. Then the comparator 20 is turned off as indicated in block 86.
Turning to
System 24 may include a controller or processor 28, an input/output (I/O) device 32 (e.g. a keypad, display), a memory 52, a wireless interface 50, and a static random and coupled to each other via a bus 30. The memory 52 may include the counter 16 and its associated block 22. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.
Processor 28 may comprise, for example, one or more microprocessors, digital signal processors, micro-controllers, or the like. Memory 52 may be used to store messages transmitted to or by system 24. Memory 52 may also optionally be used to store instructions that are executed by processor 28 during the operation of system 24, and may be used to store user data. The instructions may be stored as digital information and the user data, as disclosed herein, may be stored in one section of the memory as digital data and in another section as analog memory. As another example, a given section at one time may be labeled as such and store digital information, and then later may be relabeled and reconfigured to store analog information. Memory 52 may be provided by one or more different types of memory. For example, memory 52 may comprise a volatile memory (any type of random access memory), a non-volatile memory such as a flash memory.
The I/O device 32 may be used to generate a message. The system 24 may use the wireless interface 50 to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of the wireless interface 50 may include an antenna, or a wireless transceiver, such as a dipole antenna, although the scope of the present invention is not limited in this respect. Also, the I/O device 32 may deliver a voltage reflecting what is stored as either a digital output (if digital information was stored), or it may be analog information (if analog information was stored).
While an example in a wireless application is provided above, embodiments of the present invention may also be used in non-wireless applications as well.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
